Searched refs:reg_val_GCR (Results 1 - 1 of 1) sorted by relevance
| /linux-4.4.14/sound/soc/ux500/ |
| H A D | ux500_msp_i2s.c | 221 u32 reg_val_GCR; setup_bitclk() local
228 reg_val_GCR = readl(msp->registers + MSP_GCR); setup_bitclk()
229 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR); setup_bitclk()
267 reg_val_GCR = readl(msp->registers + MSP_GCR); setup_bitclk()
268 writel(reg_val_GCR | SRG_ENABLE, msp->registers + MSP_GCR); setup_bitclk()
356 u32 reg_val_DMACR, reg_val_GCR; enable_msp() local
393 reg_val_GCR = readl(msp->registers + MSP_GCR); enable_msp()
394 writel(reg_val_GCR | FRAME_GEN_ENABLE, msp->registers + MSP_GCR); enable_msp()
401 u32 reg_val_DR, reg_val_GCR, reg_val_FLR; flush_fifo_rx() local
404 reg_val_GCR = readl(msp->registers + MSP_GCR); flush_fifo_rx()
405 writel(reg_val_GCR | RX_ENABLE, msp->registers + MSP_GCR); flush_fifo_rx()
413 writel(reg_val_GCR, msp->registers + MSP_GCR); flush_fifo_rx()
418 u32 reg_val_TSTDR, reg_val_GCR, reg_val_FLR; flush_fifo_tx() local
421 reg_val_GCR = readl(msp->registers + MSP_GCR); flush_fifo_tx()
422 writel(reg_val_GCR | TX_ENABLE, msp->registers + MSP_GCR); flush_fifo_tx()
431 writel(reg_val_GCR, msp->registers + MSP_GCR); flush_fifo_tx()
506 u32 reg_val_GCR, reg_val_DMACR, reg_val_IMSC; disable_msp_rx() local
508 reg_val_GCR = readl(msp->registers + MSP_GCR); disable_msp_rx()
509 writel(reg_val_GCR & ~RX_ENABLE, msp->registers + MSP_GCR); disable_msp_rx()
522 u32 reg_val_GCR, reg_val_DMACR, reg_val_IMSC; disable_msp_tx() local
524 reg_val_GCR = readl(msp->registers + MSP_GCR); disable_msp_tx()
525 writel(reg_val_GCR & ~TX_ENABLE, msp->registers + MSP_GCR); disable_msp_tx()
538 u32 reg_val_GCR; disable_msp() local
542 reg_val_GCR = readl(msp->registers + MSP_GCR); disable_msp()
546 reg_val_GCR = readl(msp->registers + MSP_GCR); disable_msp()
547 writel(reg_val_GCR | LOOPBACK_MASK, disable_msp()
577 u32 reg_val_GCR, enable_bit; ux500_msp_i2s_trigger() local
593 reg_val_GCR = readl(msp->registers + MSP_GCR); ux500_msp_i2s_trigger()
594 writel(reg_val_GCR | enable_bit, msp->registers + MSP_GCR); ux500_msp_i2s_trigger()
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