Searched refs:reg_tbl (Results 1 – 11 of 11) sorted by relevance
40 readl(((a)->ahw->pci_base0) + ((a)->ahw->reg_tbl[addr]))44 writel(value, ((a)->ahw->pci_base0) + ((a)->ahw->reg_tbl[addr]))
531 u32 *reg_tbl; member
263 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl; in qlcnic_83xx_register_map()3566 sizeof(*adapter->ahw->reg_tbl)); in qlcnic_83xx_get_regs_len()
654 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl; in qlcnic_sriov_vf_register_map()
2496 ahw->reg_tbl = (u32 *) qlcnic_reg_tbl; in qlcnic_probe()
824 uint32_t *reg_tbl; member1064 return ha->isp_ops->rd_reg_direct(ha, ha->reg_tbl[crb_reg]); in qla4_8xxx_rd_direct()1071 ha->isp_ops->wr_reg_direct(ha, ha->reg_tbl[crb_reg], value); in qla4_8xxx_wr_direct()
452 ha->reg_tbl[QLA8XXX_CRB_DEV_PART_INFO]); in qla4_83xx_can_perform_reset()454 drv_active = qla4_83xx_rd_reg(ha, ha->reg_tbl[QLA8XXX_CRB_DRV_ACTIVE]); in qla4_83xx_can_perform_reset()
8631 ha->reg_tbl = (uint32_t *) qla4_82xx_reg_tbl; in qla4xxx_probe_adapter()8643 ha->reg_tbl = (uint32_t *)qla4_83xx_reg_tbl; in qla4xxx_probe_adapter()
2179 } reg_tbl[] = { in bnx2x_test_registers() local2291 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) { in bnx2x_test_registers()2293 if (!(hw & reg_tbl[i].hw)) in bnx2x_test_registers()2296 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1; in bnx2x_test_registers()2297 mask = reg_tbl[i].mask; in bnx2x_test_registers()
5564 } reg_tbl[] = { in bnx2_test_registers() local5678 for (i = 0; reg_tbl[i].offset != 0xffff; i++) { in bnx2_test_registers()5680 u16 flags = reg_tbl[i].flags; in bnx2_test_registers()5685 offset = (u32) reg_tbl[i].offset; in bnx2_test_registers()5686 rw_mask = reg_tbl[i].rw_mask; in bnx2_test_registers()5687 ro_mask = reg_tbl[i].ro_mask; in bnx2_test_registers()
13045 } reg_tbl[] = { in tg3_test_registers() local13188 for (i = 0; reg_tbl[i].offset != 0xffff; i++) { in tg3_test_registers()13189 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705)) in tg3_test_registers()13192 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705)) in tg3_test_registers()13196 (reg_tbl[i].flags & TG3_FL_NOT_5788)) in tg3_test_registers()13199 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750)) in tg3_test_registers()13202 offset = (u32) reg_tbl[i].offset; in tg3_test_registers()13203 read_mask = reg_tbl[i].read_mask; in tg3_test_registers()13204 write_mask = reg_tbl[i].write_mask; in tg3_test_registers()