Searched refs:reg_offsets (Results 1 – 11 of 11) sorted by relevance
127 struct mv64xxx_i2c_regs reg_offsets; member215 writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset); in mv64xxx_i2c_hw_init()217 drv_data->reg_base + drv_data->reg_offsets.clock); in mv64xxx_i2c_hw_init()218 writel(0, drv_data->reg_base + drv_data->reg_offsets.addr); in mv64xxx_i2c_hw_init()219 writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr); in mv64xxx_i2c_hw_init()221 drv_data->reg_base + drv_data->reg_offsets.control); in mv64xxx_i2c_hw_init()343 drv_data->reg_base + drv_data->reg_offsets.control); in mv64xxx_i2c_send_start()371 drv_data->reg_base + drv_data->reg_offsets.control); in mv64xxx_i2c_do_action()376 drv_data->reg_base + drv_data->reg_offsets.data); in mv64xxx_i2c_do_action()378 drv_data->reg_base + drv_data->reg_offsets.control); in mv64xxx_i2c_do_action()[all …]
148 const unsigned long *reg_offsets; member164 return readb(bs->regs + bs->reg_offsets[offset]); in bcm_spi_readb()171 return ioread16be(bs->regs + bs->reg_offsets[offset]); in bcm_spi_readw()173 return readw(bs->regs + bs->reg_offsets[offset]); in bcm_spi_readw()180 writeb(value, bs->regs + bs->reg_offsets[offset]); in bcm_spi_writeb()187 iowrite16be(value, bs->regs + bs->reg_offsets[offset]); in bcm_spi_writew()189 writew(value, bs->regs + bs->reg_offsets[offset]); in bcm_spi_writew()530 bs->reg_offsets = bcm63xx_spireg; in bcm63xx_spi_probe()531 bs->fifo_size = bs->reg_offsets[SPI_MSG_DATA_SIZE]; in bcm63xx_spi_probe()546 bs->msg_type_shift = bs->reg_offsets[SPI_MSG_TYPE_SHIFT]; in bcm63xx_spi_probe()[all …]
49 static int reg_offsets[32]; variable53 u8 *p = ((u8 *)fp) + reg_offsets[reg]; in get_reg_val()59 u8 *p = ((u8 *)fp) + reg_offsets[reg]; in put_reg_val()214 reg_offsets[r] = offset; in misaligned_calc_reg_offsets()222 reg_offsets[r] = offset; in misaligned_calc_reg_offsets()
162 const unsigned int *reg_offsets; member284 !gpu->reg_offsets[offset_name]) { in adreno_reg_check()293 u32 reg = gpu->reg_offsets[offset_name]; in adreno_gpu_read()303 u32 reg = gpu->reg_offsets[offset_name]; in adreno_gpu_write()
564 adreno_gpu->reg_offsets = a4xx_register_offsets; in a4xx_gpu_init()
565 adreno_gpu->reg_offsets = a3xx_register_offsets; in a3xx_gpu_init()
22 static const int reg_offsets[] = variable110 child->thread.regs.regs.gp[reg_offsets[regno >> 3]] = value; in putreg()174 return mask & child->thread.regs.regs.gp[reg_offsets[regno >> 3]]; in getreg()
54 static const int reg_offsets[] = { variable117 child->thread.regs.regs.gp[reg_offsets[regno]] = value; in putreg()170 return mask & child->thread.regs.regs.gp[reg_offsets[regno]]; in getreg()
26 u32 *reg_offsets; /* register offsets */ member
101 u32 reg_offsets[0x20]; member889 if (ax->plat->reg_offsets) in ax_probe()890 ei_local->reg_offset = ax->plat->reg_offsets; in ax_probe()892 ei_local->reg_offset = ax->reg_offsets; in ax_probe()894 ax->reg_offsets[ret] = (mem_size / 0x18) * ret; in ax_probe()916 if (!ax->plat->reg_offsets) { in ax_probe()918 ax->reg_offsets[ret] = (mem_size / 0x20) * ret; in ax_probe()
140 const u16 *reg_offsets; member438 ctrl->reg_offsets = brcmnand_regs_v71; in brcmnand_revision_init()440 ctrl->reg_offsets = brcmnand_regs_v60; in brcmnand_revision_init()442 ctrl->reg_offsets = brcmnand_regs_v50; in brcmnand_revision_init()444 ctrl->reg_offsets = brcmnand_regs_v40; in brcmnand_revision_init()514 u16 offs = ctrl->reg_offsets[reg]; in brcmnand_read_reg()525 u16 offs = ctrl->reg_offsets[reg]; in brcmnand_write_reg()556 u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE]; in brcmnand_cs_offset()557 u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE]; in brcmnand_cs_offset()929 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE]; in oob_reg_read()[all …]