Searched refs:reg_divider_width (Results 1 – 1 of 1) sorted by relevance
205 u32 reg_divider_width; /* Width of the bit to divider field */ member317 data &= (1 << pclk->param.reg_divider_width) - 1; in xgene_clk_recalc_rate()348 divider &= (1 << pclk->param.reg_divider_width) - 1; in xgene_clk_set_rate()354 data &= ~((1 << pclk->param.reg_divider_width) - 1); in xgene_clk_set_rate()492 ¶meters.reg_divider_width)) in xgene_devclk_init()493 parameters.reg_divider_width = 0; in xgene_devclk_init()