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Searched refs:ref_div (Results 1 – 34 of 34) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Damdgpu_pll.c84 unsigned *fb_div, unsigned *ref_div) in amdgpu_pll_get_fb_ref_div() argument
90 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); in amdgpu_pll_get_fb_ref_div()
91 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); in amdgpu_pll_get_fb_ref_div()
95 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); in amdgpu_pll_get_fb_ref_div()
126 unsigned ref_div_min, ref_div_max, ref_div; in amdgpu_pll_compute() local
201 ref_div_max, &fb_div, &ref_div); in amdgpu_pll_compute()
203 (ref_div * post_div)); in amdgpu_pll_compute()
216 &fb_div, &ref_div); in amdgpu_pll_compute()
220 amdgpu_pll_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); in amdgpu_pll_compute()
228 ref_div *= tmp; in amdgpu_pll_compute()
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Datombios_crtc.c531 u32 ref_div, in amdgpu_atombios_crtc_program_pll() argument
558 args.v1.usRefDiv = cpu_to_le16(ref_div); in amdgpu_atombios_crtc_program_pll()
568 args.v2.usRefDiv = cpu_to_le16(ref_div); in amdgpu_atombios_crtc_program_pll()
578 args.v3.usRefDiv = cpu_to_le16(ref_div); in amdgpu_atombios_crtc_program_pll()
595 args.v5.ucRefDiv = ref_div; in amdgpu_atombios_crtc_program_pll()
625 args.v6.ucRefDiv = ref_div; in amdgpu_atombios_crtc_program_pll()
747 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; in amdgpu_atombios_crtc_set_pll() local
776 &fb_div, &frac_fb_div, &ref_div, &post_div); in amdgpu_atombios_crtc_set_pll()
783 ref_div, fb_div, frac_fb_div, post_div, in amdgpu_atombios_crtc_set_pll()
796 step_size = (4 * amount * ref_div * ((u32)amdgpu_crtc->ss.rate * 2048)) / in amdgpu_atombios_crtc_set_pll()
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Datombios_crtc.h46 u32 ref_div,
Damdgpu_atombios.h43 u32 ref_div; member
Damdgpu_atombios.c967 dividers->ref_div = args.v6_out.ucPllRefDiv; in amdgpu_atombios_get_clock_dividers()
Dci_dpm.c3288 reference_divider = 1 + dividers.ref_div; in ci_calculate_sclk_params()
/linux-4.4.14/arch/mips/ath79/
Dclock.c221 static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac, in ar934x_get_pll_freq() argument
229 do_div(t, ref_div); in ar934x_get_pll_freq()
234 do_div(t, ref_div * frac); in ar934x_get_pll_freq()
247 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; in ar934x_clocks_init() local
268 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) & in ar934x_clocks_init()
275 ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & in ar934x_clocks_init()
284 cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint, in ar934x_clocks_init()
295 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) & in ar934x_clocks_init()
302 ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & in ar934x_clocks_init()
311 ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint, in ar934x_clocks_init()
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/linux-4.4.14/drivers/gpu/drm/radeon/
Dradeon_clocks.c38 uint32_t fb_div, ref_div, post_div, sclk; in radeon_legacy_get_engine_clock() local
45 ref_div = in radeon_legacy_get_engine_clock()
48 if (ref_div == 0) in radeon_legacy_get_engine_clock()
51 sclk = fb_div / ref_div; in radeon_legacy_get_engine_clock()
68 uint32_t fb_div, ref_div, post_div, mclk; in radeon_legacy_get_memory_clock() local
75 ref_div = in radeon_legacy_get_memory_clock()
78 if (ref_div == 0) in radeon_legacy_get_memory_clock()
81 mclk = fb_div / ref_div; in radeon_legacy_get_memory_clock()
351 int ref_div = spll->reference_div; in calc_eng_mem_clock() local
353 if (!ref_div) in calc_eng_mem_clock()
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Dradeon_display.c952 unsigned *fb_div, unsigned *ref_div) in avivo_get_fb_ref_div() argument
958 *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); in avivo_get_fb_ref_div()
959 *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); in avivo_get_fb_ref_div()
963 *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); in avivo_get_fb_ref_div()
994 unsigned ref_div_min, ref_div_max, ref_div; in radeon_compute_pll_avivo() local
1072 ref_div_max, &fb_div, &ref_div); in radeon_compute_pll_avivo()
1074 (ref_div * post_div)); in radeon_compute_pll_avivo()
1087 &fb_div, &ref_div); in radeon_compute_pll_avivo()
1091 avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); in radeon_compute_pll_avivo()
1099 ref_div *= tmp; in radeon_compute_pll_avivo()
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Drv740_dpm.c142 reference_divider = 1 + dividers.ref_div; in rv740_populate_sclk_value()
149 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv740_populate_sclk_value()
217 mpll_ad_func_cntl |= CLKR(dividers.ref_div); in rv740_populate_mclk_value()
234 mpll_dq_func_cntl |= CLKR(dividers.ref_div); in rv740_populate_mclk_value()
253 u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div); in rv740_populate_mclk_value()
Drs780_dpm.c86 r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div); in rs780_initialize_dpm_power_state()
453 if ((min_dividers.ref_div != max_dividers.ref_div) || in rs780_set_engine_clock_scaling()
455 (max_dividers.ref_div != current_max_dividers.ref_div) || in rs780_set_engine_clock_scaling()
987 u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1; in rs780_dpm_debugfs_print_current_performance_level() local
991 (post_div * ref_div); in rs780_dpm_debugfs_print_current_performance_level()
1009 u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1; in rs780_dpm_get_current_sclk() local
1013 (post_div * ref_div); in rs780_dpm_get_current_sclk()
Drv730_dpm.c62 reference_divider = 1 + dividers.ref_div; in rv730_populate_sclk_value()
80 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv730_populate_sclk_value()
140 reference_divider = dividers.ref_div + 1; in rv730_populate_mclk_value()
155 mpll_func_cntl |= MPLL_REF_DIV(dividers.ref_div); in rv730_populate_mclk_value()
Datombios_crtc.c820 u32 ref_div, in atombios_crtc_program_pll() argument
847 args.v1.usRefDiv = cpu_to_le16(ref_div); in atombios_crtc_program_pll()
857 args.v2.usRefDiv = cpu_to_le16(ref_div); in atombios_crtc_program_pll()
867 args.v3.usRefDiv = cpu_to_le16(ref_div); in atombios_crtc_program_pll()
884 args.v5.ucRefDiv = ref_div; in atombios_crtc_program_pll()
913 args.v6.ucRefDiv = ref_div; in atombios_crtc_program_pll()
1063 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; in atombios_crtc_set_pll() local
1095 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
1098 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
1101 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
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Drv770_dpm.c334 reference_divider = dividers->ref_div; in rv770_calculate_fractional_mpll_feedback_divider()
415 if ((dividers.ref_div < 1) || (dividers.ref_div > 5)) in rv770_populate_mclk_value()
433 mpll_ad_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]); in rv770_populate_mclk_value()
461 mpll_dq_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]); in rv770_populate_mclk_value()
511 reference_divider = 1 + dividers.ref_div; in rv770_populate_sclk_value()
527 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in rv770_populate_sclk_value()
811 (MPLL_LOCK_TIME(R600_MPLLLOCKTIME_DFLT * pi->ref_div) | in rv770_program_mpll_timing_parameters()
2376 pi->ref_div = dividers.ref_div + 1; in rv770_dpm_init()
2378 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; in rv770_dpm_init()
Drv6xx_dpm.c531 (dividers->ref_div + 1); in rv6xx_calculate_vco_frequency()
568 (ref_clk / (dividers.ref_div + 1)), in rv6xx_program_engine_spread_spectrum()
574 (ref_clk / (dividers.ref_div + 1))); in rv6xx_program_engine_spread_spectrum()
607 rv6xx_memory_clock_entry_set_reference_divider(rdev, entry, dividers.ref_div); in rv6xx_program_mclk_stepping_entry()
686 (ref_clk / (dividers.ref_div + 1)), in rv6xx_program_mclk_spread_spectrum_parameters()
692 (ref_clk / (dividers.ref_div + 1))); in rv6xx_program_mclk_spread_spectrum_parameters()
1960 pi->spll_ref_div = dividers.ref_div + 1; in rv6xx_dpm_init()
1967 pi->mpll_ref_div = dividers.ref_div + 1; in rv6xx_dpm_init()
Dradeon_legacy_crtc.c262 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, in radeon_compute_pll_gain() argument
267 if (!ref_div) in radeon_compute_pll_gain()
270 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div; in radeon_compute_pll_gain()
Drv770_dpm.h114 u32 ref_div; member
Dcypress_dpm.c519 mpll_ad_func_cntl |= CLKR(dividers.ref_div); in cypress_populate_mclk_value()
536 mpll_dq_func_cntl |= CLKR(dividers.ref_div); in cypress_populate_mclk_value()
560 u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div); in cypress_populate_mclk_value()
2058 pi->ref_div = dividers.ref_div + 1; in cypress_dpm_init()
2060 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; in cypress_dpm_init()
Dni_dpm.c2022 reference_divider = 1 + dividers.ref_div; in ni_calculate_sclk_params()
2030 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in ni_calculate_sclk_params()
2202 mpll_ad_func_cntl |= CLKR(dividers.ref_div); in ni_populate_mclk_value()
2219 mpll_dq_func_cntl |= CLKR(dividers.ref_div); in ni_populate_mclk_value()
2243 u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div); in ni_populate_mclk_value()
4105 pi->ref_div = dividers.ref_div + 1; in ni_dpm_init()
4107 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; in ni_dpm_init()
Dbtc_dpm.c2608 pi->ref_div = dividers.ref_div + 1; in btc_dpm_init()
2610 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; in btc_dpm_init()
Dr600.c199 unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; in r600_set_uvd_clocks() local
222 ref_div = 34; in r600_set_uvd_clocks()
224 ref_div = 4; in r600_set_uvd_clocks()
227 ref_div + 1, 0xFFF, 2, 30, ~0, in r600_set_uvd_clocks()
252 UPLL_REF_DIV(ref_div), in r600_set_uvd_clocks()
Dradeon_mode.h599 u32 ref_div; member
Dradeon_atombios.c2864 dividers->ref_div = args.v2.ucAction; in radeon_atom_get_clock_dividers()
2884 dividers->ref_div = args.v3.ucRefDiv; in radeon_atom_get_clock_dividers()
2904 dividers->ref_div = args.v5.ucRefDiv; in radeon_atom_get_clock_dividers()
2929 dividers->ref_div = args.v6_out.ucPllRefDiv; in radeon_atom_get_clock_dividers()
Dsi_dpm.c4818 reference_divider = 1 + dividers.ref_div; in si_calculate_sclk_params()
4825 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); in si_calculate_sclk_params()
6982 pi->ref_div = dividers.ref_div + 1; in si_dpm_init()
6984 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; in si_dpm_init()
Dci_dpm.c3150 reference_divider = 1 + dividers.ref_div; in ci_calculate_sclk_params()
/linux-4.4.14/arch/mips/netlogic/xlp/
Dnlm_hal.c311 u32 mdiv, fdiv, pll_out_freq_den, reg_select, ref_div, pic_div; in nlm_xlp2_get_pic_frequency() local
328 ref_div = 3; in nlm_xlp2_get_pic_frequency()
332 ref_div = 1; in nlm_xlp2_get_pic_frequency()
336 ref_div = 1; in nlm_xlp2_get_pic_frequency()
340 ref_div = 3; in nlm_xlp2_get_pic_frequency()
432 pll_out_freq_den = (1 << vco_post_div) * pll_post_div * ref_div; in nlm_xlp2_get_pic_frequency()
/linux-4.4.14/drivers/media/dvb-frontends/
Dtda8261.c84 static const u8 ref_div[] = { 0x00, 0x01, 0x02, 0x05, 0x07 }; variable
136 buf[2] = (0x01 << 7) | ((ref_div[config->step_size] & 0x07) << 1); in tda8261_set_state()
/linux-4.4.14/drivers/net/wireless/ath/ath9k/
Dar9002_phy.c306 int ref_div = 5; in ar9002_hw_compute_pll_control() local
312 ref_div = 10; in ar9002_hw_compute_pll_control()
319 pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV); in ar9002_hw_compute_pll_control()
/linux-4.4.14/drivers/video/fbdev/aty/
Dradeon_base.c583 unsigned sclk, mclk, tmp, ref_div; in radeon_probe_pll_params() local
697 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff; in radeon_probe_pll_params()
707 rinfo->pll.ref_div = ref_div; in radeon_probe_pll_params()
776 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; in radeon_get_pllinfo()
799 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10); in radeon_get_pllinfo()
834 rinfo->pll.ref_div, in radeon_get_pllinfo()
1629 rinfo->pll.ref_div, rinfo->pll.ref_clk, in radeon_calc_pll_regs()
1639 rinfo->pll.ref_div, rinfo->pll.ref_clk, in radeon_calc_pll_regs()
1642 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq, in radeon_calc_pll_regs()
1644 regs->ppll_ref_div = rinfo->pll.ref_div; in radeon_calc_pll_regs()
Datyfb.h50 int ref_div; member
Dradeonfb.h141 int ref_div; member
Dradeon_pm.c1647 tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div; in radeon_pm_restore_pixel_pll()
2192 OUTPLL(pllPPLL_REF_DIV, rinfo->pll.ref_div); in radeon_reinitialize_M9P()
2449 tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div;
Dradeon_monitor.c668 rinfo->panel_info.ref_divider = rinfo->pll.ref_div; in radeon_fixup_panel_info()
Datyfb_base.c3404 par->pll_limits.ref_div = pll_block.ref_divider; in init_from_bios()