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Searched refs:ref_and_mask (Results 1 – 7 of 7) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/radeon/
Dcik_sdma.c175 u32 ref_and_mask; in cik_sdma_hdp_flush_ring_emit() local
178 ref_and_mask = SDMA0; in cik_sdma_hdp_flush_ring_emit()
180 ref_and_mask = SDMA1; in cik_sdma_hdp_flush_ring_emit()
185 radeon_ring_write(ring, ref_and_mask); /* reference */ in cik_sdma_hdp_flush_ring_emit()
186 radeon_ring_write(ring, ref_and_mask); /* mask */ in cik_sdma_hdp_flush_ring_emit()
Dcik.c3920 u32 ref_and_mask; in cik_hdp_flush_cp_ring_emit() local
3928 ref_and_mask = CP2 << ring->pipe; in cik_hdp_flush_cp_ring_emit()
3931 ref_and_mask = CP6 << ring->pipe; in cik_hdp_flush_cp_ring_emit()
3938 ref_and_mask = CP0; in cik_hdp_flush_cp_ring_emit()
3948 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()
3949 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Dsdma_v2_4.c285 u32 ref_and_mask = 0; in sdma_v2_4_ring_emit_hdp_flush() local
288 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); in sdma_v2_4_ring_emit_hdp_flush()
290 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); in sdma_v2_4_ring_emit_hdp_flush()
297 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v2_4_ring_emit_hdp_flush()
298 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v2_4_ring_emit_hdp_flush()
Dsdma_v3_0.c395 u32 ref_and_mask = 0; in sdma_v3_0_ring_emit_hdp_flush() local
398 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); in sdma_v3_0_ring_emit_hdp_flush()
400 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); in sdma_v3_0_ring_emit_hdp_flush()
407 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v3_0_ring_emit_hdp_flush()
408 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v3_0_ring_emit_hdp_flush()
Dcik_sdma.c249 u32 ref_and_mask; in cik_sdma_ring_emit_hdp_flush() local
252 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK; in cik_sdma_ring_emit_hdp_flush()
254 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK; in cik_sdma_ring_emit_hdp_flush()
259 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in cik_sdma_ring_emit_hdp_flush()
260 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in cik_sdma_ring_emit_hdp_flush()
Dgfx_v8_0.c4512 u32 ref_and_mask, reg_mem_engine; in gfx_v8_0_ring_emit_hdp_flush() local
4517 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; in gfx_v8_0_ring_emit_hdp_flush()
4520 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; in gfx_v8_0_ring_emit_hdp_flush()
4527 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; in gfx_v8_0_ring_emit_hdp_flush()
4537 amdgpu_ring_write(ring, ref_and_mask); in gfx_v8_0_ring_emit_hdp_flush()
4538 amdgpu_ring_write(ring, ref_and_mask); in gfx_v8_0_ring_emit_hdp_flush()
Dgfx_v7_0.c2420 u32 ref_and_mask; in gfx_v7_0_ring_emit_hdp_flush() local
2426 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; in gfx_v7_0_ring_emit_hdp_flush()
2429 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; in gfx_v7_0_ring_emit_hdp_flush()
2435 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; in gfx_v7_0_ring_emit_hdp_flush()
2444 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
2445 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()