/linux-4.4.14/drivers/staging/rdma/hfi1/ |
H A D | eprom.c | 110 read_csr(dd, ASIC_GPIO_OUT) | EPROM_WP_N); write_enable() 113 read_csr(dd, ASIC_GPIO_OE) | EPROM_WP_N); write_enable() 123 read_csr(dd, ASIC_GPIO_OUT) & ~EPROM_WP_N); write_disable() 126 read_csr(dd, ASIC_GPIO_OE) & ~EPROM_WP_N); write_disable() 145 reg = read_csr(dd, ASIC_EEP_DATA); wait_for_not_busy() 169 return (u32)read_csr(dd, ASIC_EEP_DATA); read_device_id() 234 result[i] = (u32)read_csr(dd, ASIC_EEP_DATA); read_page()
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H A D | firmware.c | 258 while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS) __read_8051_data() 270 *result = read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_RD_DATA); __read_8051_data() 343 while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS) write_8051() 703 status = (read_csr(dd, MISC_CFG_FW_CTRL) run_rsa() 738 status = (read_csr(dd, MISC_CFG_FW_CTRL) run_rsa() 785 reg = read_csr(dd, MISC_ERR_STATUS); run_rsa() 814 u64 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE); get_firmware_state() 1010 reg = read_csr(dd, ASIC_STS_SBUS_RESULT); sbus_request_slow() 1014 u64 counts = read_csr(dd, ASIC_STS_SBUS_COUNTERS); sbus_request_slow() 1027 reg = read_csr(dd, ASIC_STS_SBUS_RESULT); sbus_request_slow() 1032 reg = read_csr(dd, ASIC_STS_SBUS_RESULT); sbus_request_slow() 1037 reg = read_csr(dd, ASIC_STS_SBUS_RESULT); sbus_request_slow() 1186 user = (u8)read_csr(dd, ASIC_CFG_MUTEX); acquire_hw_mutex() 1224 reg = read_csr(dd, ASIC_STS_SBUS_COUNTERS); clear_sbus_fast_mode() 1230 reg = read_csr(dd, ASIC_STS_SBUS_COUNTERS); clear_sbus_fast_mode() 1602 (void) read_csr(dd, CCE_DC_CTRL); read_guid() 1604 dd->base_guid = read_csr(dd, DC_DC8051_CFG_LOCAL_GUID); read_guid()
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H A D | intr.c | 139 read_csr(dd, handle_linkup_change() 142 read_csr(dd, DC_DC8051_STS_REMOTE_NODE_TYPE) & handle_linkup_change() 145 read_csr(dd, DC_DC8051_STS_REMOTE_PORT_NO) & handle_linkup_change()
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H A D | chip.c | 1250 u64 read_csr(const struct hfi1_devdata *dd, u32 offset) read_csr() function 1281 ret = read_csr(dd, csr); read_write_csr() 2312 u64 src = read_csr(dd, SEND_EGRESS_ERR_SOURCE); /* read first */ handle_send_egress_err_info() 2313 u64 info = read_csr(dd, SEND_EGRESS_ERR_INFO); handle_send_egress_err_info() 2831 reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_1); handle_8051_request() 2960 dd->lcb_err_en = read_csr(dd, DC_LCB_ERR_EN); lcb_shutdown() 2961 reg = read_csr(dd, DCC_CFG_RESET); lcb_shutdown() 2966 (void) read_csr(dd, DCC_CFG_RESET); /* make sure the write completed */ lcb_shutdown() 3180 rcvctrl = read_csr(dd, RCV_CTRL); adjust_rcvctrl() 3248 reg = read_csr(dd, CCE_STATUS); wait_for_freeze_status() 3805 reg = read_csr(dd, SEND_CM_CTRL); handle_verify_cap() 3868 reg = read_csr(dd, DC_LCB_CFG_LINK_KILL_EN); handle_verify_cap() 3882 read_csr(dd, DC_DC8051_STS_REMOTE_GUID); handle_verify_cap() 3883 ppd->neighbor_port_number = read_csr(dd, DC_DC8051_STS_REMOTE_PORT_NO) & handle_verify_cap() 3886 read_csr(dd, DC_DC8051_STS_REMOTE_NODE_TYPE) & handle_verify_cap() 3889 read_csr(dd, DC_DC8051_STS_REMOTE_FM_SECURITY) & handle_verify_cap() 4022 info = read_csr(dd, DC_DC8051_DBG_ERR_INFO_SET_BY_8051); handle_8051_interrupt() 4119 read_csr(dd, DC_DC8051_ERR_EN) handle_8051_interrupt() 4200 info = read_csr(dd, DCC_ERR_INFO_UNCORRECTABLE); handle_dcc_err() 4219 info = read_csr(dd, DCC_ERR_INFO_FMCONFIG); handle_dcc_err() 4269 info = read_csr(dd, DCC_ERR_INFO_PORTRCV); handle_dcc_err() 4270 hdr0 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR0); handle_dcc_err() 4271 hdr1 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR1); handle_dcc_err() 4543 regs[i] = read_csr(dd, CCE_INT_STATUS + (8 * i)) & general_interrupt() 4573 /* This read_csr is really bad in the hot path */ sdma_interrupt() 4574 status = read_csr(dd, sdma_interrupt() 4605 (void)read_csr(dd, addr); clear_recv_intr() 4703 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE); read_physical_state() 4712 reg = read_csr(dd, DCC_CFG_PORT_CONFIG); read_logical_state() 4721 reg = read_csr(dd, DCC_CFG_PORT_CONFIG); set_logical_state() 4738 *data = read_csr(dd, addr); read_lcb_via_8051() 4768 *data = read_csr(dd, addr); read_lcb_csr() 4879 reg = read_csr(dd, DC_DC8051_CFG_HOST_CMD_1); do_8051_command() 4899 *out_data |= (read_csr(dd, DC_DC8051_CFG_EXT_DEV_1) do_8051_command() 5311 reg = read_csr(dd, do_quick_linkup() 5395 (read_csr(dd, DC_DC8051_CFG_MODE) | DISABLE_SELF_GUID_CHECK)); init_loopback() 5576 qsfp_mask = read_csr(dd, reset_qsfp() 5583 qsfp_mask = read_csr(dd, reset_qsfp() 6185 len1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG); set_send_length() 6198 u64 c1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG1); set_lidlmc() 6960 u64 reg = read_csr(dd, csr); read_one_cm_vl() 6989 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); get_buffer_control() 7006 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_15_0); get_sc2vlnt() 7014 reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_31_16); get_sc2vlnt() 7088 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); set_global_shared() 7099 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT); set_global_limit() 7116 reg = read_csr(dd, addr); set_vl_shared() 7133 reg = read_csr(dd, addr); set_vl_dedicated() 7148 reg = read_csr(dd, SEND_CM_CREDIT_USED_STATUS) & mask; wait_for_vl_status_clear() 8620 qsfp_oe = read_csr(dd, target_oe); hfi1_gpio_mod() 8629 return read_csr(dd, target ? ASIC_QSFP2_IN : ASIC_QSFP1_IN); hfi1_gpio_mod() 8669 reg = read_csr(dd, ASIC_STS_THERM); hfi1_tempsense_rd() 8711 cce_int_mask = read_csr(dd, CCE_INT_MASK + set_intr_state() 8819 reg = read_csr(dd, CCE_INT_MAP + (8*m)); remap_intr() 9353 reg = read_csr(dd, CCE_STATUS); clear_cce_status() 9363 reg = read_csr(dd, CCE_STATUS); clear_cce_status() 9665 reg = read_csr(dd, RCV_STATUS); init_rbufs() 9694 read_csr(dd, RCV_CTRL); init_rbufs() 9701 reg = read_csr(dd, RCV_STATUS); init_rbufs() 9893 (void) read_csr(dd, CCE_DC_CTRL); init_chip() 10510 dd->revision = read_csr(dd, CCE_REVISION); hfi1_init_dd() 10523 reg = read_csr(dd, CCE_REVISION2); hfi1_init_dd() 10540 dd->chip_rcv_contexts = read_csr(dd, RCV_CONTEXTS); hfi1_init_dd() 10541 dd->chip_send_contexts = read_csr(dd, SEND_CONTEXTS); hfi1_init_dd() 10542 dd->chip_sdma_engines = read_csr(dd, SEND_DMA_ENGINES); hfi1_init_dd() 10543 dd->chip_pio_mem_size = read_csr(dd, SEND_PIO_MEM_SIZE); hfi1_init_dd() 10544 dd->chip_sdma_mem_size = read_csr(dd, SEND_DMA_MEM_SIZE); hfi1_init_dd()
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H A D | pcie.c | 211 dd->chip_rcv_array_count = read_csr(dd, RCV_ARRAY_CNT); hfi1_pcie_ddinit() 864 read_csr(dd, ASIC_PCIE_SD_HOST_CMD); arm_gasket_logic() 941 therm = read_csr(dd, ASIC_CFG_THERM_POLL_EN); do_pcie_gen3_transition() 1132 (void) read_csr(dd, CCE_DC_CTRL); /* DC reset hold */ do_pcie_gen3_transition() 1134 fw_ctrl = read_csr(dd, MISC_CFG_FW_CTRL); do_pcie_gen3_transition() 1191 reg = read_csr(dd, ASIC_PCIE_SD_HOST_STATUS); do_pcie_gen3_transition()
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H A D | chip.h | 552 u64 read_csr(const struct hfi1_devdata *dd, u32 offset); 564 return read_csr(dd, offset0 + (0x100 * ctxt)); read_kctxt_csr() 599 return read_csr(dd, offset0 + (0x1000 * ctxt)); read_uctxt_csr()
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H A D | pio.c | 73 sendctrl = read_csr(dd, SEND_CTRL); __cm_reset() 97 reg = read_csr(dd, SEND_CTRL); pio_send_control() 133 (void) read_csr(dd, SEND_CTRL); /* flush write */ pio_send_control() 931 reg = read_csr(dd, sc->hw_context * 8 + sc_wait_for_packet_egress() 1125 reg = read_csr(dd, SEND_PIO_INIT_CTXT); pio_init_wait_progress()
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H A D | qsfp.c | 409 reg = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_IN : ASIC_QSFP1_IN); qsfp_mod_present()
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H A D | mad.c | 1443 *val++ = read_csr(dd, SEND_SC2VLT0); get_sc2vlt_tables() 1444 *val++ = read_csr(dd, SEND_SC2VLT1); get_sc2vlt_tables() 1445 *val++ = read_csr(dd, SEND_SC2VLT2); get_sc2vlt_tables() 1446 *val++ = read_csr(dd, SEND_SC2VLT3); get_sc2vlt_tables() 2706 cpu_to_be64(read_csr(dd, DCC_PRF_PORT_VL_MARK_FECN_CNT pma_get_opa_datacounters() 2893 reg = read_csr(dd, RCV_ERR_INFO); pma_get_opa_errorinfo() 3466 reg = read_csr(dd, DCC_CFG_LED_CNTRL); __subn_get_opa_led_info()
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H A D | sdma.c | 317 reg = read_csr(dd, off + SEND_EGRESS_SEND_DMA_STATUS); sdma_wait_for_packet_egress() 1758 csr = read_csr(sde->dd, reg); \ 1769 csr = read_csr(sde->dd, reg + (8 * i)); \
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H A D | diag.c | 708 dd->hfi1_snoop.dcc_cfg = read_csr(dd, DCC_CFG_PORT_CONFIG1); hfi1_snoop_open()
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/linux-4.4.14/drivers/net/ethernet/amd/ |
H A D | pcnet32.c | 246 u16 (*read_csr) (unsigned long, int); member in struct:pcnet32_access 383 .read_csr = pcnet32_wio_read_csr, 438 .read_csr = pcnet32_dwio_read_csr, 463 val = lp->a->read_csr(ioaddr, CSR3); pcnet32_netif_start() 957 x = a->read_csr(ioaddr, CSR15) & 0xfffc; pcnet32_loopback_test() 1015 x = a->read_csr(ioaddr, CSR15); pcnet32_loopback_test() 1087 csr5 = a->read_csr(ioaddr, CSR5); pcnet32_suspend() 1092 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) { pcnet32_suspend() 1359 val = lp->a->read_csr(ioaddr, CSR3); pcnet32_poll() 1393 csr0 = a->read_csr(ioaddr, CSR0); pcnet32_get_regs() 1403 *buff++ = a->read_csr(ioaddr, i); pcnet32_get_regs() 1405 *buff++ = a->read_csr(ioaddr, 112); pcnet32_get_regs() 1406 *buff++ = a->read_csr(ioaddr, 114); pcnet32_get_regs() 1435 csr5 = a->read_csr(ioaddr, CSR5); pcnet32_get_regs() 1574 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16); pcnet32_probe1() 1666 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00); pcnet32_probe1() 1716 val = a->read_csr(ioaddr, i + 12) & 0x0ffff; pcnet32_probe1() 1746 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */ pcnet32_probe1() 2092 val = lp->a->read_csr(ioaddr, 124) & ~0x10; pcnet32_open() 2197 val = lp->a->read_csr(ioaddr, CSR3); pcnet32_open() 2231 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON) pcnet32_open() 2243 lp->a->read_csr(ioaddr, CSR0)); pcnet32_open() 2374 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_STOP) pcnet32_restart() 2389 if (lp->a->read_csr(ioaddr, CSR0) & CSR0_IDON) pcnet32_restart() 2404 dev->name, lp->a->read_csr(ioaddr, CSR0)); pcnet32_tx_timeout() 2448 __func__, lp->a->read_csr(ioaddr, CSR0)); pcnet32_start_xmit() 2509 csr0 = lp->a->read_csr(ioaddr, CSR0); pcnet32_interrupt() 2518 csr0, lp->a->read_csr(ioaddr, CSR0)); pcnet32_interrupt() 2545 val = lp->a->read_csr(ioaddr, CSR3); pcnet32_interrupt() 2552 csr0 = lp->a->read_csr(ioaddr, CSR0); pcnet32_interrupt() 2557 lp->a->read_csr(ioaddr, CSR0)); pcnet32_interrupt() 2577 dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112); pcnet32_close() 2581 lp->a->read_csr(ioaddr, CSR0)); pcnet32_close() 2613 dev->stats.rx_missed_errors = lp->a->read_csr(ioaddr, 112); pcnet32_get_stats() 2666 csr15 = lp->a->read_csr(ioaddr, CSR15); pcnet32_set_multicast_list() 2684 csr5 = lp->a->read_csr(ioaddr, CSR5); pcnet32_set_multicast_list()
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/linux-4.4.14/drivers/firewire/ |
H A D | core.h | 90 u32 (*read_csr)(struct fw_card *card, int csr_offset); member in struct:fw_card_driver
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H A D | core-transaction.c | 1118 *data = cpu_to_be32(card->driver->read_csr(card, reg)); handle_registers()
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H A D | core-cdev.c | 1214 cycle_time = card->driver->read_csr(card, CSR_CYCLE_TIME); ioctl_get_cycle_timer2()
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H A D | ohci.c | 3518 .read_csr = ohci_read_csr,
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