Searched refs:ratesArray (Results 1 - 3 of 3) sorted by relevance

/linux-4.4.14/drivers/net/wireless/ath/ath9k/
H A Deeprom_9287.c549 int16_t *ratesArray, ath9k_hw_set_ar9287_power_per_rate_table()
723 ratesArray[rate6mb] = ath9k_hw_set_ar9287_power_per_rate_table()
724 ratesArray[rate9mb] = ath9k_hw_set_ar9287_power_per_rate_table()
725 ratesArray[rate12mb] = ath9k_hw_set_ar9287_power_per_rate_table()
726 ratesArray[rate18mb] = ath9k_hw_set_ar9287_power_per_rate_table()
727 ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0]; ath9k_hw_set_ar9287_power_per_rate_table()
729 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; ath9k_hw_set_ar9287_power_per_rate_table()
730 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; ath9k_hw_set_ar9287_power_per_rate_table()
731 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; ath9k_hw_set_ar9287_power_per_rate_table()
732 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; ath9k_hw_set_ar9287_power_per_rate_table()
735 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; ath9k_hw_set_ar9287_power_per_rate_table()
738 ratesArray[rate1l] = targetPowerCck.tPow2x[0]; ath9k_hw_set_ar9287_power_per_rate_table()
739 ratesArray[rate2s] = ath9k_hw_set_ar9287_power_per_rate_table()
740 ratesArray[rate2l] = targetPowerCck.tPow2x[1]; ath9k_hw_set_ar9287_power_per_rate_table()
741 ratesArray[rate5_5s] = ath9k_hw_set_ar9287_power_per_rate_table()
742 ratesArray[rate5_5l] = targetPowerCck.tPow2x[2]; ath9k_hw_set_ar9287_power_per_rate_table()
743 ratesArray[rate11s] = ath9k_hw_set_ar9287_power_per_rate_table()
744 ratesArray[rate11l] = targetPowerCck.tPow2x[3]; ath9k_hw_set_ar9287_power_per_rate_table()
748 ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i]; ath9k_hw_set_ar9287_power_per_rate_table()
750 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; ath9k_hw_set_ar9287_power_per_rate_table()
751 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; ath9k_hw_set_ar9287_power_per_rate_table()
752 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; ath9k_hw_set_ar9287_power_per_rate_table()
755 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; ath9k_hw_set_ar9287_power_per_rate_table()
770 int16_t ratesArray[Ar5416RateSize]; ath9k_hw_ar9287_set_txpower() local
774 memset(ratesArray, 0, sizeof(ratesArray)); ath9k_hw_ar9287_set_txpower()
781 &ratesArray[0], cfgCtl, ath9k_hw_ar9287_set_txpower()
788 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { ath9k_hw_ar9287_set_txpower()
789 if (ratesArray[i] > MAX_RATE_POWER) ath9k_hw_ar9287_set_txpower()
790 ratesArray[i] = MAX_RATE_POWER; ath9k_hw_ar9287_set_txpower()
792 if (ratesArray[i] > regulatory->max_power_level) ath9k_hw_ar9287_set_txpower()
793 regulatory->max_power_level = ratesArray[i]; ath9k_hw_ar9287_set_txpower()
802 ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2; ath9k_hw_ar9287_set_txpower()
808 ATH9K_POW_SM(ratesArray[rate18mb], 24) ath9k_hw_ar9287_set_txpower()
809 | ATH9K_POW_SM(ratesArray[rate12mb], 16) ath9k_hw_ar9287_set_txpower()
810 | ATH9K_POW_SM(ratesArray[rate9mb], 8) ath9k_hw_ar9287_set_txpower()
811 | ATH9K_POW_SM(ratesArray[rate6mb], 0)); ath9k_hw_ar9287_set_txpower()
814 ATH9K_POW_SM(ratesArray[rate54mb], 24) ath9k_hw_ar9287_set_txpower()
815 | ATH9K_POW_SM(ratesArray[rate48mb], 16) ath9k_hw_ar9287_set_txpower()
816 | ATH9K_POW_SM(ratesArray[rate36mb], 8) ath9k_hw_ar9287_set_txpower()
817 | ATH9K_POW_SM(ratesArray[rate24mb], 0)); ath9k_hw_ar9287_set_txpower()
822 ATH9K_POW_SM(ratesArray[rate2s], 24) ath9k_hw_ar9287_set_txpower()
823 | ATH9K_POW_SM(ratesArray[rate2l], 16) ath9k_hw_ar9287_set_txpower()
824 | ATH9K_POW_SM(ratesArray[rateXr], 8) ath9k_hw_ar9287_set_txpower()
825 | ATH9K_POW_SM(ratesArray[rate1l], 0)); ath9k_hw_ar9287_set_txpower()
827 ATH9K_POW_SM(ratesArray[rate11s], 24) ath9k_hw_ar9287_set_txpower()
828 | ATH9K_POW_SM(ratesArray[rate11l], 16) ath9k_hw_ar9287_set_txpower()
829 | ATH9K_POW_SM(ratesArray[rate5_5s], 8) ath9k_hw_ar9287_set_txpower()
830 | ATH9K_POW_SM(ratesArray[rate5_5l], 0)); ath9k_hw_ar9287_set_txpower()
835 ATH9K_POW_SM(ratesArray[rateHt20_3], 24) ath9k_hw_ar9287_set_txpower()
836 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16) ath9k_hw_ar9287_set_txpower()
837 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8) ath9k_hw_ar9287_set_txpower()
838 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)); ath9k_hw_ar9287_set_txpower()
841 ATH9K_POW_SM(ratesArray[rateHt20_7], 24) ath9k_hw_ar9287_set_txpower()
842 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16) ath9k_hw_ar9287_set_txpower()
843 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8) ath9k_hw_ar9287_set_txpower()
844 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)); ath9k_hw_ar9287_set_txpower()
850 ATH9K_POW_SM(ratesArray[rateHt40_3], 24) ath9k_hw_ar9287_set_txpower()
851 | ATH9K_POW_SM(ratesArray[rateHt40_2], 16) ath9k_hw_ar9287_set_txpower()
852 | ATH9K_POW_SM(ratesArray[rateHt40_1], 8) ath9k_hw_ar9287_set_txpower()
853 | ATH9K_POW_SM(ratesArray[rateHt40_0], 0)); ath9k_hw_ar9287_set_txpower()
856 ATH9K_POW_SM(ratesArray[rateHt40_7], 24) ath9k_hw_ar9287_set_txpower()
857 | ATH9K_POW_SM(ratesArray[rateHt40_6], 16) ath9k_hw_ar9287_set_txpower()
858 | ATH9K_POW_SM(ratesArray[rateHt40_5], 8) ath9k_hw_ar9287_set_txpower()
859 | ATH9K_POW_SM(ratesArray[rateHt40_4], 0)); ath9k_hw_ar9287_set_txpower()
862 ATH9K_POW_SM(ratesArray[rateHt40_3] + ath9k_hw_ar9287_set_txpower()
864 | ATH9K_POW_SM(ratesArray[rateHt40_2] + ath9k_hw_ar9287_set_txpower()
866 | ATH9K_POW_SM(ratesArray[rateHt40_1] + ath9k_hw_ar9287_set_txpower()
868 | ATH9K_POW_SM(ratesArray[rateHt40_0] + ath9k_hw_ar9287_set_txpower()
872 ATH9K_POW_SM(ratesArray[rateHt40_7] + ath9k_hw_ar9287_set_txpower()
874 | ATH9K_POW_SM(ratesArray[rateHt40_6] + ath9k_hw_ar9287_set_txpower()
876 | ATH9K_POW_SM(ratesArray[rateHt40_5] + ath9k_hw_ar9287_set_txpower()
878 | ATH9K_POW_SM(ratesArray[rateHt40_4] + ath9k_hw_ar9287_set_txpower()
884 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) ath9k_hw_ar9287_set_txpower()
885 | ATH9K_POW_SM(ratesArray[rateExtCck], 16) ath9k_hw_ar9287_set_txpower()
886 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) ath9k_hw_ar9287_set_txpower()
887 | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); ath9k_hw_ar9287_set_txpower()
895 ar5008_hw_init_rate_txpower(ah, ratesArray, chan, ht40_delta); ath9k_hw_ar9287_set_txpower()
547 ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah, struct ath9k_channel *chan, int16_t *ratesArray, u16 cfgCtl, u16 antenna_reduction, u16 powerLimit) ath9k_hw_set_ar9287_power_per_rate_table() argument
H A Deeprom_def.c967 int16_t *ratesArray, ath9k_hw_set_def_power_per_rate_table()
1153 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = ath9k_hw_set_def_power_per_rate_table()
1154 ratesArray[rate18mb] = ratesArray[rate24mb] = ath9k_hw_set_def_power_per_rate_table()
1156 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; ath9k_hw_set_def_power_per_rate_table()
1157 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; ath9k_hw_set_def_power_per_rate_table()
1158 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; ath9k_hw_set_def_power_per_rate_table()
1159 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; ath9k_hw_set_def_power_per_rate_table()
1162 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; ath9k_hw_set_def_power_per_rate_table()
1165 ratesArray[rate1l] = targetPowerCck.tPow2x[0]; ath9k_hw_set_def_power_per_rate_table()
1166 ratesArray[rate2s] = ratesArray[rate2l] = ath9k_hw_set_def_power_per_rate_table()
1168 ratesArray[rate5_5s] = ratesArray[rate5_5l] = ath9k_hw_set_def_power_per_rate_table()
1170 ratesArray[rate11s] = ratesArray[rate11l] = ath9k_hw_set_def_power_per_rate_table()
1175 ratesArray[rateHt40_0 + i] = ath9k_hw_set_def_power_per_rate_table()
1178 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; ath9k_hw_set_def_power_per_rate_table()
1179 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; ath9k_hw_set_def_power_per_rate_table()
1180 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; ath9k_hw_set_def_power_per_rate_table()
1182 ratesArray[rateExtCck] = ath9k_hw_set_def_power_per_rate_table()
1194 #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta) ath9k_hw_def_set_txpower()
1199 int16_t ratesArray[Ar5416RateSize]; ath9k_hw_def_set_txpower() local
1203 memset(ratesArray, 0, sizeof(ratesArray)); ath9k_hw_def_set_txpower()
1211 &ratesArray[0], cfgCtl, ath9k_hw_def_set_txpower()
1218 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { ath9k_hw_def_set_txpower()
1219 if (ratesArray[i] > MAX_RATE_POWER) ath9k_hw_def_set_txpower()
1220 ratesArray[i] = MAX_RATE_POWER; ath9k_hw_def_set_txpower()
1221 if (ratesArray[i] > regulatory->max_power_level) ath9k_hw_def_set_txpower()
1222 regulatory->max_power_level = ratesArray[i]; ath9k_hw_def_set_txpower()
1236 ratesArray[i] -= pwr_table_offset * 2; ath9k_hw_def_set_txpower()
1243 ATH9K_POW_SM(ratesArray[rate18mb], 24) ath9k_hw_def_set_txpower()
1244 | ATH9K_POW_SM(ratesArray[rate12mb], 16) ath9k_hw_def_set_txpower()
1245 | ATH9K_POW_SM(ratesArray[rate9mb], 8) ath9k_hw_def_set_txpower()
1246 | ATH9K_POW_SM(ratesArray[rate6mb], 0)); ath9k_hw_def_set_txpower()
1248 ATH9K_POW_SM(ratesArray[rate54mb], 24) ath9k_hw_def_set_txpower()
1249 | ATH9K_POW_SM(ratesArray[rate48mb], 16) ath9k_hw_def_set_txpower()
1250 | ATH9K_POW_SM(ratesArray[rate36mb], 8) ath9k_hw_def_set_txpower()
1251 | ATH9K_POW_SM(ratesArray[rate24mb], 0)); ath9k_hw_def_set_txpower()
1259 | ATH9K_POW_SM(ratesArray[rateXr], 8) ath9k_hw_def_set_txpower()
1268 ATH9K_POW_SM(ratesArray[rate2s], 24) ath9k_hw_def_set_txpower()
1269 | ATH9K_POW_SM(ratesArray[rate2l], 16) ath9k_hw_def_set_txpower()
1270 | ATH9K_POW_SM(ratesArray[rateXr], 8) ath9k_hw_def_set_txpower()
1271 | ATH9K_POW_SM(ratesArray[rate1l], 0)); ath9k_hw_def_set_txpower()
1273 ATH9K_POW_SM(ratesArray[rate11s], 24) ath9k_hw_def_set_txpower()
1274 | ATH9K_POW_SM(ratesArray[rate11l], 16) ath9k_hw_def_set_txpower()
1275 | ATH9K_POW_SM(ratesArray[rate5_5s], 8) ath9k_hw_def_set_txpower()
1276 | ATH9K_POW_SM(ratesArray[rate5_5l], 0)); ath9k_hw_def_set_txpower()
1281 ATH9K_POW_SM(ratesArray[rateHt20_3], 24) ath9k_hw_def_set_txpower()
1282 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16) ath9k_hw_def_set_txpower()
1283 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8) ath9k_hw_def_set_txpower()
1284 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)); ath9k_hw_def_set_txpower()
1286 ATH9K_POW_SM(ratesArray[rateHt20_7], 24) ath9k_hw_def_set_txpower()
1287 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16) ath9k_hw_def_set_txpower()
1288 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8) ath9k_hw_def_set_txpower()
1289 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)); ath9k_hw_def_set_txpower()
1293 ATH9K_POW_SM(ratesArray[rateHt40_3] + ath9k_hw_def_set_txpower()
1295 | ATH9K_POW_SM(ratesArray[rateHt40_2] + ath9k_hw_def_set_txpower()
1297 | ATH9K_POW_SM(ratesArray[rateHt40_1] + ath9k_hw_def_set_txpower()
1299 | ATH9K_POW_SM(ratesArray[rateHt40_0] + ath9k_hw_def_set_txpower()
1302 ATH9K_POW_SM(ratesArray[rateHt40_7] + ath9k_hw_def_set_txpower()
1304 | ATH9K_POW_SM(ratesArray[rateHt40_6] + ath9k_hw_def_set_txpower()
1306 | ATH9K_POW_SM(ratesArray[rateHt40_5] + ath9k_hw_def_set_txpower()
1308 | ATH9K_POW_SM(ratesArray[rateHt40_4] + ath9k_hw_def_set_txpower()
1312 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) ath9k_hw_def_set_txpower()
1314 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) ath9k_hw_def_set_txpower()
1318 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) ath9k_hw_def_set_txpower()
1319 | ATH9K_POW_SM(ratesArray[rateExtCck], 16) ath9k_hw_def_set_txpower()
1320 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) ath9k_hw_def_set_txpower()
1321 | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); ath9k_hw_def_set_txpower()
1334 ar5008_hw_init_rate_txpower(ah, ratesArray, chan, ht40_delta); ath9k_hw_def_set_txpower()
965 ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah, struct ath9k_channel *chan, int16_t *ratesArray, u16 cfgCtl, u16 antenna_reduction, u16 powerLimit) ath9k_hw_set_def_power_per_rate_table() argument
H A Deeprom_4k.c458 int16_t *ratesArray, ath9k_hw_set_4k_power_per_rate_table()
612 ratesArray[rate6mb] = ath9k_hw_set_4k_power_per_rate_table()
613 ratesArray[rate9mb] = ath9k_hw_set_4k_power_per_rate_table()
614 ratesArray[rate12mb] = ath9k_hw_set_4k_power_per_rate_table()
615 ratesArray[rate18mb] = ath9k_hw_set_4k_power_per_rate_table()
616 ratesArray[rate24mb] = ath9k_hw_set_4k_power_per_rate_table()
619 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; ath9k_hw_set_4k_power_per_rate_table()
620 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; ath9k_hw_set_4k_power_per_rate_table()
621 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; ath9k_hw_set_4k_power_per_rate_table()
622 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; ath9k_hw_set_4k_power_per_rate_table()
625 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; ath9k_hw_set_4k_power_per_rate_table()
627 ratesArray[rate1l] = targetPowerCck.tPow2x[0]; ath9k_hw_set_4k_power_per_rate_table()
628 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1]; ath9k_hw_set_4k_power_per_rate_table()
629 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2]; ath9k_hw_set_4k_power_per_rate_table()
630 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3]; ath9k_hw_set_4k_power_per_rate_table()
634 ratesArray[rateHt40_0 + i] = ath9k_hw_set_4k_power_per_rate_table()
637 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; ath9k_hw_set_4k_power_per_rate_table()
638 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; ath9k_hw_set_4k_power_per_rate_table()
639 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; ath9k_hw_set_4k_power_per_rate_table()
640 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; ath9k_hw_set_4k_power_per_rate_table()
655 int16_t ratesArray[Ar5416RateSize]; ath9k_hw_4k_set_txpower() local
659 memset(ratesArray, 0, sizeof(ratesArray)); ath9k_hw_4k_set_txpower()
667 &ratesArray[0], cfgCtl, ath9k_hw_4k_set_txpower()
674 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) { ath9k_hw_4k_set_txpower()
675 if (ratesArray[i] > MAX_RATE_POWER) ath9k_hw_4k_set_txpower()
676 ratesArray[i] = MAX_RATE_POWER; ath9k_hw_4k_set_txpower()
678 if (ratesArray[i] > regulatory->max_power_level) ath9k_hw_4k_set_txpower()
679 regulatory->max_power_level = ratesArray[i]; ath9k_hw_4k_set_txpower()
686 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2; ath9k_hw_4k_set_txpower()
692 ATH9K_POW_SM(ratesArray[rate18mb], 24) ath9k_hw_4k_set_txpower()
693 | ATH9K_POW_SM(ratesArray[rate12mb], 16) ath9k_hw_4k_set_txpower()
694 | ATH9K_POW_SM(ratesArray[rate9mb], 8) ath9k_hw_4k_set_txpower()
695 | ATH9K_POW_SM(ratesArray[rate6mb], 0)); ath9k_hw_4k_set_txpower()
697 ATH9K_POW_SM(ratesArray[rate54mb], 24) ath9k_hw_4k_set_txpower()
698 | ATH9K_POW_SM(ratesArray[rate48mb], 16) ath9k_hw_4k_set_txpower()
699 | ATH9K_POW_SM(ratesArray[rate36mb], 8) ath9k_hw_4k_set_txpower()
700 | ATH9K_POW_SM(ratesArray[rate24mb], 0)); ath9k_hw_4k_set_txpower()
704 ATH9K_POW_SM(ratesArray[rate2s], 24) ath9k_hw_4k_set_txpower()
705 | ATH9K_POW_SM(ratesArray[rate2l], 16) ath9k_hw_4k_set_txpower()
706 | ATH9K_POW_SM(ratesArray[rateXr], 8) ath9k_hw_4k_set_txpower()
707 | ATH9K_POW_SM(ratesArray[rate1l], 0)); ath9k_hw_4k_set_txpower()
709 ATH9K_POW_SM(ratesArray[rate11s], 24) ath9k_hw_4k_set_txpower()
710 | ATH9K_POW_SM(ratesArray[rate11l], 16) ath9k_hw_4k_set_txpower()
711 | ATH9K_POW_SM(ratesArray[rate5_5s], 8) ath9k_hw_4k_set_txpower()
712 | ATH9K_POW_SM(ratesArray[rate5_5l], 0)); ath9k_hw_4k_set_txpower()
716 ATH9K_POW_SM(ratesArray[rateHt20_3], 24) ath9k_hw_4k_set_txpower()
717 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16) ath9k_hw_4k_set_txpower()
718 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8) ath9k_hw_4k_set_txpower()
719 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)); ath9k_hw_4k_set_txpower()
721 ATH9K_POW_SM(ratesArray[rateHt20_7], 24) ath9k_hw_4k_set_txpower()
722 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16) ath9k_hw_4k_set_txpower()
723 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8) ath9k_hw_4k_set_txpower()
724 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)); ath9k_hw_4k_set_txpower()
729 ATH9K_POW_SM(ratesArray[rateHt40_3] + ath9k_hw_4k_set_txpower()
731 | ATH9K_POW_SM(ratesArray[rateHt40_2] + ath9k_hw_4k_set_txpower()
733 | ATH9K_POW_SM(ratesArray[rateHt40_1] + ath9k_hw_4k_set_txpower()
735 | ATH9K_POW_SM(ratesArray[rateHt40_0] + ath9k_hw_4k_set_txpower()
738 ATH9K_POW_SM(ratesArray[rateHt40_7] + ath9k_hw_4k_set_txpower()
740 | ATH9K_POW_SM(ratesArray[rateHt40_6] + ath9k_hw_4k_set_txpower()
742 | ATH9K_POW_SM(ratesArray[rateHt40_5] + ath9k_hw_4k_set_txpower()
744 | ATH9K_POW_SM(ratesArray[rateHt40_4] + ath9k_hw_4k_set_txpower()
747 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24) ath9k_hw_4k_set_txpower()
748 | ATH9K_POW_SM(ratesArray[rateExtCck], 16) ath9k_hw_4k_set_txpower()
749 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8) ath9k_hw_4k_set_txpower()
750 | ATH9K_POW_SM(ratesArray[rateDupCck], 0)); ath9k_hw_4k_set_txpower()
758 ar5008_hw_init_rate_txpower(ah, ratesArray, chan, ht40_delta); ath9k_hw_4k_set_txpower()
456 ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah, struct ath9k_channel *chan, int16_t *ratesArray, u16 cfgCtl, u16 antenna_reduction, u16 powerLimit) ath9k_hw_set_4k_power_per_rate_table() argument

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