/linux-4.4.14/drivers/staging/rtl8712/ |
D | rtl871x_mp.c | 364 set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x0); in r8712_SwitchBandwidth() 374 set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x1); in r8712_SwitchBandwidth() 517 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) in r8712_SetSingleCarrierTx() 519 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable); in r8712_SetSingleCarrierTx() 555 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bDisable); in r8712_SetSingleToneTx() 556 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bDisable); in r8712_SetSingleToneTx() 564 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable); in r8712_SetSingleToneTx() 565 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable); in r8712_SetSingleToneTx() 580 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) { in r8712_SetCarrierSuppressionTx() 582 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, in r8712_SetCarrierSuppressionTx() [all …]
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D | rtl871x_mp_phy_regdef.h | 84 #define rFPGA0_RFMOD 0x800 /*RF mode & CCK TxSC RF macro
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/linux-4.4.14/drivers/staging/rtl8723au/hal/ |
D | usb_halinit.c | 457 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1); in _BBTurnOnBlock() 458 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1); in _BBTurnOnBlock() 744 if (((rtl8723au_read32(Adapter, rFPGA0_RFMOD) & 0xFF000000) != in rtl8723au_hal_init() 746 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(24), 1); in rtl8723au_hal_init() 795 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 0); in phy_SsPwrSwitch92CU() 836 rtl8723au_read32(Adapter, rFPGA0_RFMOD); in phy_SsPwrSwitch92CU() 843 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 1); in phy_SsPwrSwitch92CU()
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D | rtl8723a_phycfg.c | 850 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0); in _PHY_SetBWMode23a92C() 858 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1); in _PHY_SetBWMode23a92C()
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D | HalDMOutSrc8723A_CE.c | 746 rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD in _PHY_IQCalibrate() 757 bbvalue = rtl8723au_read32(pAdapter, rFPGA0_RFMOD); in _PHY_IQCalibrate() 776 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, BIT(24), 0x00); in _PHY_IQCalibrate()
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/linux-4.4.14/drivers/staging/rtl8188eu/hal/ |
D | phy.c | 283 phy_set_bb_reg(adapt, rFPGA0_RFMOD, bRFMOD, 0x0); in phy_set_bw_mode_callback() 287 phy_set_bb_reg(adapt, rFPGA0_RFMOD, bRFMOD, 0x1); in phy_set_bw_mode_callback() 1090 rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD}; in phy_iq_calibrate() 1120 phy_set_bb_reg(adapt, rFPGA0_RFMOD, BIT(24), 0x00); in phy_iq_calibrate()
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D | usb_halinit.c | 618 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1); in _BBTurnOnBlock() 619 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1); in _BBTurnOnBlock()
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/linux-4.4.14/drivers/staging/rtl8192u/ |
D | r819xU_phy.c | 809 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); in rtl8192_BB_Config_ParaFile() 1559 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); in rtl8192_SetBWModeWorkItem() 1589 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); in rtl8192_SetBWModeWorkItem()
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D | r819xU_phyreg.h | 39 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ macro
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D | r8192U_core.c | 2987 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1); in rtl8192_adapter_start() 2988 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1); in rtl8192_adapter_start()
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/linux-4.4.14/drivers/staging/rtl8192e/rtl8192e/ |
D | r8192E_phyreg.h | 55 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ macro
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D | r8192E_phy.c | 565 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); in _rtl92e_bb_config_para_file() 1205 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); in _rtl92e_set_bw_mode_work_item() 1220 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); in _rtl92e_set_bw_mode_work_item()
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D | r8192E_dev.c | 869 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn, 0x1); in rtl92e_start_adapter() 870 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1); in rtl92e_start_adapter()
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/linux-4.4.14/drivers/staging/rtl8188eu/include/ |
D | rtw_mp_phy_regdef.h | 105 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting?? */ macro
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D | Hal8188EPhyReg.h | 71 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting */ macro
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/linux-4.4.14/drivers/staging/rtl8723au/include/ |
D | Hal8723APhyReg.h | 55 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting?? */ macro
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