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Searched refs:rFPGA0_RFMOD (Results 1 – 16 of 16) sorted by relevance

/linux-4.4.14/drivers/staging/rtl8712/
Drtl871x_mp.c364 set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x0); in r8712_SwitchBandwidth()
374 set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x1); in r8712_SwitchBandwidth()
517 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) in r8712_SetSingleCarrierTx()
519 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable); in r8712_SetSingleCarrierTx()
555 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bDisable); in r8712_SetSingleToneTx()
556 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bDisable); in r8712_SetSingleToneTx()
564 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable); in r8712_SetSingleToneTx()
565 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable); in r8712_SetSingleToneTx()
580 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) { in r8712_SetCarrierSuppressionTx()
582 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, in r8712_SetCarrierSuppressionTx()
[all …]
Drtl871x_mp_phy_regdef.h84 #define rFPGA0_RFMOD 0x800 /*RF mode & CCK TxSC RF macro
/linux-4.4.14/drivers/staging/rtl8723au/hal/
Dusb_halinit.c457 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1); in _BBTurnOnBlock()
458 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1); in _BBTurnOnBlock()
744 if (((rtl8723au_read32(Adapter, rFPGA0_RFMOD) & 0xFF000000) != in rtl8723au_hal_init()
746 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(24), 1); in rtl8723au_hal_init()
795 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 0); in phy_SsPwrSwitch92CU()
836 rtl8723au_read32(Adapter, rFPGA0_RFMOD); in phy_SsPwrSwitch92CU()
843 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 1); in phy_SsPwrSwitch92CU()
Drtl8723a_phycfg.c850 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0); in _PHY_SetBWMode23a92C()
858 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1); in _PHY_SetBWMode23a92C()
DHalDMOutSrc8723A_CE.c746 rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD in _PHY_IQCalibrate()
757 bbvalue = rtl8723au_read32(pAdapter, rFPGA0_RFMOD); in _PHY_IQCalibrate()
776 PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, BIT(24), 0x00); in _PHY_IQCalibrate()
/linux-4.4.14/drivers/staging/rtl8188eu/hal/
Dphy.c283 phy_set_bb_reg(adapt, rFPGA0_RFMOD, bRFMOD, 0x0); in phy_set_bw_mode_callback()
287 phy_set_bb_reg(adapt, rFPGA0_RFMOD, bRFMOD, 0x1); in phy_set_bw_mode_callback()
1090 rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD}; in phy_iq_calibrate()
1120 phy_set_bb_reg(adapt, rFPGA0_RFMOD, BIT(24), 0x00); in phy_iq_calibrate()
Dusb_halinit.c618 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1); in _BBTurnOnBlock()
619 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1); in _BBTurnOnBlock()
/linux-4.4.14/drivers/staging/rtl8192u/
Dr819xU_phy.c809 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); in rtl8192_BB_Config_ParaFile()
1559 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); in rtl8192_SetBWModeWorkItem()
1589 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); in rtl8192_SetBWModeWorkItem()
Dr819xU_phyreg.h39 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ macro
Dr8192U_core.c2987 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1); in rtl8192_adapter_start()
2988 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1); in rtl8192_adapter_start()
/linux-4.4.14/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_phyreg.h55 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ macro
Dr8192E_phy.c565 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); in _rtl92e_bb_config_para_file()
1205 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); in _rtl92e_set_bw_mode_work_item()
1220 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); in _rtl92e_set_bw_mode_work_item()
Dr8192E_dev.c869 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn, 0x1); in rtl92e_start_adapter()
870 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1); in rtl92e_start_adapter()
/linux-4.4.14/drivers/staging/rtl8188eu/include/
Drtw_mp_phy_regdef.h105 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting?? */ macro
DHal8188EPhyReg.h71 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting */ macro
/linux-4.4.14/drivers/staging/rtl8723au/include/
DHal8723APhyReg.h55 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting?? */ macro