Searched refs:psr (Results 1 - 129 of 129) sorted by relevance

/linux-4.4.14/arch/sparc/include/asm/
H A Dhead_32.h6 #define WRITE_PAUSE nop; nop; nop; /* Have to do this after %wim/%psr chg */
12 rd %psr, %l0; b label; rd %wim, %l3; nop;
15 #define SRMMU_TFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 1, %l7;
16 #define SRMMU_DFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 0, %l7;
20 rd %psr, %l0; mov num, %l7; b bad_trap_handler; rd %wim, %l3;
37 rd %psr, %l0;
41 rd %psr,%l0; \
48 rd %psr,%l0; \
58 b getcc_trap_handler; rd %psr, %l0; nop; nop;
62 b setcc_trap_handler; rd %psr, %l0; nop; nop;
66 rd %psr, %i0; jmp %l2; rett %l2 + 4; nop;
72 mov int_level, %l7; rd %psr, %l0; b real_irq_entry; rd %wim, %l3;
78 rd %psr, %l0; rd %wim, %l3; b spill_window_entry; andcc %l0, PSR_PS, %g0;
81 rd %psr, %l0; rd %wim, %l3; b fill_window_entry; andcc %l0, PSR_PS, %g0;
H A Dpsr.h2 * psr.h: This file holds the macros for masking off various parts of
13 #include <uapi/asm/psr.h>
17 /* Get the %psr register. */ get_psr()
20 unsigned int psr; get_psr() local
22 "rd %%psr, %0\n\t" get_psr()
26 : "=r" (psr) get_psr()
30 return psr; get_psr()
36 "wr %0, 0x0, %%psr\n\t" put_psr()
46 * enable bit is set in the %psr when you execute this or you will
H A Dirqflags_32.h16 #include <asm/psr.h>
26 asm volatile("rd %%psr, %0" : "=r" (flags)); arch_local_save_flags()
H A Dswitch_to_32.h23 (prv)->thread.kregs->psr &= ~PSR_EF; \
33 (nxt)->thread.kregs->psr&=~PSR_EF; \
65 "rd %%psr, %%g4\n\t" \
68 "wr %%g4, 0x20, %%psr\n\t" \
76 "wr %%g4, 0x20, %%psr\n\t" \
84 "wr %%g4, 0x0, %%psr\n\t" \
H A Dptrace.h88 return (regs->psr & PSR_SYSCALL); pt_regs_is_syscall()
93 return (regs->psr &= ~PSR_SYSCALL); pt_regs_clear_syscall()
107 #define user_mode(regs) (!((regs)->psr & PSR_PS))
H A Dprocessor_32.h15 #include <asm/psr.h>
85 regs->psr = (regs->psr & (PSR_CWP)) | PSR_S; start_thread()
H A Dsyscall.h41 return (regs->psr & PSR_C) ? true : false; syscall_has_error()
45 regs->psr |= PSR_C; syscall_set_error()
49 regs->psr &= ~PSR_C; syscall_clear_error()
H A Dide.h21 #include <asm/psr.h>
H A Dsigcontext.h39 unsigned int psr; member in struct:__anon2718::__anon2719
H A Dross.h13 /* Ross made Hypersparcs have a %psr 'impl' field of '0001'. The 'vers'
H A Dspinlock_32.h11 #include <asm/psr.h>
/linux-4.4.14/arch/frv/include/asm/
H A Dirqflags.h103 unsigned long psr; \
104 asm volatile(" movsg psr,%0 \n" \
107 " movgs %0,psr \n" \
108 : "=r"(psr) \
115 unsigned long psr; \
116 asm volatile(" movsg psr,%0 \n" \
118 " movgs %0,psr \n" \
119 : "=r"(psr) \
127 asm("movsg psr,%0" \
137 asm volatile(" movsg psr,%0 \n" \
140 " movgs %1,psr \n" \
149 asm volatile(" movgs %0,psr \n" \
H A Dptrace.h28 #define user_mode(regs) (!((regs)->psr & PSR_S))
H A Dspr-regs.h37 #define PSR_VERSION(psr) (((psr) >> PSR_VERSION_SHIFT) & 0xf)
38 #define PSR_IMPLE(psr) (((psr) >> PSR_IMPLE_SHIFT) & 0xf)
58 #define __get_PSR() ({ unsigned long x; asm volatile("movsg psr,%0" : "=r"(x)); x; })
59 #define __set_PSR(V) do { asm volatile("movgs %0,psr" : : "r"(V)); } while(0)
H A Dprocessor.h83 _regs->psr &= ~PSR_S; \
/linux-4.4.14/arch/ia64/include/asm/native/
H A Dinst.h50 (pred) mov reg = psr
90 ssm psr.ic | PSR_DEFAULT_BITS \
96 ssm psr.ic \
101 rsm psr.ic
104 (pred) ssm psr.i
107 (pred) rsm psr.i
110 rsm psr.i | psr.ic
113 rsm psr.dt
116 rsm psr.be | psr.i
119 ssm psr.dt \
/linux-4.4.14/arch/sparc/kernel/
H A Dtrampoline_32.S9 #include <asm/psr.h>
24 * in and sets PIL in %psr to 15, no irqs.
44 /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
46 wr %g1, 0x0, %psr ! traps off though
69 rd %psr, %g1
70 wr %g1, PSR_ET, %psr ! traps on
98 /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
100 wr %g1, 0x0, %psr ! traps off though
130 rd %psr, %g1
131 wr %g1, PSR_ET, %psr ! traps on
157 /* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
159 wr %g1, 0x0, %psr ! traps off though
186 rd %psr, %g1
187 wr %g1, PSR_ET, %psr ! traps on
H A Dentry.S19 #include <asm/psr.h>
157 wr %l0, 0x0, %psr
179 wr %l4, 0x0, %psr
181 wr %l4, PSR_ET, %psr
198 wr %l0, PSR_ET, %psr
228 wr %g2, 0x0, %psr
230 wr %g2, PSR_ET, %psr
237 wr %g2, PSR_ET, %psr ! keep ET up
247 wr %g2, 0x0, %psr
249 wr %g2, PSR_ET, %psr
253 wr %l0, PSR_ET, %psr
285 wr %l4, 0x0, %psr
287 wr %l4, PSR_ET, %psr
330 wr %l4, 0x0, %psr
332 wr %l4, PSR_ET, %psr
348 wr %g2, 0x0, %psr
350 wr %g2, PSR_ET, %psr
354 wr %l0, PSR_ET, %psr
376 wr %l4, 0x0, %psr
378 wr %l4, PSR_ET, %psr
402 wr %g2, 0x0, %psr
404 wr %g2, PSR_ET, %psr
408 wr %l0, PSR_ET, %psr
417 wr %l4, 0x0, %psr
419 wr %l4, PSR_ET, %psr
442 wr %l0, PSR_ET, %psr ! re-enable traps
462 wr %l0, PSR_ET, %psr
483 wr %l0, PSR_ET, %psr
495 wr %l0, PSR_ET, %psr ! re-enable traps
510 wr %l0, PSR_ET, %psr ! re-enable traps
534 wr %l0, 0x0, %psr
541 wr %l0, 0x0, %psr
549 wr %l0, PSR_ET, %psr ! re-enable traps
566 wr %l0, PSR_ET, %psr ! re-enable traps
583 wr %l0, PSR_ET, %psr ! re-enable traps
600 wr %l0, PSR_ET, %psr ! re-enable traps
617 wr %l0, PSR_ET, %psr ! re-enable traps
634 wr %l0, PSR_ET, %psr ! re-enable traps
651 wr %l0, PSR_ET, %psr ! re-enable traps
667 wr %l0, PSR_ET, %psr
701 * the %psr in register %g1.
708 and %g1, 0xf, %g1 ! only ICC bits in %psr
713 * that it would like placed in the %psr. Be careful not to flip
722 andn %l0, %l5, %l0 ! clear ICC bits in %psr
726 wr %l4, 0x0, %psr ! set new %psr
742 wr %l4, 0x0, %psr
744 wr %l4, PSR_ET, %psr
793 wr %l0, PSR_ET, %psr
883 rd %psr, %g4
902 rd %psr, %g4
925 rd %psr, %g4
989 rd %psr, %l1
1015 wr %l0, PSR_ET, %psr
1218 wr %l0, PSR_ET, %psr
1234 wr %l0, PSR_ET, %psr
1265 rd %psr, %o5 ! must clear interrupts
1267 wr %o4, 0x0, %psr ! the uwinmask state
1284 wr %o5, 0x0, %psr ! re-enable interrupts
1327 wr %l4, 0x0, %psr
1329 wr %l4, PSR_ET, %psr
1340 rd %psr, %l0
H A Dtraps_32.c86 if(regs->psr & PSR_PS) die_if_kernel()
101 if(regs->psr & PSR_PS) do_hw_interrupt()
113 unsigned long psr) do_illegal_instruction()
117 if(psr & PSR_PS) do_illegal_instruction()
133 unsigned long psr) do_priv_instruction()
137 if(psr & PSR_PS) do_priv_instruction()
150 unsigned long psr) do_memaccess_unaligned()
154 if(regs->psr & PSR_PS) { do_memaccess_unaligned()
181 unsigned long psr) do_fpd_trap()
184 if(psr & PSR_PS) do_fpd_trap()
188 regs->psr |= PSR_EF; do_fpd_trap()
223 unsigned long psr)
245 regs->psr &= ~PSR_EF;
287 if(psr & PSR_PS) {
324 regs->psr &= ~PSR_EF;
330 unsigned long psr) handle_tag_overflow()
334 if(psr & PSR_PS) handle_tag_overflow()
345 unsigned long psr) handle_watchpoint()
349 pc, npc, psr); handle_watchpoint()
351 if(psr & PSR_PS) handle_watchpoint()
357 unsigned long psr) handle_reg_access()
363 pc, npc, psr); handle_reg_access()
374 unsigned long psr) handle_cp_disabled()
387 unsigned long psr) handle_cp_exception()
393 pc, npc, psr); handle_cp_exception()
404 unsigned long psr) handle_hw_divzero()
112 do_illegal_instruction(struct pt_regs *regs, unsigned long pc, unsigned long npc, unsigned long psr) do_illegal_instruction() argument
132 do_priv_instruction(struct pt_regs *regs, unsigned long pc, unsigned long npc, unsigned long psr) do_priv_instruction() argument
149 do_memaccess_unaligned(struct pt_regs *regs, unsigned long pc, unsigned long npc, unsigned long psr) do_memaccess_unaligned() argument
180 do_fpd_trap(struct pt_regs *regs, unsigned long pc, unsigned long npc, unsigned long psr) do_fpd_trap() argument
222 do_fpe_trap(struct pt_regs *regs, unsigned long pc, unsigned long npc, unsigned long psr) do_fpe_trap() argument
329 handle_tag_overflow(struct pt_regs *regs, unsigned long pc, unsigned long npc, unsigned long psr) handle_tag_overflow() argument
344 handle_watchpoint(struct pt_regs *regs, unsigned long pc, unsigned long npc, unsigned long psr) handle_watchpoint() argument
356 handle_reg_access(struct pt_regs *regs, unsigned long pc, unsigned long npc, unsigned long psr) handle_reg_access() argument
373 handle_cp_disabled(struct pt_regs *regs, unsigned long pc, unsigned long npc, unsigned long psr) handle_cp_disabled() argument
386 handle_cp_exception(struct pt_regs *regs, unsigned long pc, unsigned long npc, unsigned long psr) handle_cp_exception() argument
403 handle_hw_divzero(struct pt_regs *regs, unsigned long pc, unsigned long npc, unsigned long psr) handle_hw_divzero() argument
H A Dsigutil_32.c22 regs->psr &= ~(PSR_EF); save_fpu_state()
31 regs->psr &= ~(PSR_EF); save_fpu_state()
57 regs->psr &= ~PSR_EF; restore_fpu_state()
61 regs->psr &= ~PSR_EF; restore_fpu_state()
H A Dsignal_32.c108 up_psr = regs->psr; do_sigreturn()
111 /* User can only change condition codes and FPU enabling in %psr. */ do_sigreturn()
112 regs->psr = (up_psr & ~(PSR_ICC | PSR_EF)) do_sigreturn()
113 | (regs->psr & (PSR_ICC | PSR_EF)); do_sigreturn()
145 unsigned int psr, pc, npc, ufp; do_rt_sigreturn() local
167 err |= __get_user(psr, &sf->regs.psr); do_rt_sigreturn()
172 regs->psr = (regs->psr & ~PSR_ICC) | (psr & PSR_ICC); do_rt_sigreturn()
327 unsigned int psr; setup_rt_frame() local
348 psr = regs->psr; setup_rt_frame()
350 psr |= PSR_EF; setup_rt_frame()
351 err |= __put_user(psr, &sf->regs.psr); setup_rt_frame()
355 if (psr & PSR_EF) { setup_rt_frame()
439 regs->psr |= PSR_C; syscall_restart()
480 if (pt_regs_is_syscall(regs) && (regs->psr & PSR_C)) do_signal()
490 if (pt_regs_is_syscall(regs) && (regs->psr & PSR_C)) { do_signal()
H A Dentry.h15 unsigned long npc, unsigned long psr);
18 unsigned long npc, unsigned long psr);
20 unsigned long npc, unsigned long psr);
22 unsigned long npc, unsigned long psr);
24 unsigned long npc, unsigned long psr);
26 unsigned long npc, unsigned long psr);
28 unsigned long npc, unsigned long psr);
30 unsigned long npc, unsigned long psr);
32 unsigned long npc, unsigned long psr);
34 unsigned long npc, unsigned long psr);
H A Dsignal32.c53 /* Only valid if (info.si_regs.psr & (PSR_VERS|PSR_IMPL)) == PSR_V8PLUS */
67 /* Only valid if (regs.psr & (PSR_VERS|PSR_IMPL)) == PSR_V8PLUS */
158 unsigned int psr, ufp; do_sigreturn32() local
198 err |= __get_user(psr, &sf->info.si_regs.psr); do_sigreturn32()
202 if ((psr & (PSR_VERS|PSR_IMPL)) == PSR_V8PLUS) { do_sigreturn32()
217 regs->tstate |= psr_to_tstate_icc(psr); do_sigreturn32()
247 unsigned int psr, pc, npc, ufp; do_rt_sigreturn32() local
287 err |= __get_user(psr, &sf->regs.psr); do_rt_sigreturn32()
291 if ((psr & (PSR_VERS|PSR_IMPL)) == PSR_V8PLUS) { do_rt_sigreturn32()
306 regs->tstate |= psr_to_tstate_icc(psr); do_rt_sigreturn32()
425 u32 psr; setup_frame32() local
458 psr = tstate_to_psr(regs->tstate); setup_frame32()
460 psr |= PSR_EF; setup_frame32()
461 err |= __put_user(psr, &sf->info.si_regs.psr); setup_frame32()
472 if (psr & PSR_EF) { setup_frame32()
556 u32 psr; setup_rt_frame32() local
589 psr = tstate_to_psr(regs->tstate); setup_rt_frame32()
591 psr |= PSR_EF; setup_rt_frame32()
592 err |= __put_user(psr, &sf->regs.psr); setup_rt_frame32()
603 if (psr & PSR_EF) { setup_rt_frame32()
H A Dkgdb_32.c36 gdb_regs[GDB_PSR] = regs->psr; pt_regs_to_gdb_regs()
91 if (regs->psr != gdb_regs[GDB_PSR]) { gdb_regs_to_pt_regs()
92 unsigned long cwp = regs->psr & PSR_CWP; gdb_regs_to_pt_regs()
94 regs->psr = (gdb_regs[GDB_PSR] & ~PSR_CWP) | cwp; gdb_regs_to_pt_regs()
H A Drtrap_32.S9 #include <asm/psr.h>
57 wr %t_psr, 0x0, %psr
87 wr %t_psr, 0x0, %psr
95 wr %t_psr, PSR_ET, %psr
153 wr %t_psr, 0x0, %psr
166 wr %t_psr, PSR_ET, %psr
209 wr %t_psr, 0x0, %psr
218 wr %t_psr, PSR_ET, %psr
H A Dptrace_32.c92 reg = regs->psr; genregs32_get()
169 unsigned long psr; genregs32_set() local
178 psr = regs->psr; genregs32_set()
179 psr &= ~(PSR_ICC | PSR_SYSCALL); genregs32_set()
180 psr |= (reg & (PSR_ICC | PSR_SYSCALL)); genregs32_set()
181 regs->psr = psr; genregs32_set()
360 &pregs->psr); arch_ptrace()
373 &pregs->psr); arch_ptrace()
H A Dwuf.S10 #include <asm/psr.h>
37 * rd %psr, %l0
118 /* Now preserve the condition codes in %psr, pause, and
121 wr %t_psr, 0x0, %psr
163 rd %psr, %g3 /* Read %psr in live user window */
187 wr %t_psr, PSR_ET, %psr ! enable traps
213 wr %t_psr, 0x0, %psr
299 wr %t_psr, 0x0, %psr
H A Dwof.S10 #include <asm/psr.h>
33 #define t_psr l0 /* %psr at trap time T */
59 * rd %psr, %l0
121 wr %t_psr, 0x0, %psr ! restore condition codes in %psr
190 wr %t_psr, 0x0, %psr
206 rd %psr, %glob_tmp
252 wr %t_psr, PSR_ET, %psr
278 /* Restore globals, condition codes in the %psr and
285 wr %t_psr, 0x0, %psr
363 rd %psr, %glob_tmp
H A Dirq_32.c36 "rd %%psr, %0\n\t" arch_local_irq_save()
38 "wr %1, 0, %%psr\n\t" arch_local_irq_save()
53 "rd %%psr, %0\n\t" arch_local_irq_enable()
55 "wr %0, 0, %%psr\n\t" arch_local_irq_enable()
68 "rd %%psr, %0\n\t" arch_local_irq_restore()
71 "wr %0, %2, %%psr\n\t" arch_local_irq_restore()
H A Dprocess_32.c37 #include <asm/psr.h>
125 r->psr, r->pc, r->npc, r->y, print_tainted()); show_regs()
347 unsigned long psr; local
354 psr = childregs->psr = get_psr();
355 ti->kpsr = psr | PSR_PIL;
356 ti->kwim = 1 << (((psr & PSR_CWP) + 1) % nwindows);
399 childregs->psr &= ~PSR_EF;
432 regs->psr &= ~(PSR_EF); dump_fpu()
442 regs->psr &= ~(PSR_EF); dump_fpu()
H A Detrap_32.S12 #include <asm/psr.h>
47 * rd %psr, %l0
70 * %l0 contains trap time %psr, %l1 and %l2 contain the
82 andcc %t_psr, PSR_PS, %g0 ! fromsupv_p = (psr & PSR_PS)
84 sll %t_twinmask, %t_psr, %t_twinmask ! t_twinmask = (1 << psr)
141 sll %t_twinmask, %t_psr, %t_twinmask ! t_twinmask = (1 << psr)
H A Dcpu.c20 #include <asm/psr.h>
442 int psr; cpu_type_probe() local
447 psr = get_psr(); cpu_type_probe()
448 put_psr(psr | PSR_EF); cpu_type_probe()
455 put_psr(psr); cpu_type_probe()
H A Dhead_32.S20 #include <asm/psr.h>
201 * LEON - identified by the psr.impl field
202 * Viking - identified by the psr.impl field
208 rd %psr, %g3
241 rd %psr, %g3 ! DO NOT TOUCH %g3
243 wr %g2, 0x0, %psr
292 wr %g3, 0x0, %psr ! tick tock, tick tock
477 rd %psr, %o1
510 wr %g2, 0x0, %psr
565 rd %psr, %g3
653 rd %psr, %g3
654 wr %g3, 0x0, %psr
657 wr %g3, PSR_ET, %psr
H A Dkernel.h75 unsigned long npc, unsigned long psr);
H A Dptrace_64.c887 &pregs->psr); compat_arch_ptrace()
899 &pregs->psr); compat_arch_ptrace()
/linux-4.4.14/arch/ia64/include/asm/
H A Dmca_asm.h62 * 1. Save the current psr
66 * in the psr before updating the ipsr and iip.
68 * 4. Turn off the instruction, data and rse translation bits of the psr
72 * [psr.{rt, it, dt, i, be} = 0]
80 * 6. Do an rfi to move the values from ipsr to psr and iip to ip.
83 mov old_psr = psr; \
99 mov temp1 = psr; \
100 mov temp2 = psr; \
105 mov psr.l = temp2; \
144 * 1. Get the old saved psr
146 * 2. Clear the interrupt state collection bit in the current psr.
148 * 3. Set the instruction translation bit back in the old psr
150 * lower 32-bits of old psr.(Also the old psr has the data and
159 * 7. Do an rfi to move ipsr to psr and iip to ip.
163 mov temp2 = psr; \
169 mov psr.l = temp2; \
H A Dirqflags.h28 * - clearing psr.i is implicitly serialized (visible by next insn)
29 * - setting psr.i requires data serialization
H A Dspinlock.h160 "(p6) ssm psr.i\n" arch_read_lock_flags()
166 "(p6) rsm psr.i\n" arch_read_lock_flags()
212 "(p6) ssm psr.i\n" arch_write_lock_flags()
218 "(p6) rsm psr.i\n" arch_write_lock_flags()
H A Dprocessor.h457 __u64 psr; ia64_clear_ic() local
458 psr = ia64_getreg(_IA64_REG_PSR); ia64_clear_ic()
462 return psr; ia64_clear_ic()
466 * Restore the psr.
469 ia64_set_psr (__u64 psr) ia64_set_psr() argument
472 ia64_setreg(_IA64_REG_PSR_L, psr); ia64_set_psr()
H A Delf.h150 * ip cfm psr
H A Dpal.h764 u64 pmsa_xpsr; /* previous psr */
/linux-4.4.14/arch/ia64/kernel/
H A Dpal.S70 mov loc3 = psr
78 rsm psr.i
82 1: mov psr.l = loc3
87 srlz.d // seralize restoration of psr.l
112 mov loc3 = psr
114 rsm psr.i
118 .ret0: mov psr.l = loc3
122 srlz.d // serialize restoration of psr.l
161 mov loc3 = psr // save psr
173 or loc3=loc3,r17 // add in psr the bits to set
175 andcm r16=loc3,r16 // removes bits to clear from psr
183 mov r16=loc3 // r16= original psr
187 mov psr.l = loc3 // restore init PSR
193 srlz.d // seralize restoration of psr.l
215 mov loc3 = psr // save psr
224 or loc3=loc3,r17 // add in psr the bits to set
227 andcm r16=loc3,r16 // removes bits to clear from psr
240 mov r16=loc3 // r16= original psr
245 mov psr.l = loc3 // restore init PSR
250 srlz.d // seralize restoration of psr.l
H A Desi_stub.S22 * psr.dfl and psr.dfh MUST be cleared, despite what this manual says.
24 * (the br.ia instruction fails unless psr.dfl and psr.dfh are
75 mov loc3=psr // save processor status word
81 andcm r16=loc3,r16 // get psr with IT, DT, and RT bits cleared
87 mov r16=loc3 // save virtual mode psr
H A Defi_stub.S19 * psr.dfl and psr.dfh MUST be cleared, despite what this manual says.
21 * (the br.ia instruction fails unless psr.dfl and psr.dfh are
58 mov loc3=psr // save processor status word
64 andcm r16=loc3,r16 // get psr with IT, DT, and RT bits cleared
H A Dminstate.h24 * the minimum state necessary that allows us to turn psr.ic back
28 * psr.ic: off
32 * psr.ic: off
40 * p15 = TRUE if psr.i is set in cr.ipsr
44 * Note that psr.ic is NOT turned on by this macro. This is so that
153 * SAVE_REST saves the remainder of pt_regs (with psr.ic on).
156 * psr.ic: on
H A Drelocate_kernel.S27 rsm psr.i| psr.ic
55 rfi // note: this unmask MCA/INIT (psr.mc)
H A Dhead.S197 rsm psr.i | psr.ic
317 rsm psr.ic
338 ssm psr.ic
352 * always sets the psr.dfh bit of the task it is switching to).
880 * r16 = new psr to establish
889 rsm psr.i | psr.ic // disable interrupts and interrupt collection
929 * r16 = new psr to establish
937 rsm psr.i | psr.ic // disable interrupts and interrupt collection
1078 rsm psr.i | psr.ic
1097 rfi;; // note: this unmask MCA/INIT (psr.mc)
1164 ssm psr.ic;;
H A Dperfmon.c316 unsigned long ctx_saved_psr_up; /* only contains psr.up value */
970 * we cannot use psr.pp/psr.up for this, it is controlled by pfm_mask_monitoring()
999 unsigned long psr, val; pfm_restore_monitoring() local
1014 psr = pfm_get_psr(); pfm_restore_monitoring()
1019 * restore the PMC (and PMD) and then re-establish the psr pfm_restore_monitoring()
1087 pfm_set_psr_l(psr); pfm_restore_monitoring()
2498 * to user level when psr.sp=0 pfm_reset_pmu_state()
4058 * set user level psr.pp for the caller pfm_start()
4325 DPRINT(("clearing psr.sp for [%d]\n", task_pid_nr(task))); pfm_context_load()
4371 /* initial saved psr (stopped) */ pfm_context_load()
4438 * clear psr and dcr bits pfm_context_unload()
4499 DPRINT(("setting psr.sp for [%d]\n", task_pid_nr(task))); pfm_context_unload()
4517 * reset activation counter and psr pfm_context_unload()
4596 { u64 psr = pfm_get_psr(); pfm_exit_thread() local
4597 BUG_ON(psr & (IA64_PSR_UP|IA64_PSR_PP)); pfm_exit_thread()
5398 * in case monitoring must be stopped, we toggle the psr bits pfm_overflow_handler()
5434 * context. All we need to do is to stop monitoring using the psr bits which pfm_overflow_handler()
5644 unsigned long psr; pfm_proc_show() local
5688 psr = pfm_get_psr(); pfm_proc_show()
5693 "CPU%-2d psr : 0x%lx\n" pfm_proc_show()
5695 cpu, psr, pfm_proc_show()
5812 u64 psr; pfm_save_regs() local
5844 psr = pfm_get_psr(); pfm_save_regs()
5846 BUG_ON(psr & (IA64_PSR_I)); pfm_save_regs()
5852 * We do not need to set psr.sp because, it is irrelevant in kernel. pfm_save_regs()
5858 * keep a copy of psr.up (for reload) pfm_save_regs()
5860 ctx->ctx_saved_psr_up = psr & IA64_PSR_UP; pfm_save_regs()
5900 u64 psr; pfm_save_regs() local
5908 psr = pfm_get_psr(); pfm_save_regs()
5910 BUG_ON(psr & (IA64_PSR_I)); pfm_save_regs()
5916 * We do not need to set psr.sp because, it is irrelevant in kernel. pfm_save_regs()
5922 * keep a copy of psr.up (for reload) pfm_save_regs()
5924 ctx->ctx_saved_psr_up = psr & IA64_PSR_UP; pfm_save_regs()
5933 { u64 psr = pfm_get_psr(); pfm_lazy_save_regs() local
5934 BUG_ON(psr & IA64_PSR_UP); pfm_lazy_save_regs()
5995 u64 psr, psr_up; pfm_load_regs() local
6014 psr = pfm_get_psr(); pfm_load_regs()
6018 BUG_ON(psr & (IA64_PSR_UP|IA64_PSR_PP)); pfm_load_regs()
6019 BUG_ON(psr & IA64_PSR_I); pfm_load_regs()
6047 * retrieve saved psr.up pfm_load_regs()
6053 * then nothing to do except restore psr pfm_load_regs()
6065 * To avoid leaking information to the user level when psr.sp=0, pfm_load_regs()
6135 * restore the psr.up bit. measurement pfm_load_regs()
6158 u64 psr, psr_up; pfm_load_regs() local
6163 psr = pfm_get_psr(); pfm_load_regs()
6165 BUG_ON(psr & (IA64_PSR_UP|IA64_PSR_PP)); pfm_load_regs()
6166 BUG_ON(psr & IA64_PSR_I); pfm_load_regs()
6182 * retrieved saved psr.up pfm_load_regs()
6189 * need to restore psr and we go pfm_load_regs()
6191 * we do not touch either PMC nor PMD. the psr is not touched pfm_load_regs()
6209 * To avoid leaking information to the user level when psr.sp=0, pfm_load_regs()
6256 * restore the psr.up bit. measurement pfm_load_regs()
6688 unsigned long psr, dcr, info, flags; dump_pmu_state() local
6715 psr = pfm_get_psr(); dump_pmu_state()
6717 printk("->CPU%d pmc0=0x%lx psr.pp=%d psr.up=%d dcr.pp=%d syst_info=0x%lx user_psr.up=%d user_psr.pp=%d\n", dump_pmu_state()
6720 psr & IA64_PSR_PP ? 1 : 0, dump_pmu_state()
6721 psr & IA64_PSR_UP ? 1 : 0, dump_pmu_state()
6773 * the psr bits are already set properly in copy_threads() pfm_inherit()
H A Dmca_asm.S960 // The psr is set to all zeroes. SAL return requires either all zeroes or
961 // just psr.mc set. Leaving psr.mc off allows INIT to be issued if this
1100 // Set psr.mc bit to mask MCA/INIT.
1102 rsm psr.i | psr.ic // disable interrupts
1106 mov r14 = psr // get psr{36:35,31:0}
1109 dep r14 = -1, r14, PSR_MC, 1 // set psr.mc
1111 dep r14 = -1, r14, PSR_IC, 1 // set psr.ic
H A Dtraps.c192 * care of clearing psr.dfh.
197 struct ia64_psr *psr = ia64_psr(regs); disabled_fph_fault() local
200 psr->dfh = 0; disabled_fph_fault()
224 psr->mfh = 0; disabled_fph_fault()
231 psr->mfh = 1; disabled_fph_fault()
449 * This fault was due to lfetch.fault, set "ed" bit in the psr to cancel ia64_fault()
H A Divt.S62 # define PSR_DEFAULT_BITS psr.ac
356 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
361 cmp.ne p8,p0=r0,r23 // psr.cpl != 0?
405 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
451 * Clobbered: b0, r18, r19, r21, r22, psr.dt (cleared)
856 SSM_PSR_I(p15, p15, r16) // M2 restore psr.i
1180 rsm psr.dfh // ensure we can access fph
1517 // call do_page_fault (predicates are in r31, psr.dt may be off, r16 is faulting address)
1527 SSM_PSR_I(p15, p15, r14) // restore psr.i
1554 SSM_PSR_I(p15, p15, r15) // restore psr.i
1569 // ensure everybody knows psr.ic is back on
1602 SSM_PSR_I(p15, p15, r3) // restore psr.i
1622 * psr.ic: off
1637 SSM_PSR_I(p15, p15, r3) // restore psr.i
1663 SSM_PSR_I(p15, p15, r3) // restore psr.i
H A Dptrace.c681 struct ia64_psr *psr = ia64_psr(task_pt_regs(task)); ia64_flush_fph() local
688 if (ia64_is_local_fpu_owner(task) && psr->mfh) { ia64_flush_fph()
689 psr->mfh = 0; ia64_flush_fph()
707 struct ia64_psr *psr = ia64_psr(task_pt_regs(task)); ia64_sync_fph() local
715 psr->dfh = 1; ia64_sync_fph()
824 unsigned long psr, ec, lc, rnat, bsp, cfm, nat_bits, val; ptrace_getregs() local
848 if (access_uarea(child, PT_CR_IPSR, &psr, 0) < 0 ptrace_getregs()
860 retval |= __put_user(psr, &ppr->cr_ipsr); ptrace_getregs()
968 unsigned long psr, rsc, ec, lc, rnat, bsp, cfm, nat_bits, val = 0; ptrace_setregs() local
996 retval |= __get_user(psr, &ppr->cr_ipsr); ptrace_setregs()
1098 retval |= access_uarea(child, PT_CR_IPSR, &psr, 1); ptrace_setregs()
1458 /* psr.ri==3 is a reserved value: SDM 2:25 */ access_elf_areg()
1575 /* ip cfm psr ar.rsc ar.bsp ar.bspstore ar.rnat do_gpregs_get()
1663 /* ip cfm psr ar.rsc ar.bsp ar.bspstore ar.rnat do_gpregs_set()
H A Dprocess.c106 printk("psr : %016lx ifs : %016lx ip : [<%016lx>] %s (%s)\n", show_regs()
400 * the psr.up/psr.pp bits must be cleared on fork but inherited on execve() copy_thread()
428 * the psr.up/psr.pp bits must be cleared on fork but inherited on execve() copy_thread()
H A Dsignal.c90 struct ia64_psr *psr = ia64_psr(&scr->pt); restore_sigcontext() local
93 psr->mfh = 0; /* drop signal handler's fph contents... */ restore_sigcontext()
95 if (psr->dfh) restore_sigcontext()
98 /* We already own the local fph, otherwise psr->dfh wouldn't be 0. */ restore_sigcontext()
H A Dfsys.S399 MOV_FROM_PSR(p0, r29, r26) // read psr (12 cyc load latency)
419 * Note that we preserve the value of psr.pp rather than
431 * - r29: psr
458 * Reading psr.l gives us only bits 0-31, psr.it, and psr.mc.
H A Defi.c454 u64 psr; efi_map_pal_code() local
462 psr = ia64_clear_ic(); efi_map_pal_code()
467 ia64_set_psr(psr); /* restore psr */ efi_map_pal_code()
H A Dentry.S206 RSM_PSR_IC(r25) // interrupts (psr.i) are already disabled here
220 SSM_PSR_IC_AND_SRLZ_D(r8, r9) // reenable the psr.ic bit
551 (pUStk) rsm psr.i // disable interrupts
668 * r29: user-level psr
1115 (pKStk) extr.u r22=r22,21,1 // I0 extract current value of psr.pp from r22
1119 (pKStk) dep r29=r22,r29,21,1 // I0 update ipsr.pp with psr.pp
H A Dmca.c1227 unsigned long psr; mca_insert_tr() local
1233 psr = ia64_clear_ic(); mca_insert_tr()
1258 ia64_set_psr(psr); mca_insert_tr()
H A Dmca_drv.c160 "iip: %p, psr: 0x%lx,paddr: 0x%lx](%s) encounters MCA.\n", mca_handler_bh()
/linux-4.4.14/arch/sparc/include/uapi/asm/
H A Dpsrcompat.h37 static inline unsigned long psr_to_tstate_icc(unsigned int psr) psr_to_tstate_icc() argument
39 unsigned long tstate = ((unsigned long)(psr & PSR_ICC)) << 12; psr_to_tstate_icc()
40 if ((psr & (PSR_VERS|PSR_IMPL)) == PSR_V8PLUS) psr_to_tstate_icc()
41 tstate |= ((unsigned long)(psr & PSR_XCC)) << 20; psr_to_tstate_icc()
H A Dpsr.h2 * psr.h: This file holds the macros for masking off various parts of
H A Dptrace.h43 unsigned int psr; member in struct:pt_regs32
94 #include <asm/psr.h>
104 unsigned long psr; member in struct:pt_regs
/linux-4.4.14/arch/frv/kernel/
H A Dprocess.c210 unsigned long psr = __get_PSR(); elf_check_arch() local
239 if (PSR_IMPLE(psr) != PSR_IMPLE_FR405 && elf_check_arch()
240 PSR_IMPLE(psr) != PSR_IMPLE_FR451) elf_check_arch()
252 if (PSR_IMPLE(psr) != PSR_IMPLE_FR401 && elf_check_arch()
253 PSR_IMPLE(psr) != PSR_IMPLE_FR405 && elf_check_arch()
254 PSR_IMPLE(psr) != PSR_IMPLE_FR451 && elf_check_arch()
255 PSR_IMPLE(psr) != PSR_IMPLE_FR551) elf_check_arch()
259 if (PSR_IMPLE(psr) != PSR_IMPLE_FR451) elf_check_arch()
263 if (PSR_IMPLE(psr) != PSR_IMPLE_FR501) elf_check_arch()
267 if (PSR_IMPLE(psr) != PSR_IMPLE_FR551) elf_check_arch()
H A Dentry.S113 movsg psr ,gr22
170 movsg psr,gr4
173 movgs gr4,psr
175 movgs gr4,psr
240 movsg psr ,gr22
289 movsg psr,gr4
291 movgs gr4,psr
293 movgs gr4,psr
311 movsg psr,gr30
314 movgs gr30,psr
332 movsg psr,gr30
334 movgs gr30,psr
379 movsg psr,gr22
455 movsg psr,gr22
599 movsg psr,gr4
601 movgs gr4,psr
624 movsg psr,gr4
626 movgs gr4,psr
652 movsg psr,gr4
654 movgs gr4,psr
672 movsg psr,gr4
674 movgs gr4,psr
691 movsg psr,gr4
693 movgs gr4,psr
713 movsg psr,gr4
715 movgs gr4,psr
739 movsg psr,gr4
741 movgs gr4,psr
759 movsg psr,gr4
761 movgs gr4,psr
778 movsg psr,gr4
780 movgs gr4,psr
798 movsg psr,gr4
800 movgs gr4,psr
821 movsg psr,gr4
823 movgs gr4,psr
836 movsg psr,gr4
838 movgs gr4,psr
846 movsg psr,gr4
848 movgs gr4,psr
886 movsg psr,gr4 ; enable exceptions
888 movgs gr4,psr
917 movsg psr,gr23
923 # rebuild saved psr - execve will change it for init/main.c
933 movgs gr23,psr
944 movgs gr22,psr
1023 movsg psr ,gr30
1061 movsg psr,gr23
1063 movgs gr23,psr
1069 movsg psr,gr23
1071 movgs gr23,psr
1097 movsg psr,gr23
1099 movgs gr23,psr
1114 movsg psr,gr23
1116 movgs gr23,psr
1118 movsg psr,gr23
1120 movgs gr23,psr
1157 movsg psr,gr23
1159 movgs gr23,psr
H A Dsleep.S62 # save hsr0, psr, isr, and lr for resume code
67 movsg psr,gr5
101 movsg psr,gr8
104 movgs gr8,psr
128 # gr8 holds desired psr sleep value
177 movgs gr8,psr
220 # restore hsr0, psr, isr, and leave saved lr in gr7
261 lddi @(gr11,#0),gr4 ; hsr0, psr
273 movgs gr5,psr
317 movsg psr,gr8
320 movgs gr4,psr
359 movgs gr8,psr
H A Dswitch_to.S77 movsg psr,gr4
91 movgs gr5,psr
107 movgs gr4,psr
148 movsg psr,gr7
150 movgs gr7,psr
151 movsg psr,gr7
317 movsg psr,gr7
319 movgs gr7,psr
320 movsg psr,gr7
H A Dcmode.S70 movsg psr,gr14
72 movgs gr3,psr
185 movgs gr14,psr
H A Dbreak.S142 movsg psr,gr2
177 movgs gr3,psr
308 movsg psr,gr2
311 movgs gr2,psr
340 movsg psr,gr2
342 movgs gr2,psr
440 movsg psr,gr2
443 movgs gr2,psr
516 movsg psr,gr22
550 movgs gr22,psr
615 movsg psr ,gr22
H A Dsignal.c62 unsigned long tbr, psr; restore_sigcontext() local
68 psr = user->i.psr; restore_sigcontext()
72 user->i.psr = psr; restore_sigcontext()
H A Dsetup.c369 unsigned long psr = __get_PSR(); determine_cpu() local
372 __set_PSR(psr | PSR_EM | PSR_EF | PSR_CM | PSR_NEM); determine_cpu()
374 __set_PSR(psr); determine_cpu()
392 switch (PSR_IMPLE(psr)) { determine_cpu()
398 switch (PSR_VERSION(psr)) { determine_cpu()
429 switch (PSR_VERSION(psr)) { determine_cpu()
459 switch (PSR_VERSION(psr)) { determine_cpu()
476 switch (PSR_VERSION(psr)) { determine_cpu()
489 switch (PSR_VERSION(psr)) { determine_cpu()
526 unsigned long clkc, psr, quot; determine_clocks() local
529 psr = __get_PSR(); determine_clocks()
536 printk("psr=%08lx hsr0=%08lx clkc=%08lx\n", psr, __get_HSR(0), clkc); determine_clocks()
H A Dasm-offsets.c45 DEF_PTREG(REG_PSR, psr); foo()
H A Dptrace.c70 if (pos < offsetof(struct user_int_regs, psr) + sizeof(long) && genregs_set()
71 pos + count > offsetof(struct user_int_regs, psr)) genregs_set()
H A Dhead.S115 movsg psr,gr5
293 movsg psr,gr5
359 movsg psr,gr6
463 movsg psr,gr22
467 movgs gr22,psr
H A Dgdb-stub.c1188 __debug_frame->psr & PSR_S ? "kernel" : "user"); gdbstub_show_regs()
1436 __debug_frame->psr |= PSR_ET; gdbstub()
1437 __debug_frame->psr &= ~PSR_S; gdbstub()
1438 if (__debug_frame->psr & PSR_PS) gdbstub()
1439 __debug_frame->psr |= PSR_S; gdbstub()
1451 __debug_frame->psr |= PSR_ET; gdbstub()
1452 __debug_frame->psr &= ~PSR_S; gdbstub()
1453 if (__debug_frame->psr & PSR_PS) gdbstub()
1454 __debug_frame->psr |= PSR_S; gdbstub()
1633 ptr = mem2hex(&__debug_frame->psr, ptr, 4, 0); gdbstub()
1712 ptr = hex2mem(ptr, &__debug_frame->psr, 4); gdbstub()
1823 __debug_user_context->i.psr = temp; gdbstub()
H A Ddma.c141 unsigned long psr = __get_PSR(); frv_dma_init() local
145 switch (PSR_IMPLE(psr)) { frv_dma_init()
H A Dhead-uc-fr401.S69 movsg psr,gr3 ; check for FR401/FR401A
209 movsg psr,gr3
H A Dtraps.c504 regs->psr & PSR_S ? "kernel" : "user"); show_regs()
549 frame->psr & PSR_S ? "Kernel Mode" : "User Mode", show_backtrace_regs()
/linux-4.4.14/arch/ia64/sn/kernel/sn2/
H A Dptc_deadlock.S59 mov psrsave=psr // Disable IC (no PMIs)
60 rsm psr.i | psr.dt | psr.ic;;
84 mov psr.l=psrsave;; // Reenable IC
/linux-4.4.14/drivers/gpu/drm/i915/
H A Dintel_psr.c179 if (dev_priv->psr.aux_frame_sync) hsw_psr_enable_sink()
264 uint32_t idle_frames = dev_priv->vbt.psr.idle_frames ? hsw_psr_enable_source()
265 dev_priv->vbt.psr.idle_frames + 1 : 5; hsw_psr_enable_source()
285 if (dev_priv->psr.psr2_support) hsw_psr_enable_source()
298 lockdep_assert_held(&dev_priv->psr.lock); intel_psr_match_conditions()
302 dev_priv->psr.source_ok = false; intel_psr_match_conditions()
327 if (!IS_VALLEYVIEW(dev) && ((dev_priv->vbt.psr.full_link) || intel_psr_match_conditions()
333 dev_priv->psr.source_ok = true; intel_psr_match_conditions()
344 WARN_ON(dev_priv->psr.active); intel_psr_activate()
345 lockdep_assert_held(&dev_priv->psr.lock); intel_psr_activate()
357 dev_priv->psr.active = true; intel_psr_activate()
383 mutex_lock(&dev_priv->psr.lock); intel_psr_enable()
384 if (dev_priv->psr.enabled) { intel_psr_enable()
392 dev_priv->psr.busy_frontbuffer_bits = 0; intel_psr_enable()
397 if (dev_priv->psr.psr2_support) { intel_psr_enable()
401 dev_priv->psr.psr2_support = false; intel_psr_enable()
430 dev_priv->psr.enabled = intel_dp; intel_psr_enable()
432 mutex_unlock(&dev_priv->psr.lock); intel_psr_enable()
444 if (dev_priv->psr.active) { vlv_psr_disable()
456 dev_priv->psr.active = false; vlv_psr_disable()
468 if (dev_priv->psr.active) { hsw_psr_disable()
477 dev_priv->psr.active = false; hsw_psr_disable()
495 mutex_lock(&dev_priv->psr.lock); intel_psr_disable()
496 if (!dev_priv->psr.enabled) { intel_psr_disable()
497 mutex_unlock(&dev_priv->psr.lock); intel_psr_disable()
506 dev_priv->psr.enabled = NULL; intel_psr_disable()
507 mutex_unlock(&dev_priv->psr.lock); intel_psr_disable()
509 cancel_delayed_work_sync(&dev_priv->psr.work); intel_psr_disable()
515 container_of(work, typeof(*dev_priv), psr.work.work); intel_psr_work()
516 struct intel_dp *intel_dp = dev_priv->psr.enabled; intel_psr_work()
538 mutex_lock(&dev_priv->psr.lock); intel_psr_work()
539 intel_dp = dev_priv->psr.enabled; intel_psr_work()
549 if (dev_priv->psr.busy_frontbuffer_bits) intel_psr_work()
554 mutex_unlock(&dev_priv->psr.lock); intel_psr_work()
560 struct intel_dp *intel_dp = dev_priv->psr.enabled; intel_psr_exit()
565 if (!dev_priv->psr.active) intel_psr_exit()
598 dev_priv->psr.active = false; intel_psr_exit()
626 mutex_lock(&dev_priv->psr.lock); intel_psr_single_frame_update()
627 if (!dev_priv->psr.enabled) { intel_psr_single_frame_update()
628 mutex_unlock(&dev_priv->psr.lock); intel_psr_single_frame_update()
632 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; intel_psr_single_frame_update()
644 mutex_unlock(&dev_priv->psr.lock); intel_psr_single_frame_update()
666 mutex_lock(&dev_priv->psr.lock); intel_psr_invalidate()
667 if (!dev_priv->psr.enabled) { intel_psr_invalidate()
668 mutex_unlock(&dev_priv->psr.lock); intel_psr_invalidate()
672 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; intel_psr_invalidate()
676 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; intel_psr_invalidate()
681 mutex_unlock(&dev_priv->psr.lock); intel_psr_invalidate()
705 mutex_lock(&dev_priv->psr.lock); intel_psr_flush()
706 if (!dev_priv->psr.enabled) { intel_psr_flush()
707 mutex_unlock(&dev_priv->psr.lock); intel_psr_flush()
711 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc; intel_psr_flush()
715 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits; intel_psr_flush()
737 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) intel_psr_flush()
738 schedule_delayed_work(&dev_priv->psr.work, intel_psr_flush()
740 mutex_unlock(&dev_priv->psr.lock); intel_psr_flush()
754 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work); intel_psr_init()
755 mutex_init(&dev_priv->psr.lock); intel_psr_init()
H A Dintel_bios.c634 const struct bdb_psr *psr; parse_psr() local
637 psr = find_section(bdb, BDB_PSR); parse_psr()
638 if (!psr) { parse_psr()
643 psr_table = &psr->psr_table[panel_type]; parse_psr()
645 dev_priv->vbt.psr.full_link = psr_table->full_link; parse_psr()
646 dev_priv->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup; parse_psr()
649 dev_priv->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 : parse_psr()
654 dev_priv->vbt.psr.lines_to_wait = PSR_0_LINES_TO_WAIT; parse_psr()
657 dev_priv->vbt.psr.lines_to_wait = PSR_1_LINE_TO_WAIT; parse_psr()
660 dev_priv->vbt.psr.lines_to_wait = PSR_4_LINES_TO_WAIT; parse_psr()
663 dev_priv->vbt.psr.lines_to_wait = PSR_8_LINES_TO_WAIT; parse_psr()
671 dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time; parse_psr()
672 dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time; parse_psr()
H A Di915_debugfs.c2542 mutex_lock(&dev_priv->psr.lock); i915_edp_psr_status()
2543 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support)); i915_edp_psr_status()
2544 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok)); i915_edp_psr_status()
2545 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled)); i915_edp_psr_status()
2546 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active)); i915_edp_psr_status()
2548 dev_priv->psr.busy_frontbuffer_bits); i915_edp_psr_status()
2550 yesno(work_busy(&dev_priv->psr.work.work))); i915_edp_psr_status()
2580 mutex_unlock(&dev_priv->psr.lock);
H A Dintel_dp.c3995 dev_priv->psr.sink_support = true; intel_dp_get_dpcd()
4003 dev_priv->psr.sink_support = true; intel_dp_get_dpcd()
4007 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false; intel_dp_get_dpcd()
4009 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync; intel_dp_get_dpcd()
4011 dev_priv->psr.psr2_support ? "supported" : "not supported"); intel_dp_get_dpcd()
5533 * FIXME: This needs proper synchronization with psr state for some intel_dp_set_drrs_state()
H A Di915_drv.h1490 } psr; member in struct:intel_vbt_data
1871 struct i915_psr psr; member in struct:drm_i915_private
/linux-4.4.14/arch/arm/mm/
H A Dabort-macro.S12 .macro do_thumb_abort, fsr, pc, psr, tmp
13 tst \psr, #PSR_T_BIT
H A Dabort-lv4t.S8 * : r5 = aborted context psr
/linux-4.4.14/arch/sparc/mm/
H A Dswift.S7 #include <asm/psr.h>
59 rd %psr, %g1
61 wr %g3, 0x0, %psr
99 wr %g1, 0x0, %psr
125 rd %psr, %g1
127 wr %g3, 0x0, %psr
165 wr %g1, 0x0, %psr
H A Dfault_32.c95 "rd %%psr, %0\n\t" lookup_fault()
98 "nop\n" : "=r" (regs.psr)); lookup_fault()
151 if (regs->psr & PSR_PS) compute_si_addr()
175 int from_user = !(regs->psr & PSR_PS); do_sparc_fault()
H A Dtsunami.S9 #include <asm/psr.h>
H A Dsrmmu.c1530 unsigned long mreg, psr; get_srmmu_type() local
1536 mreg = srmmu_get_mmureg(); psr = get_psr(); get_srmmu_type()
1539 psr_typ = (psr >> 28) & 0xf; get_srmmu_type()
1540 psr_vers = (psr >> 24) & 0xf; get_srmmu_type()
1589 if (!prom_getintdefault(cpunode, "psr-implementation", 1) && get_srmmu_type()
1590 prom_getintdefault(cpunode, "psr-version", 1) == 5) { get_srmmu_type()
H A Dviking.S10 #include <asm/psr.h>
H A Dhypersparc.S8 #include <asm/psr.h>
/linux-4.4.14/arch/arm/kernel/
H A Dopcodes.c55 asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr) arm_check_condition() argument
58 u32 psr_cond = psr >> 28; arm_check_condition()
H A Dprocess.c119 printk("pc : [<%08lx>] lr : [<%08lx>] psr: %08lx\n" __show_regs()
H A Dentry-armv.S54 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5
71 @ r5 - aborted context psr
/linux-4.4.14/arch/ia64/include/asm/sn/
H A Drw_mmr.h16 * pio_atomic_phys_write_mmrs - atomically write 1 or 2 MMRs with psr.ic=0
/linux-4.4.14/drivers/cpufreq/
H A Dmaple-cpufreq.c95 unsigned long psr = scom970_read(SCOM_PSR); maple_scom_switch_freq() local
97 if ((psr & PSR_CMD_RECEIVED) == 0 && maple_scom_switch_freq()
98 (((psr >> PSR_CUR_SPEED_SHIFT) ^ maple_scom_switch_freq()
102 if (psr & PSR_CMD_COMPLETED) maple_scom_switch_freq()
117 unsigned long psr = scom970_read(SCOM_PSR); maple_scom_query_freq() local
121 if ((((psr >> PSR_CUR_SPEED_SHIFT) ^ maple_scom_query_freq()
H A Dpmac64-cpufreq.c169 unsigned long psr = scom970_read(SCOM_PSR); g5_scom_switch_freq() local
171 if ((psr & PSR_CMD_RECEIVED) == 0 && g5_scom_switch_freq()
172 (((psr >> PSR_CUR_SPEED_SHIFT) ^ g5_scom_switch_freq()
176 if (psr & PSR_CMD_COMPLETED) g5_scom_switch_freq()
195 unsigned long psr = scom970_read(SCOM_PSR); g5_scom_query_freq() local
199 if ((((psr >> PSR_CUR_SPEED_SHIFT) ^ g5_scom_query_freq()
/linux-4.4.14/arch/sparc/lib/
H A Dlocks.S10 #include <asm/psr.h>
/linux-4.4.14/arch/powerpc/sysdev/
H A Dfsl_gtm.c176 u8 psr; gtm_set_ref_timer16() local
187 * We have two 8 bit prescalers -- primary and secondary (psr, sps), gtm_set_ref_timer16()
189 * 16 * (psr + 1) * (sps + 1). Though, for CPM2 GTMs we losing psr. gtm_set_ref_timer16()
200 psr = 0; gtm_set_ref_timer16()
203 psr = 256 - 1; gtm_set_ref_timer16()
219 out_be16(tmr->gtpsr, psr); gtm_set_ref_timer16()
/linux-4.4.14/drivers/net/can/m_can/
H A Dm_can.c639 static int m_can_handle_state_errors(struct net_device *dev, u32 psr) m_can_handle_state_errors() argument
644 if ((psr & PSR_EW) && m_can_handle_state_errors()
651 if ((psr & PSR_EP) && m_can_handle_state_errors()
658 if ((psr & PSR_BO) && m_can_handle_state_errors()
684 static inline bool is_lec_err(u32 psr) is_lec_err() argument
686 psr &= LEC_UNUSED; is_lec_err()
688 return psr && (psr != LEC_UNUSED); is_lec_err()
692 u32 psr) m_can_handle_bus_errors()
702 is_lec_err(psr)) m_can_handle_bus_errors()
703 work_done += m_can_handle_lec_err(dev, psr & LEC_UNUSED); m_can_handle_bus_errors()
716 u32 irqstatus, psr; m_can_poll() local
722 psr = m_can_read(priv, M_CAN_PSR); m_can_poll()
724 work_done += m_can_handle_state_errors(dev, psr); m_can_poll()
727 work_done += m_can_handle_bus_errors(dev, irqstatus, psr); m_can_poll()
691 m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus, u32 psr) m_can_handle_bus_errors() argument
/linux-4.4.14/arch/m68k/include/asm/
H A Dbvme6000hw.h27 pad_n[3], psr, member in struct:__anon1778
H A Dtraps.h117 /* bits for 68030 MMU status register (mmusr,psr) */
/linux-4.4.14/arch/m68k/mm/
H A Dcache.c55 "pmove %%psr,%1" virt_to_phys_slow()
/linux-4.4.14/arch/ia64/include/uapi/asm/
H A Dgcc_intrin.h37 asm volatile ("mov psr.l=%0" :: "r"(val) : "memory"); \
74 asm volatile ("mov %0=psr" : "=r"(ia64_intri_res)); \
612 "(p6) ssm psr.i;" \
613 "(p7) rsm psr.i;;" \
H A Dptrace.h88 unsigned long cr_ipsr; /* interrupted task's psr */
/linux-4.4.14/drivers/spi/
H A Dspi-s3c64xx.c829 u32 psr, speed; s3c64xx_spi_setup() local
837 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1; s3c64xx_spi_setup()
838 psr &= S3C64XX_SPI_PSR_MASK; s3c64xx_spi_setup()
839 if (psr == S3C64XX_SPI_PSR_MASK) s3c64xx_spi_setup()
840 psr--; s3c64xx_spi_setup()
842 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); s3c64xx_spi_setup()
844 if (psr+1 < S3C64XX_SPI_PSR_MASK) { s3c64xx_spi_setup()
845 psr++; s3c64xx_spi_setup()
852 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); s3c64xx_spi_setup()
/linux-4.4.14/arch/frv/include/uapi/asm/
H A Dregisters.h77 unsigned long psr; /* Processor Status Register */ member in struct:pt_regs
168 unsigned long psr; /* Processor Status Register */ member in struct:user_int_regs
/linux-4.4.14/arch/ia64/mm/
H A Dfault.c242 * bit in the psr to ensure forward progress. (Target register will get a ia64_do_page_fault()
265 * bit in the psr to ensure forward progress. (Target register will get a ia64_do_page_fault()
H A Dtlb.c428 unsigned long psr; ia64_itr_entry() local
493 psr = ia64_clear_ic(); ia64_itr_entry()
512 ia64_set_psr(psr); ia64_itr_entry()
/linux-4.4.14/arch/powerpc/boot/
H A D4xx.c557 u32 psr = mfdcr(DCRN_405_CPC0_PSR); ibm405gp_fixup_clocks() local
574 if (!(psr & 0x00001000)) /* PCI async mode enable == 0 */ ibm405gp_fixup_clocks()
575 if (psr & 0x00000020) /* New mode enable */ ibm405gp_fixup_clocks()
579 else if (psr & 0x00000020) /* New mode enable */ ibm405gp_fixup_clocks()
580 if (psr & 0x00000800) /* PerClk synch mode */ ibm405gp_fixup_clocks()
/linux-4.4.14/drivers/media/common/saa7146/
H A Dsaa7146_core.c333 u32 psr = saa7146_read(dev, PSR); interrupt_hw() local
335 pr_warn("%s: unexpected i2c irq: isr %08x psr %08x ssr %08x\n", interrupt_hw()
336 dev->name, isr, psr, ssr); interrupt_hw()
/linux-4.4.14/arch/score/kernel/
H A Dptrace.c49 /* r0 - r31, cel, ceh, sr0, sr1, sr2, epc, ema, psr, ecr, condition */ genregs_get()
77 /* r0 - r31, cel, ceh, sr0, sr1, sr2, epc, ema, psr, ecr, condition */ genregs_set()
/linux-4.4.14/arch/avr32/mach-at32ap/
H A Dpio.c339 u32 psr, osr, imr, pdsr, pusr, ifsr, mdsr; pio_bank_show() local
344 psr = pio_readl(pio, PSR); pio_bank_show()
/linux-4.4.14/sound/soc/fsl/
H A Dfsl_esai.c114 * This function is used to calculate the divisors of psr, pm, fp and it is
126 u32 psr, pm = 999, maxfp, prod, sub, savesub, i, j; fsl_esai_divisor_cal() local
144 psr = ratio <= 256 * maxfp ? ESAI_xCCR_xPSR_BYPASS : ESAI_xCCR_xPSR_DIV8; fsl_esai_divisor_cal()
147 savesub = (psr ? 1 : 8) * 256 * maxfp / 1000; fsl_esai_divisor_cal()
153 prod = (psr ? 1 : 8) * i * j; fsl_esai_divisor_cal()
186 psr | ESAI_xCCR_xPM(pm)); fsl_esai_divisor_cal()
H A Dfsl_ssi.c648 u32 pm = 999, div2, psr, stccr, mask, afreq, factor, i; fsl_ssi_set_bclk() local
667 psr = 0; fsl_ssi_set_bclk()
670 factor = (div2 + 1) * (7 * psr + 1) * 2; fsl_ssi_set_bclk()
703 if (sub < savesub && !(i == 0 && psr == 0 && div2 == 0)) { fsl_ssi_set_bclk()
721 (psr ? CCSR_SSI_SxCCR_PSR : 0); fsl_ssi_set_bclk()
/linux-4.4.14/drivers/net/ethernet/agere/
H A Det131x.h354 * 11-0: psr ndes
362 * 12: psr avail wrap
363 * 11-0: psr avail
370 * 12: psr full wrap
371 * 11-0: psr full
H A Det131x.c2189 struct pkt_stat_desc *psr; nic_rx_pkts() local
2213 psr = (struct pkt_stat_desc *)(rx_local->ps_ring_virtaddr) + nic_rx_pkts()
2219 len = psr->word1 & 0xFFFF; nic_rx_pkts()
2220 ring_index = (psr->word1 >> 26) & 0x03; nic_rx_pkts()
2222 buff_index = (psr->word1 >> 16) & 0x3FF; nic_rx_pkts()
2223 word0 = psr->word0; nic_rx_pkts()
2229 /* Clear psr full and toggle the wrap bit */ nic_rx_pkts()
/linux-4.4.14/arch/m68k/kernel/
H A Dtraps.c534 "pmove %%psr,%1" bus_error030()
543 "pmove %%psr,%0" bus_error030()
584 "pmove %%psr,%0" bus_error030()
642 "pmove %%psr,%1" bus_error030()
651 "pmove %%psr,%0" bus_error030()
/linux-4.4.14/drivers/net/wan/
H A Dn2.c159 u8 psr = inb(card->io + N2_PSR); openwin() local
160 outb((psr & ~PSR_PAGEBITS) | page, card->io + N2_PSR); openwin()
/linux-4.4.14/arch/unicore32/kernel/
H A Dprocess.c141 printk(KERN_DEFAULT "pc : [<%08lx>] lr : [<%08lx>] psr: %08lx\n" __show_regs()
/linux-4.4.14/arch/arm/include/asm/
H A Dopcodes.h14 extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
/linux-4.4.14/sound/soc/samsung/
H A Di2s.c813 u32 psr; config_setup() local
859 psr = i2s->rclk_srcrate / i2s->frmclk / rfs; config_setup()
860 writel(((psr - 1) << 8) | PSR_PSREN, i2s->addr + I2SPSR); config_setup()
863 i2s->rclk_srcrate, psr, rfs, bfs); config_setup()
/linux-4.4.14/arch/frv/mm/
H A Dtlb-miss.S74 movgs gr31,psr
113 movgs gr31,psr
/linux-4.4.14/drivers/net/ethernet/renesas/
H A Dravb_main.c653 u32 ecsr, psr; ravb_emac_interrupt() local
663 psr = ravb_read(ndev, PSR); ravb_emac_interrupt()
665 psr ^= PSR_LMON; ravb_emac_interrupt()
666 if (!(psr & PSR_LMON)) { ravb_emac_interrupt()
/linux-4.4.14/arch/arm/probes/kprobes/
H A Dcore.c558 "ldr r2, [sp, %4] \n\t" /* r2 = saved psr */ jprobe_return()
/linux-4.4.14/drivers/atm/
H A Dfore200e.h774 volatile u32 __iomem * psr; /* address of PCI specific register */ member in struct:fore200e_pca_regs
H A Dfore200e.c503 int irq_posted = readl(fore200e->regs.pca.psr); fore200e_pca_irq_check()
547 fore200e->regs.pca.psr = fore200e->virt_base + PCA200E_PSR_OFFSET; fore200e_pca_map()
/linux-4.4.14/drivers/media/pci/ttpci/
H A Dav7110.c391 printk("DEBI irq oops @ %ld, psr:0x%08x, ssr:0x%08x\n", debiirq()
499 printk("dvb-ttpci: GPIO0 irq oops @ %ld, psr:0x%08x, ssr:0x%08x\n", gpioirq()
/linux-4.4.14/arch/x86/kernel/
H A Dapm_32.c258 * [no-]broken[-_]psr BIOS has a broken GetPowerStatus call
1900 if ((strncmp(str, "broken-psr", 10) == 0) || apm_setup()

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