Searched refs:postdiv2 (Results 1 - 4 of 4) sorted by relevance
| /linux-4.4.14/drivers/clk/pistachio/ |
| H A D | clk-pll.c | 244 params->postdiv2 != old_postdiv2)) pll_gf40lp_frac_set_rate()
247 if (params->postdiv2 > params->postdiv1) pll_gf40lp_frac_set_rate()
248 pr_warn("%s: postdiv2 should not exceed postdiv1\n", name); pll_gf40lp_frac_set_rate()
257 (params->postdiv2 << PLL_FRAC_CTRL2_POSTDIV2_SHIFT); pll_gf40lp_frac_set_rate()
276 u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate; pll_gf40lp_frac_recalc_rate() local
285 postdiv2 = (val >> PLL_FRAC_CTRL2_POSTDIV2_SHIFT) & pll_gf40lp_frac_recalc_rate()
296 rate = do_div_round_closest(rate, (prediv * postdiv1 * postdiv2) << 24); pll_gf40lp_frac_recalc_rate()
390 params->postdiv2 != old_postdiv2)) pll_gf40lp_laint_set_rate()
393 if (params->postdiv2 > params->postdiv1) pll_gf40lp_laint_set_rate()
394 pr_warn("%s: postdiv2 should not exceed postdiv1\n", name); pll_gf40lp_laint_set_rate()
403 (params->postdiv2 << PLL_INT_CTRL1_POSTDIV2_SHIFT); pll_gf40lp_laint_set_rate()
416 u32 val, prediv, fbdiv, postdiv1, postdiv2; pll_gf40lp_laint_recalc_rate() local
424 postdiv2 = (val >> PLL_INT_CTRL1_POSTDIV2_SHIFT) & pll_gf40lp_laint_recalc_rate()
428 rate = do_div_round_closest(rate, prediv * postdiv1 * postdiv2); pll_gf40lp_laint_recalc_rate()
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| H A D | clk.h | 103 unsigned long long postdiv2; member in struct:pistachio_pll_rate_table
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| /linux-4.4.14/arch/mips/ar7/ |
| H A D | clock.c | 86 u32 postdiv2; member in struct:tnetd7200_clock
275 int prediv, int postdiv, int postdiv2, int mul, u32 frequency) tnetd7200_set_clock()
279 "postdiv = %d, postdiv2 = %d, mul = %d\n", tnetd7200_set_clock()
280 base, frequency, prediv, postdiv, postdiv2, mul); tnetd7200_set_clock()
297 writel(DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F), &clock->postdiv2); tnetd7200_set_clock()
274 tnetd7200_set_clock(int base, struct tnetd7200_clock *clock, int prediv, int postdiv, int postdiv2, int mul, u32 frequency) tnetd7200_set_clock() argument
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| /linux-4.4.14/drivers/gpu/drm/msm/dsi/pll/ |
| H A D | dsi_pll_28nm.c | 151 /* Force postdiv2 to be div-4 */ dsi_pll_28nm_clk_set_rate()
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