Searched refs:pllreg (Results 1 - 6 of 6) sorted by relevance

/linux-4.4.14/arch/arm/mach-lpc32xx/
H A Dtimer.c92 u32 clkrate, pllreg; lpc32xx_timer_init() local
111 pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF; lpc32xx_timer_init()
112 clkrate = clk_get_pllrate_from_reg(clkrate, pllreg); lpc32xx_timer_init()
H A Dclock.c260 u32 clkin, pllreg; local_update_armpll_rate() local
263 pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF; local_update_armpll_rate()
265 clk_armpll.rate = clk_get_pllrate_from_reg(clkin, pllreg); local_update_armpll_rate()
/linux-4.4.14/sound/pci/pcxhr/
H A Dpcxhr_mix22.c324 unsigned int *pllreg, hr222_pll_freq_register()
334 *pllreg = reg + 0xC00; hr222_pll_freq_register()
336 *pllreg = reg + 0x800; hr222_pll_freq_register()
338 *pllreg = reg & 0x1ff; hr222_pll_freq_register()
340 *pllreg = ((reg >> 1) & 0x1ff) + 0x200; hr222_pll_freq_register()
343 *pllreg = ((reg >> 2) & 0x1ff) + 0x400; hr222_pll_freq_register()
355 unsigned int speed, pllreg = 0; hr222_sub_set_clock() local
361 err = hr222_pll_freq_register(rate, &pllreg, &realfreq); hr222_sub_set_clock()
385 PCXHR_OUTPB(mgr, PCXHR_XLX_HIFREQ, pllreg >> 8); hr222_sub_set_clock()
386 PCXHR_OUTPB(mgr, PCXHR_XLX_LOFREQ, pllreg & 0xff); hr222_sub_set_clock()
410 dev_dbg(&mgr->pci->dev, "set_clock to %dHz (realfreq=%d pllreg=%x)\n", hr222_sub_set_clock()
411 rate, realfreq, pllreg); hr222_sub_set_clock()
323 hr222_pll_freq_register(unsigned int freq, unsigned int *pllreg, unsigned int *realfreq) hr222_pll_freq_register() argument
H A Dpcxhr.c197 static int pcxhr_pll_freq_register(unsigned int freq, unsigned int* pllreg, pcxhr_pll_freq_register() argument
207 *pllreg = reg + 0x800; pcxhr_pll_freq_register()
209 *pllreg = reg & 0x1ff; pcxhr_pll_freq_register()
211 *pllreg = ((reg >> 1) & 0x1ff) + 0x200; pcxhr_pll_freq_register()
214 *pllreg = ((reg >> 2) & 0x1ff) + 0x400; pcxhr_pll_freq_register()
251 unsigned int val, realfreq, pllreg; pcxhr_get_clock_reg() local
277 err = pcxhr_pll_freq_register(rate, &pllreg, &realfreq); pcxhr_get_clock_reg()
282 rmh.cmd[1] = pllreg & MASK_DSP_WORD; pcxhr_get_clock_reg()
283 rmh.cmd[2] = pllreg >> 24; pcxhr_get_clock_reg()
/linux-4.4.14/drivers/bcma/
H A Ddriver_chipcommon_pmu.c337 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
/linux-4.4.14/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.c468 uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF; nv_load_state_ramdac() local
474 clk->pll_prog(clk, pllreg, &regp->pllvals); nv_load_state_ramdac()

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