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Searched refs:pllclk (Results 1 – 6 of 6) sorted by relevance

/linux-4.4.14/arch/arm/mach-w90x900/
Dcpu.c127 unsigned int pllclk, ahbclk, apbclk, val; in nuc900_set_clkval() local
129 pllclk = 0; in nuc900_set_clkval()
135 pllclk = PLL_66MHZ; in nuc900_set_clkval()
141 pllclk = PLL_100MHZ; in nuc900_set_clkval()
147 pllclk = PLL_120MHZ; in nuc900_set_clkval()
153 pllclk = PLL_166MHZ; in nuc900_set_clkval()
159 pllclk = PLL_200MHZ; in nuc900_set_clkval()
165 __raw_writel(pllclk, REG_PLLCON0); in nuc900_set_clkval()
/linux-4.4.14/Documentation/devicetree/bindings/clock/
Drenesas,h8s2678-pll-clock.txt18 pllclk: pllclk {
/linux-4.4.14/arch/h8300/boot/dts/
Dh8s_sim.dts23 pllclk: pllclk { label
31 clocks = <&pllclk>;
Dedosk2674.dts24 pllclk: pllclk { label
32 clocks = <&pllclk>;
/linux-4.4.14/drivers/clk/
Dclk-xgene.c72 struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw); in xgene_clk_pll_is_enabled() local
75 data = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_is_enabled()
85 struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw); in xgene_clk_pll_recalc_rate() local
93 pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_recalc_rate()
95 if (pllclk->type == PLL_TYPE_PCP) { in xgene_clk_pll_recalc_rate()
/linux-4.4.14/arch/arm/mach-davinci/
Dda850.c1119 struct clk *pllclk = &pll0_clk; in da850_set_armrate() local
1121 return clk_set_rate(pllclk, index); in da850_set_armrate()