Searched refs:pll_ctl_val (Results 1 - 1 of 1) sorted by relevance

/linux-4.4.14/arch/arm/mach-omap1/
H A Dclock_data.c835 unsigned pll_ctl_val = omap_readw(DPLL_CTL); omap1_clk_init() local
838 if (pll_ctl_val & 0x10) { omap1_clk_init()
840 if (pll_ctl_val & 0xf80) omap1_clk_init()
841 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7; omap1_clk_init()
842 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1; omap1_clk_init()
845 switch (pll_ctl_val & 0xc) { omap1_clk_init()

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