Searched refs:pll_con0 (Results 1 - 1 of 1) sorted by relevance
| /linux-4.4.14/drivers/clk/samsung/ |
| H A D | clk-pll.c | 252 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1; samsung_pll36xx_recalc_rate() local
256 pll_con0 = __raw_readl(pll->con_reg); samsung_pll36xx_recalc_rate()
258 mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK; samsung_pll36xx_recalc_rate()
259 pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK; samsung_pll36xx_recalc_rate()
260 sdiv = (pll_con0 >> PLL36XX_SDIV_SHIFT) & PLL36XX_SDIV_MASK; samsung_pll36xx_recalc_rate()
271 const struct samsung_pll_rate_table *rate, u32 pll_con0, u32 pll_con1) samsung_pll36xx_mpk_change()
275 old_mdiv = (pll_con0 >> PLL36XX_MDIV_SHIFT) & PLL36XX_MDIV_MASK; samsung_pll36xx_mpk_change()
276 old_pdiv = (pll_con0 >> PLL36XX_PDIV_SHIFT) & PLL36XX_PDIV_MASK; samsung_pll36xx_mpk_change()
287 u32 tmp, pll_con0, pll_con1; samsung_pll36xx_set_rate() local
297 pll_con0 = __raw_readl(pll->con_reg); samsung_pll36xx_set_rate()
300 if (!(samsung_pll36xx_mpk_change(rate, pll_con0, pll_con1))) { samsung_pll36xx_set_rate()
302 pll_con0 &= ~(PLL36XX_SDIV_MASK << PLL36XX_SDIV_SHIFT); samsung_pll36xx_set_rate()
303 pll_con0 |= (rate->sdiv << PLL36XX_SDIV_SHIFT); samsung_pll36xx_set_rate()
304 __raw_writel(pll_con0, pll->con_reg); samsung_pll36xx_set_rate()
313 pll_con0 &= ~((PLL36XX_MDIV_MASK << PLL36XX_MDIV_SHIFT) | samsung_pll36xx_set_rate()
316 pll_con0 |= (rate->mdiv << PLL36XX_MDIV_SHIFT) | samsung_pll36xx_set_rate()
319 __raw_writel(pll_con0, pll->con_reg); samsung_pll36xx_set_rate()
383 static bool samsung_pll45xx_mp_change(u32 pll_con0, u32 pll_con1, samsung_pll45xx_mp_change() argument
388 old_mdiv = (pll_con0 >> PLL45XX_MDIV_SHIFT) & PLL45XX_MDIV_MASK; samsung_pll45xx_mp_change()
389 old_pdiv = (pll_con0 >> PLL45XX_PDIV_SHIFT) & PLL45XX_PDIV_MASK; samsung_pll45xx_mp_change()
513 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift; samsung_pll46xx_recalc_rate() local
516 pll_con0 = __raw_readl(pll->con_reg); samsung_pll46xx_recalc_rate()
518 mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & ((pll->type == pll_1460x) ? samsung_pll46xx_recalc_rate()
520 pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; samsung_pll46xx_recalc_rate()
521 sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK; samsung_pll46xx_recalc_rate()
534 static bool samsung_pll46xx_mpk_change(u32 pll_con0, u32 pll_con1, samsung_pll46xx_mpk_change() argument
539 old_mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK; samsung_pll46xx_mpk_change()
540 old_pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK; samsung_pll46xx_mpk_change()
696 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1; samsung_pll6553_recalc_rate() local
699 pll_con0 = __raw_readl(pll->con_reg); samsung_pll6553_recalc_rate()
701 mdiv = (pll_con0 >> PLL6553_MDIV_SHIFT) & PLL6553_MDIV_MASK; samsung_pll6553_recalc_rate()
702 pdiv = (pll_con0 >> PLL6553_PDIV_SHIFT) & PLL6553_PDIV_MASK; samsung_pll6553_recalc_rate()
703 sdiv = (pll_con0 >> PLL6553_SDIV_SHIFT) & PLL6553_SDIV_MASK; samsung_pll6553_recalc_rate()
1088 u32 mdiv, pdiv, sdiv, pll_con0, pll_con2; samsung_pll2650xx_recalc_rate() local
1092 pll_con0 = __raw_readl(pll->con_reg); samsung_pll2650xx_recalc_rate()
1094 mdiv = (pll_con0 >> PLL2650XX_MDIV_SHIFT) & PLL2650XX_MDIV_MASK; samsung_pll2650xx_recalc_rate()
1095 pdiv = (pll_con0 >> PLL2650XX_PDIV_SHIFT) & PLL2650XX_PDIV_MASK; samsung_pll2650xx_recalc_rate()
1096 sdiv = (pll_con0 >> PLL2650XX_SDIV_SHIFT) & PLL2650XX_SDIV_MASK; samsung_pll2650xx_recalc_rate()
1110 u32 tmp, pll_con0, pll_con2; samsung_pll2650xx_set_rate() local
1120 pll_con0 = __raw_readl(pll->con_reg); samsung_pll2650xx_set_rate()
1124 pll_con0 &= ~(PLL2650XX_MDIV_MASK << PLL2650XX_MDIV_SHIFT | samsung_pll2650xx_set_rate()
1127 pll_con0 |= rate->mdiv << PLL2650XX_MDIV_SHIFT; samsung_pll2650xx_set_rate()
1128 pll_con0 |= rate->pdiv << PLL2650XX_PDIV_SHIFT; samsung_pll2650xx_set_rate()
1129 pll_con0 |= rate->sdiv << PLL2650XX_SDIV_SHIFT; samsung_pll2650xx_set_rate()
1130 pll_con0 |= 1 << PLL2650XX_PLL_ENABLE_SHIFT; samsung_pll2650xx_set_rate()
1131 pll_con0 |= 1 << PLL2650XX_PLL_FOUTMASK_SHIFT; samsung_pll2650xx_set_rate()
1140 __raw_writel(pll_con0, pll->con_reg); samsung_pll2650xx_set_rate()
270 samsung_pll36xx_mpk_change( const struct samsung_pll_rate_table *rate, u32 pll_con0, u32 pll_con1) samsung_pll36xx_mpk_change() argument
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