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Searched refs:pipe_offset (Results 1 – 6 of 6) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/radeon/
Devergreen.c1923 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; in evergreen_line_buffer_adjust() local
1964 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in evergreen_line_buffer_adjust()
1967 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in evergreen_line_buffer_adjust()
2265 u32 pipe_offset = radeon_crtc->crtc_id * 16; in evergreen_program_watermarks() local
2381 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); in evergreen_program_watermarks()
2385 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); in evergreen_program_watermarks()
2386 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, in evergreen_program_watermarks()
2390 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); in evergreen_program_watermarks()
2393 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); in evergreen_program_watermarks()
2394 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset, in evergreen_program_watermarks()
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Dsi.c1917 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; in dce6_line_buffer_adjust() local
1947 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce6_line_buffer_adjust()
1950 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in dce6_line_buffer_adjust()
Dcik.c9098 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; in dce8_line_buffer_adjust() local
9130 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce8_line_buffer_adjust()
9133 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in dce8_line_buffer_adjust()
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Ddce_v11_0.c792 u32 pipe_offset = amdgpu_crtc->crtc_id; in dce_v11_0_line_buffer_adjust() local
825 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); in dce_v11_0_line_buffer_adjust()
827 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); in dce_v11_0_line_buffer_adjust()
830 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); in dce_v11_0_line_buffer_adjust()
Ddce_v10_0.c804 u32 pipe_offset = amdgpu_crtc->crtc_id; in dce_v10_0_line_buffer_adjust() local
837 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); in dce_v10_0_line_buffer_adjust()
839 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); in dce_v10_0_line_buffer_adjust()
842 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); in dce_v10_0_line_buffer_adjust()
Ddce_v8_0.c749 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; in dce_v8_0_line_buffer_adjust() local
782 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce_v8_0_line_buffer_adjust()
785 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in dce_v8_0_line_buffer_adjust()