Searched refs:phy_ctl (Results 1 – 5 of 5) sorted by relevance
260 u16 phy_ctl = 0; in b43_generate_txhdr() local377 phy_ctl |= B43_TXH_PHY_ENC_OFDM; in b43_generate_txhdr()379 phy_ctl |= B43_TXH_PHY_ENC_CCK; in b43_generate_txhdr()381 phy_ctl |= B43_TXH_PHY_SHORTPRMBL; in b43_generate_txhdr()385 phy_ctl |= B43_TXH_PHY_ANT01AUTO; in b43_generate_txhdr()388 phy_ctl |= B43_TXH_PHY_ANT0; in b43_generate_txhdr()391 phy_ctl |= B43_TXH_PHY_ANT1; in b43_generate_txhdr()394 phy_ctl |= B43_TXH_PHY_ANT2; in b43_generate_txhdr()397 phy_ctl |= B43_TXH_PHY_ANT3; in b43_generate_txhdr()570 txhdr->phy_ctl = cpu_to_le16(phy_ctl); in b43_generate_txhdr()
28 __le16 phy_ctl; /* PHY TX control */ member
202 u16 phy_ctl = 0; in generate_txhdr_fw3() local277 phy_ctl |= B43legacy_TX4_PHY_ENC_OFDM; in generate_txhdr_fw3()279 phy_ctl |= B43legacy_TX4_PHY_SHORTPRMBL; in generate_txhdr_fw3()280 phy_ctl |= B43legacy_TX4_PHY_ANTLAST; in generate_txhdr_fw3()353 txhdr->phy_ctl = cpu_to_le16(phy_ctl); in generate_txhdr_fw3()
127 u32 val, phy_ctl; in pcie_phy_read() local135 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC; in pcie_phy_read()136 writel(phy_ctl, dbi_base + PCIE_PHY_CTRL); in pcie_phy_read()