Searched refs:pgpuobj (Results 1 - 18 of 18) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/cipher/
H A Dg84.c35 int align, struct nvkm_gpuobj **pgpuobj) g84_cipher_oclass_bind()
38 align, false, parent, pgpuobj); g84_cipher_oclass_bind()
40 nvkm_kmap(*pgpuobj); g84_cipher_oclass_bind()
41 nvkm_wo32(*pgpuobj, 0x00, object->oclass); g84_cipher_oclass_bind()
42 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); g84_cipher_oclass_bind()
43 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); g84_cipher_oclass_bind()
44 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); g84_cipher_oclass_bind()
45 nvkm_done(*pgpuobj); g84_cipher_oclass_bind()
57 int align, struct nvkm_gpuobj **pgpuobj) g84_cipher_cclass_bind()
60 align, true, parent, pgpuobj); g84_cipher_cclass_bind()
34 g84_cipher_oclass_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, int align, struct nvkm_gpuobj **pgpuobj) g84_cipher_oclass_bind() argument
56 g84_cipher_cclass_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, int align, struct nvkm_gpuobj **pgpuobj) g84_cipher_cclass_bind() argument
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/dma/
H A Dusergf100.c42 int align, struct nvkm_gpuobj **pgpuobj) gf100_dmaobj_bind()
48 ret = nvkm_gpuobj_new(device, 24, align, false, parent, pgpuobj); gf100_dmaobj_bind()
50 nvkm_kmap(*pgpuobj); gf100_dmaobj_bind()
51 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0); gf100_dmaobj_bind()
52 nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit)); gf100_dmaobj_bind()
53 nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start)); gf100_dmaobj_bind()
54 nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 | gf100_dmaobj_bind()
56 nvkm_wo32(*pgpuobj, 0x10, 0x00000000); gf100_dmaobj_bind()
57 nvkm_wo32(*pgpuobj, 0x14, dmaobj->flags5); gf100_dmaobj_bind()
58 nvkm_done(*pgpuobj); gf100_dmaobj_bind()
41 gf100_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent, int align, struct nvkm_gpuobj **pgpuobj) gf100_dmaobj_bind() argument
H A Dusergf119.c41 int align, struct nvkm_gpuobj **pgpuobj) gf119_dmaobj_bind()
47 ret = nvkm_gpuobj_new(device, 24, align, false, parent, pgpuobj); gf119_dmaobj_bind()
49 nvkm_kmap(*pgpuobj); gf119_dmaobj_bind()
50 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0); gf119_dmaobj_bind()
51 nvkm_wo32(*pgpuobj, 0x04, dmaobj->base.start >> 8); gf119_dmaobj_bind()
52 nvkm_wo32(*pgpuobj, 0x08, dmaobj->base.limit >> 8); gf119_dmaobj_bind()
53 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); gf119_dmaobj_bind()
54 nvkm_wo32(*pgpuobj, 0x10, 0x00000000); gf119_dmaobj_bind()
55 nvkm_wo32(*pgpuobj, 0x14, 0x00000000); gf119_dmaobj_bind()
56 nvkm_done(*pgpuobj); gf119_dmaobj_bind()
40 gf119_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent, int align, struct nvkm_gpuobj **pgpuobj) gf119_dmaobj_bind() argument
H A Dusernv50.c42 int align, struct nvkm_gpuobj **pgpuobj) nv50_dmaobj_bind()
48 ret = nvkm_gpuobj_new(device, 24, align, false, parent, pgpuobj); nv50_dmaobj_bind()
50 nvkm_kmap(*pgpuobj); nv50_dmaobj_bind()
51 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0); nv50_dmaobj_bind()
52 nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit)); nv50_dmaobj_bind()
53 nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start)); nv50_dmaobj_bind()
54 nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 | nv50_dmaobj_bind()
56 nvkm_wo32(*pgpuobj, 0x10, 0x00000000); nv50_dmaobj_bind()
57 nvkm_wo32(*pgpuobj, 0x14, dmaobj->flags5); nv50_dmaobj_bind()
58 nvkm_done(*pgpuobj); nv50_dmaobj_bind()
41 nv50_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent, int align, struct nvkm_gpuobj **pgpuobj) nv50_dmaobj_bind() argument
H A Dusernv04.c42 int align, struct nvkm_gpuobj **pgpuobj) nv04_dmaobj_bind()
55 return nvkm_gpuobj_wrap(pgt, pgpuobj); nv04_dmaobj_bind()
62 ret = nvkm_gpuobj_new(device, 16, align, false, parent, pgpuobj); nv04_dmaobj_bind()
64 nvkm_kmap(*pgpuobj); nv04_dmaobj_bind()
65 nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0 | (adjust << 20)); nv04_dmaobj_bind()
66 nvkm_wo32(*pgpuobj, 0x04, length); nv04_dmaobj_bind()
67 nvkm_wo32(*pgpuobj, 0x08, dmaobj->flags2 | offset); nv04_dmaobj_bind()
68 nvkm_wo32(*pgpuobj, 0x0c, dmaobj->flags2 | offset); nv04_dmaobj_bind()
69 nvkm_done(*pgpuobj); nv04_dmaobj_bind()
41 nv04_dmaobj_bind(struct nvkm_dmaobj *base, struct nvkm_gpuobj *parent, int align, struct nvkm_gpuobj **pgpuobj) nv04_dmaobj_bind() argument
H A Duser.c36 int align, struct nvkm_gpuobj **pgpuobj) nvkm_dmaobj_bind()
39 return dmaobj->func->bind(dmaobj, gpuobj, align, pgpuobj); nvkm_dmaobj_bind()
35 nvkm_dmaobj_bind(struct nvkm_object *base, struct nvkm_gpuobj *gpuobj, int align, struct nvkm_gpuobj **pgpuobj) nvkm_dmaobj_bind() argument
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
H A Dnv50.c37 int align, struct nvkm_gpuobj **pgpuobj) nv50_mpeg_cclass_bind()
40 align, true, parent, pgpuobj); nv50_mpeg_cclass_bind()
42 nvkm_kmap(*pgpuobj); nv50_mpeg_cclass_bind()
43 nvkm_wo32(*pgpuobj, 0x70, 0x00801ec1); nv50_mpeg_cclass_bind()
44 nvkm_wo32(*pgpuobj, 0x7c, 0x0000037c); nv50_mpeg_cclass_bind()
45 nvkm_done(*pgpuobj); nv50_mpeg_cclass_bind()
36 nv50_mpeg_cclass_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, int align, struct nvkm_gpuobj **pgpuobj) nv50_mpeg_cclass_bind() argument
H A Dnv31.c40 int align, struct nvkm_gpuobj **pgpuobj) nv31_mpeg_object_bind()
43 false, parent, pgpuobj); nv31_mpeg_object_bind()
45 nvkm_kmap(*pgpuobj); nv31_mpeg_object_bind()
46 nvkm_wo32(*pgpuobj, 0x00, object->oclass); nv31_mpeg_object_bind()
47 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); nv31_mpeg_object_bind()
48 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); nv31_mpeg_object_bind()
49 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); nv31_mpeg_object_bind()
50 nvkm_done(*pgpuobj); nv31_mpeg_object_bind()
39 nv31_mpeg_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, int align, struct nvkm_gpuobj **pgpuobj) nv31_mpeg_object_bind() argument
H A Dnv44.c53 int align, struct nvkm_gpuobj **pgpuobj) nv44_mpeg_chan_bind()
57 align, true, parent, pgpuobj); nv44_mpeg_chan_bind()
59 chan->inst = (*pgpuobj)->addr; nv44_mpeg_chan_bind()
60 nvkm_kmap(*pgpuobj); nv44_mpeg_chan_bind()
61 nvkm_wo32(*pgpuobj, 0x78, 0x02001ec1); nv44_mpeg_chan_bind()
62 nvkm_done(*pgpuobj); nv44_mpeg_chan_bind()
52 nv44_mpeg_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, int align, struct nvkm_gpuobj **pgpuobj) nv44_mpeg_chan_bind() argument
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/core/
H A Dgpuobj.c192 nvkm_gpuobj_del(struct nvkm_gpuobj **pgpuobj) nvkm_gpuobj_del() argument
194 struct nvkm_gpuobj *gpuobj = *pgpuobj; nvkm_gpuobj_del()
200 kfree(*pgpuobj); nvkm_gpuobj_del()
201 *pgpuobj = NULL; nvkm_gpuobj_del()
207 struct nvkm_gpuobj *parent, struct nvkm_gpuobj **pgpuobj) nvkm_gpuobj_new()
212 if (!(gpuobj = *pgpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL))) nvkm_gpuobj_new()
217 nvkm_gpuobj_del(pgpuobj); nvkm_gpuobj_new()
247 nvkm_gpuobj_wrap(struct nvkm_memory *memory, struct nvkm_gpuobj **pgpuobj) nvkm_gpuobj_wrap() argument
249 if (!(*pgpuobj = kzalloc(sizeof(**pgpuobj), GFP_KERNEL))) nvkm_gpuobj_wrap()
252 (*pgpuobj)->addr = nvkm_memory_addr(memory); nvkm_gpuobj_wrap()
253 (*pgpuobj)->size = nvkm_memory_size(memory); nvkm_gpuobj_wrap()
206 nvkm_gpuobj_new(struct nvkm_device *device, u32 size, int align, bool zero, struct nvkm_gpuobj *parent, struct nvkm_gpuobj **pgpuobj) nvkm_gpuobj_new() argument
H A Doproxy.c83 int align, struct nvkm_gpuobj **pgpuobj) nvkm_oproxy_bind()
86 parent, align, pgpuobj); nvkm_oproxy_bind()
82 nvkm_oproxy_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, int align, struct nvkm_gpuobj **pgpuobj) nvkm_oproxy_bind() argument
H A Dobject.c103 int align, struct nvkm_gpuobj **pgpuobj) nvkm_object_bind()
106 return object->func->bind(object, gpuobj, align, pgpuobj); nvkm_object_bind()
102 nvkm_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *gpuobj, int align, struct nvkm_gpuobj **pgpuobj) nvkm_object_bind() argument
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv40.c45 int align, struct nvkm_gpuobj **pgpuobj) nv40_gr_object_bind()
48 false, parent, pgpuobj); nv40_gr_object_bind()
50 nvkm_kmap(*pgpuobj); nv40_gr_object_bind()
51 nvkm_wo32(*pgpuobj, 0x00, object->oclass); nv40_gr_object_bind()
52 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); nv40_gr_object_bind()
53 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); nv40_gr_object_bind()
55 nvkm_mo32(*pgpuobj, 0x08, 0x01000000, 0x01000000); nv40_gr_object_bind()
57 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); nv40_gr_object_bind()
58 nvkm_wo32(*pgpuobj, 0x10, 0x00000000); nv40_gr_object_bind()
59 nvkm_done(*pgpuobj); nv40_gr_object_bind()
75 int align, struct nvkm_gpuobj **pgpuobj) nv40_gr_chan_bind()
80 align, true, parent, pgpuobj); nv40_gr_chan_bind()
82 chan->inst = (*pgpuobj)->addr; nv40_gr_chan_bind()
83 nvkm_kmap(*pgpuobj); nv40_gr_chan_bind()
84 nv40_grctx_fill(gr->base.engine.subdev.device, *pgpuobj); nv40_gr_chan_bind()
85 nvkm_wo32(*pgpuobj, 0x00000, chan->inst >> 4); nv40_gr_chan_bind()
86 nvkm_done(*pgpuobj); nv40_gr_chan_bind()
44 nv40_gr_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, int align, struct nvkm_gpuobj **pgpuobj) nv40_gr_object_bind() argument
74 nv40_gr_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, int align, struct nvkm_gpuobj **pgpuobj) nv40_gr_chan_bind() argument
H A Dnv50.c42 int align, struct nvkm_gpuobj **pgpuobj) nv50_gr_object_bind()
45 align, false, parent, pgpuobj); nv50_gr_object_bind()
47 nvkm_kmap(*pgpuobj); nv50_gr_object_bind()
48 nvkm_wo32(*pgpuobj, 0x00, object->oclass); nv50_gr_object_bind()
49 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); nv50_gr_object_bind()
50 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); nv50_gr_object_bind()
51 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); nv50_gr_object_bind()
52 nvkm_done(*pgpuobj); nv50_gr_object_bind()
68 int align, struct nvkm_gpuobj **pgpuobj) nv50_gr_chan_bind()
72 align, true, parent, pgpuobj); nv50_gr_chan_bind()
74 nvkm_kmap(*pgpuobj); nv50_gr_chan_bind()
75 nv50_grctx_fill(gr->base.engine.subdev.device, *pgpuobj); nv50_gr_chan_bind()
76 nvkm_done(*pgpuobj); nv50_gr_chan_bind()
41 nv50_gr_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, int align, struct nvkm_gpuobj **pgpuobj) nv50_gr_object_bind() argument
67 nv50_gr_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, int align, struct nvkm_gpuobj **pgpuobj) nv50_gr_chan_bind() argument
H A Dgf100.c281 int align, struct nvkm_gpuobj **pgpuobj) gf100_gr_chan_bind()
288 align, false, parent, pgpuobj); gf100_gr_chan_bind()
292 nvkm_kmap(*pgpuobj); gf100_gr_chan_bind()
294 nvkm_wo32(*pgpuobj, i, gr->data[i / 4]); gf100_gr_chan_bind()
297 nvkm_wo32(*pgpuobj, 0x00, chan->mmio_nr / 2); gf100_gr_chan_bind()
298 nvkm_wo32(*pgpuobj, 0x04, chan->mmio_vma.offset >> 8); gf100_gr_chan_bind()
300 nvkm_wo32(*pgpuobj, 0xf4, 0); gf100_gr_chan_bind()
301 nvkm_wo32(*pgpuobj, 0xf8, 0); gf100_gr_chan_bind()
302 nvkm_wo32(*pgpuobj, 0x10, chan->mmio_nr / 2); gf100_gr_chan_bind()
303 nvkm_wo32(*pgpuobj, 0x14, lower_32_bits(chan->mmio_vma.offset)); gf100_gr_chan_bind()
304 nvkm_wo32(*pgpuobj, 0x18, upper_32_bits(chan->mmio_vma.offset)); gf100_gr_chan_bind()
305 nvkm_wo32(*pgpuobj, 0x1c, 1); gf100_gr_chan_bind()
306 nvkm_wo32(*pgpuobj, 0x20, 0); gf100_gr_chan_bind()
307 nvkm_wo32(*pgpuobj, 0x28, 0); gf100_gr_chan_bind()
308 nvkm_wo32(*pgpuobj, 0x2c, 0); gf100_gr_chan_bind()
310 nvkm_done(*pgpuobj); gf100_gr_chan_bind()
280 gf100_gr_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, int align, struct nvkm_gpuobj **pgpuobj) gf100_gr_chan_bind() argument
H A Dnv04.c1044 int align, struct nvkm_gpuobj **pgpuobj) nv04_gr_object_bind()
1047 false, parent, pgpuobj); nv04_gr_object_bind()
1049 nvkm_kmap(*pgpuobj); nv04_gr_object_bind()
1050 nvkm_wo32(*pgpuobj, 0x00, object->oclass); nv04_gr_object_bind()
1052 nvkm_mo32(*pgpuobj, 0x00, 0x00080000, 0x00080000); nv04_gr_object_bind()
1054 nvkm_wo32(*pgpuobj, 0x04, 0x00000000); nv04_gr_object_bind()
1055 nvkm_wo32(*pgpuobj, 0x08, 0x00000000); nv04_gr_object_bind()
1056 nvkm_wo32(*pgpuobj, 0x0c, 0x00000000); nv04_gr_object_bind()
1057 nvkm_done(*pgpuobj); nv04_gr_object_bind()
1043 nv04_gr_object_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, int align, struct nvkm_gpuobj **pgpuobj) nv04_gr_object_bind() argument
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/
H A Dxtensa.c45 int align, struct nvkm_gpuobj **pgpuobj) nvkm_xtensa_cclass_bind()
48 true, parent, pgpuobj); nvkm_xtensa_cclass_bind()
44 nvkm_xtensa_cclass_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, int align, struct nvkm_gpuobj **pgpuobj) nvkm_xtensa_cclass_bind() argument
H A Dfalcon.c46 int align, struct nvkm_gpuobj **pgpuobj) nvkm_falcon_cclass_bind()
49 align, true, parent, pgpuobj); nvkm_falcon_cclass_bind()
45 nvkm_falcon_cclass_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent, int align, struct nvkm_gpuobj **pgpuobj) nvkm_falcon_cclass_bind() argument

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