Searched refs:only (Results 1 - 200 of 12516) sorted by relevance

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/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/
H A Dexynos4.h32 #define CLK_MOUT_MPLL_USER_T 17 /* Exynos4x12 only */
33 #define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */
57 #define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */
66 #define CLK_SCLK_SATA 150 /* Exynos4210 only */
79 #define CLK_SCLK_FIMD1 163 /* Exynos4210 only */
80 #define CLK_SCLK_MIPI1 164 /* Exynos4210 only */
85 #define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */
89 #define CLK_SCLK_PWM_ISP 173 /* Exynos4x12 only */
90 #define CLK_SCLK_SPI0_ISP 174 /* Exynos4x12 only */
91 #define CLK_SCLK_SPI1_ISP 175 /* Exynos4x12 only */
92 #define CLK_SCLK_UART_ISP 176 /* Exynos4x12 only */
110 #define CLK_TVENC 270 /* Exynos4210 only */
125 #define CLK_MDNIE0 285 /* Exynos4412 only */
128 #define CLK_FIMD1 288 /* Exynos4210 only */
129 #define CLK_MIE1 289 /* Exynos4210 only */
130 #define CLK_DSIM1 290 /* Exynos4210 only */
131 #define CLK_SMMU_FIMD1 291 /* Exynos4210 only */
135 #define CLK_SATA_PHY 295 /* Exynos4210 only */
142 #define CLK_SATA 302 /* Exynos4210 only */
189 #define CLK_MIPI_HSI 349 /* Exynos4210 only */
192 #define CLK_FIMC_LITE0 353 /* Exynos4x12 only */
193 #define CLK_FIMC_LITE1 354 /* Exynos4x12 only */
194 #define CLK_PPMUISPX 355 /* Exynos4x12 only */
195 #define CLK_PPMUISPMX 356 /* Exynos4x12 only */
196 #define CLK_FIMC_ISP 357 /* Exynos4x12 only */
197 #define CLK_FIMC_DRC 358 /* Exynos4x12 only */
198 #define CLK_FIMC_FD 359 /* Exynos4x12 only */
199 #define CLK_MCUISP 360 /* Exynos4x12 only */
200 #define CLK_GICISP 361 /* Exynos4x12 only */
201 #define CLK_SMMU_ISP 362 /* Exynos4x12 only */
202 #define CLK_SMMU_DRC 363 /* Exynos4x12 only */
203 #define CLK_SMMU_FD 364 /* Exynos4x12 only */
204 #define CLK_SMMU_LITE0 365 /* Exynos4x12 only */
205 #define CLK_SMMU_LITE1 366 /* Exynos4x12 only */
206 #define CLK_MCUCTL_ISP 367 /* Exynos4x12 only */
207 #define CLK_MPWM_ISP 368 /* Exynos4x12 only */
208 #define CLK_I2C0_ISP 369 /* Exynos4x12 only */
209 #define CLK_I2C1_ISP 370 /* Exynos4x12 only */
210 #define CLK_MTCADC_ISP 371 /* Exynos4x12 only */
211 #define CLK_PWM_ISP 372 /* Exynos4x12 only */
212 #define CLK_WDT_ISP 373 /* Exynos4x12 only */
213 #define CLK_UART_ISP 374 /* Exynos4x12 only */
214 #define CLK_ASYNCAXIM 375 /* Exynos4x12 only */
215 #define CLK_SMMU_ISPCX 376 /* Exynos4x12 only */
216 #define CLK_SPI0_ISP 377 /* Exynos4x12 only */
217 #define CLK_SPI1_ISP 378 /* Exynos4x12 only */
218 #define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */
219 #define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */
220 #define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */
221 #define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */
236 #define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */
250 #define CLK_PPMULCD1 409 /* Exynos4210 only */
259 #define CLK_DIV_ISP0 450 /* Exynos4x12 only */
260 #define CLK_DIV_ISP1 451 /* Exynos4x12 only */
261 #define CLK_DIV_MCUISP0 452 /* Exynos4x12 only */
262 #define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */
263 #define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
264 #define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
267 #define CLK_DIV_C2C 458 /* Exynos4x12 only */
/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/
H A Dexynos4.h32 #define CLK_MOUT_MPLL_USER_T 17 /* Exynos4x12 only */
33 #define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */
57 #define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */
66 #define CLK_SCLK_SATA 150 /* Exynos4210 only */
79 #define CLK_SCLK_FIMD1 163 /* Exynos4210 only */
80 #define CLK_SCLK_MIPI1 164 /* Exynos4210 only */
85 #define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */
89 #define CLK_SCLK_PWM_ISP 173 /* Exynos4x12 only */
90 #define CLK_SCLK_SPI0_ISP 174 /* Exynos4x12 only */
91 #define CLK_SCLK_SPI1_ISP 175 /* Exynos4x12 only */
92 #define CLK_SCLK_UART_ISP 176 /* Exynos4x12 only */
110 #define CLK_TVENC 270 /* Exynos4210 only */
125 #define CLK_MDNIE0 285 /* Exynos4412 only */
128 #define CLK_FIMD1 288 /* Exynos4210 only */
129 #define CLK_MIE1 289 /* Exynos4210 only */
130 #define CLK_DSIM1 290 /* Exynos4210 only */
131 #define CLK_SMMU_FIMD1 291 /* Exynos4210 only */
135 #define CLK_SATA_PHY 295 /* Exynos4210 only */
142 #define CLK_SATA 302 /* Exynos4210 only */
189 #define CLK_MIPI_HSI 349 /* Exynos4210 only */
192 #define CLK_FIMC_LITE0 353 /* Exynos4x12 only */
193 #define CLK_FIMC_LITE1 354 /* Exynos4x12 only */
194 #define CLK_PPMUISPX 355 /* Exynos4x12 only */
195 #define CLK_PPMUISPMX 356 /* Exynos4x12 only */
196 #define CLK_FIMC_ISP 357 /* Exynos4x12 only */
197 #define CLK_FIMC_DRC 358 /* Exynos4x12 only */
198 #define CLK_FIMC_FD 359 /* Exynos4x12 only */
199 #define CLK_MCUISP 360 /* Exynos4x12 only */
200 #define CLK_GICISP 361 /* Exynos4x12 only */
201 #define CLK_SMMU_ISP 362 /* Exynos4x12 only */
202 #define CLK_SMMU_DRC 363 /* Exynos4x12 only */
203 #define CLK_SMMU_FD 364 /* Exynos4x12 only */
204 #define CLK_SMMU_LITE0 365 /* Exynos4x12 only */
205 #define CLK_SMMU_LITE1 366 /* Exynos4x12 only */
206 #define CLK_MCUCTL_ISP 367 /* Exynos4x12 only */
207 #define CLK_MPWM_ISP 368 /* Exynos4x12 only */
208 #define CLK_I2C0_ISP 369 /* Exynos4x12 only */
209 #define CLK_I2C1_ISP 370 /* Exynos4x12 only */
210 #define CLK_MTCADC_ISP 371 /* Exynos4x12 only */
211 #define CLK_PWM_ISP 372 /* Exynos4x12 only */
212 #define CLK_WDT_ISP 373 /* Exynos4x12 only */
213 #define CLK_UART_ISP 374 /* Exynos4x12 only */
214 #define CLK_ASYNCAXIM 375 /* Exynos4x12 only */
215 #define CLK_SMMU_ISPCX 376 /* Exynos4x12 only */
216 #define CLK_SPI0_ISP 377 /* Exynos4x12 only */
217 #define CLK_SPI1_ISP 378 /* Exynos4x12 only */
218 #define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */
219 #define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */
220 #define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */
221 #define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */
236 #define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */
250 #define CLK_PPMULCD1 409 /* Exynos4210 only */
259 #define CLK_DIV_ISP0 450 /* Exynos4x12 only */
260 #define CLK_DIV_ISP1 451 /* Exynos4x12 only */
261 #define CLK_DIV_MCUISP0 452 /* Exynos4x12 only */
262 #define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */
263 #define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
264 #define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
267 #define CLK_DIV_C2C 458 /* Exynos4x12 only */
/linux-4.4.14/include/dt-bindings/clock/
H A Dexynos4.h32 #define CLK_MOUT_MPLL_USER_T 17 /* Exynos4x12 only */
33 #define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */
57 #define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */
66 #define CLK_SCLK_SATA 150 /* Exynos4210 only */
79 #define CLK_SCLK_FIMD1 163 /* Exynos4210 only */
80 #define CLK_SCLK_MIPI1 164 /* Exynos4210 only */
85 #define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */
89 #define CLK_SCLK_PWM_ISP 173 /* Exynos4x12 only */
90 #define CLK_SCLK_SPI0_ISP 174 /* Exynos4x12 only */
91 #define CLK_SCLK_SPI1_ISP 175 /* Exynos4x12 only */
92 #define CLK_SCLK_UART_ISP 176 /* Exynos4x12 only */
110 #define CLK_TVENC 270 /* Exynos4210 only */
125 #define CLK_MDNIE0 285 /* Exynos4412 only */
128 #define CLK_FIMD1 288 /* Exynos4210 only */
129 #define CLK_MIE1 289 /* Exynos4210 only */
130 #define CLK_DSIM1 290 /* Exynos4210 only */
131 #define CLK_SMMU_FIMD1 291 /* Exynos4210 only */
135 #define CLK_SATA_PHY 295 /* Exynos4210 only */
142 #define CLK_SATA 302 /* Exynos4210 only */
189 #define CLK_MIPI_HSI 349 /* Exynos4210 only */
192 #define CLK_FIMC_LITE0 353 /* Exynos4x12 only */
193 #define CLK_FIMC_LITE1 354 /* Exynos4x12 only */
194 #define CLK_PPMUISPX 355 /* Exynos4x12 only */
195 #define CLK_PPMUISPMX 356 /* Exynos4x12 only */
196 #define CLK_FIMC_ISP 357 /* Exynos4x12 only */
197 #define CLK_FIMC_DRC 358 /* Exynos4x12 only */
198 #define CLK_FIMC_FD 359 /* Exynos4x12 only */
199 #define CLK_MCUISP 360 /* Exynos4x12 only */
200 #define CLK_GICISP 361 /* Exynos4x12 only */
201 #define CLK_SMMU_ISP 362 /* Exynos4x12 only */
202 #define CLK_SMMU_DRC 363 /* Exynos4x12 only */
203 #define CLK_SMMU_FD 364 /* Exynos4x12 only */
204 #define CLK_SMMU_LITE0 365 /* Exynos4x12 only */
205 #define CLK_SMMU_LITE1 366 /* Exynos4x12 only */
206 #define CLK_MCUCTL_ISP 367 /* Exynos4x12 only */
207 #define CLK_MPWM_ISP 368 /* Exynos4x12 only */
208 #define CLK_I2C0_ISP 369 /* Exynos4x12 only */
209 #define CLK_I2C1_ISP 370 /* Exynos4x12 only */
210 #define CLK_MTCADC_ISP 371 /* Exynos4x12 only */
211 #define CLK_PWM_ISP 372 /* Exynos4x12 only */
212 #define CLK_WDT_ISP 373 /* Exynos4x12 only */
213 #define CLK_UART_ISP 374 /* Exynos4x12 only */
214 #define CLK_ASYNCAXIM 375 /* Exynos4x12 only */
215 #define CLK_SMMU_ISPCX 376 /* Exynos4x12 only */
216 #define CLK_SPI0_ISP 377 /* Exynos4x12 only */
217 #define CLK_SPI1_ISP 378 /* Exynos4x12 only */
218 #define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */
219 #define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */
220 #define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */
221 #define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */
236 #define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */
250 #define CLK_PPMULCD1 409 /* Exynos4210 only */
259 #define CLK_DIV_ISP0 450 /* Exynos4x12 only */
260 #define CLK_DIV_ISP1 451 /* Exynos4x12 only */
261 #define CLK_DIV_MCUISP0 452 /* Exynos4x12 only */
262 #define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */
263 #define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
264 #define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
267 #define CLK_DIV_C2C 458 /* Exynos4x12 only */
/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/
H A Dexynos4.h32 #define CLK_MOUT_MPLL_USER_T 17 /* Exynos4x12 only */
33 #define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */
57 #define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */
66 #define CLK_SCLK_SATA 150 /* Exynos4210 only */
79 #define CLK_SCLK_FIMD1 163 /* Exynos4210 only */
80 #define CLK_SCLK_MIPI1 164 /* Exynos4210 only */
85 #define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */
89 #define CLK_SCLK_PWM_ISP 173 /* Exynos4x12 only */
90 #define CLK_SCLK_SPI0_ISP 174 /* Exynos4x12 only */
91 #define CLK_SCLK_SPI1_ISP 175 /* Exynos4x12 only */
92 #define CLK_SCLK_UART_ISP 176 /* Exynos4x12 only */
110 #define CLK_TVENC 270 /* Exynos4210 only */
125 #define CLK_MDNIE0 285 /* Exynos4412 only */
128 #define CLK_FIMD1 288 /* Exynos4210 only */
129 #define CLK_MIE1 289 /* Exynos4210 only */
130 #define CLK_DSIM1 290 /* Exynos4210 only */
131 #define CLK_SMMU_FIMD1 291 /* Exynos4210 only */
135 #define CLK_SATA_PHY 295 /* Exynos4210 only */
142 #define CLK_SATA 302 /* Exynos4210 only */
189 #define CLK_MIPI_HSI 349 /* Exynos4210 only */
192 #define CLK_FIMC_LITE0 353 /* Exynos4x12 only */
193 #define CLK_FIMC_LITE1 354 /* Exynos4x12 only */
194 #define CLK_PPMUISPX 355 /* Exynos4x12 only */
195 #define CLK_PPMUISPMX 356 /* Exynos4x12 only */
196 #define CLK_FIMC_ISP 357 /* Exynos4x12 only */
197 #define CLK_FIMC_DRC 358 /* Exynos4x12 only */
198 #define CLK_FIMC_FD 359 /* Exynos4x12 only */
199 #define CLK_MCUISP 360 /* Exynos4x12 only */
200 #define CLK_GICISP 361 /* Exynos4x12 only */
201 #define CLK_SMMU_ISP 362 /* Exynos4x12 only */
202 #define CLK_SMMU_DRC 363 /* Exynos4x12 only */
203 #define CLK_SMMU_FD 364 /* Exynos4x12 only */
204 #define CLK_SMMU_LITE0 365 /* Exynos4x12 only */
205 #define CLK_SMMU_LITE1 366 /* Exynos4x12 only */
206 #define CLK_MCUCTL_ISP 367 /* Exynos4x12 only */
207 #define CLK_MPWM_ISP 368 /* Exynos4x12 only */
208 #define CLK_I2C0_ISP 369 /* Exynos4x12 only */
209 #define CLK_I2C1_ISP 370 /* Exynos4x12 only */
210 #define CLK_MTCADC_ISP 371 /* Exynos4x12 only */
211 #define CLK_PWM_ISP 372 /* Exynos4x12 only */
212 #define CLK_WDT_ISP 373 /* Exynos4x12 only */
213 #define CLK_UART_ISP 374 /* Exynos4x12 only */
214 #define CLK_ASYNCAXIM 375 /* Exynos4x12 only */
215 #define CLK_SMMU_ISPCX 376 /* Exynos4x12 only */
216 #define CLK_SPI0_ISP 377 /* Exynos4x12 only */
217 #define CLK_SPI1_ISP 378 /* Exynos4x12 only */
218 #define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */
219 #define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */
220 #define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */
221 #define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */
236 #define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */
250 #define CLK_PPMULCD1 409 /* Exynos4210 only */
259 #define CLK_DIV_ISP0 450 /* Exynos4x12 only */
260 #define CLK_DIV_ISP1 451 /* Exynos4x12 only */
261 #define CLK_DIV_MCUISP0 452 /* Exynos4x12 only */
262 #define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */
263 #define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
264 #define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
267 #define CLK_DIV_C2C 458 /* Exynos4x12 only */
/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/
H A Dexynos4.h32 #define CLK_MOUT_MPLL_USER_T 17 /* Exynos4x12 only */
33 #define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */
57 #define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */
66 #define CLK_SCLK_SATA 150 /* Exynos4210 only */
79 #define CLK_SCLK_FIMD1 163 /* Exynos4210 only */
80 #define CLK_SCLK_MIPI1 164 /* Exynos4210 only */
85 #define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */
89 #define CLK_SCLK_PWM_ISP 173 /* Exynos4x12 only */
90 #define CLK_SCLK_SPI0_ISP 174 /* Exynos4x12 only */
91 #define CLK_SCLK_SPI1_ISP 175 /* Exynos4x12 only */
92 #define CLK_SCLK_UART_ISP 176 /* Exynos4x12 only */
110 #define CLK_TVENC 270 /* Exynos4210 only */
125 #define CLK_MDNIE0 285 /* Exynos4412 only */
128 #define CLK_FIMD1 288 /* Exynos4210 only */
129 #define CLK_MIE1 289 /* Exynos4210 only */
130 #define CLK_DSIM1 290 /* Exynos4210 only */
131 #define CLK_SMMU_FIMD1 291 /* Exynos4210 only */
135 #define CLK_SATA_PHY 295 /* Exynos4210 only */
142 #define CLK_SATA 302 /* Exynos4210 only */
189 #define CLK_MIPI_HSI 349 /* Exynos4210 only */
192 #define CLK_FIMC_LITE0 353 /* Exynos4x12 only */
193 #define CLK_FIMC_LITE1 354 /* Exynos4x12 only */
194 #define CLK_PPMUISPX 355 /* Exynos4x12 only */
195 #define CLK_PPMUISPMX 356 /* Exynos4x12 only */
196 #define CLK_FIMC_ISP 357 /* Exynos4x12 only */
197 #define CLK_FIMC_DRC 358 /* Exynos4x12 only */
198 #define CLK_FIMC_FD 359 /* Exynos4x12 only */
199 #define CLK_MCUISP 360 /* Exynos4x12 only */
200 #define CLK_GICISP 361 /* Exynos4x12 only */
201 #define CLK_SMMU_ISP 362 /* Exynos4x12 only */
202 #define CLK_SMMU_DRC 363 /* Exynos4x12 only */
203 #define CLK_SMMU_FD 364 /* Exynos4x12 only */
204 #define CLK_SMMU_LITE0 365 /* Exynos4x12 only */
205 #define CLK_SMMU_LITE1 366 /* Exynos4x12 only */
206 #define CLK_MCUCTL_ISP 367 /* Exynos4x12 only */
207 #define CLK_MPWM_ISP 368 /* Exynos4x12 only */
208 #define CLK_I2C0_ISP 369 /* Exynos4x12 only */
209 #define CLK_I2C1_ISP 370 /* Exynos4x12 only */
210 #define CLK_MTCADC_ISP 371 /* Exynos4x12 only */
211 #define CLK_PWM_ISP 372 /* Exynos4x12 only */
212 #define CLK_WDT_ISP 373 /* Exynos4x12 only */
213 #define CLK_UART_ISP 374 /* Exynos4x12 only */
214 #define CLK_ASYNCAXIM 375 /* Exynos4x12 only */
215 #define CLK_SMMU_ISPCX 376 /* Exynos4x12 only */
216 #define CLK_SPI0_ISP 377 /* Exynos4x12 only */
217 #define CLK_SPI1_ISP 378 /* Exynos4x12 only */
218 #define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */
219 #define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */
220 #define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */
221 #define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */
236 #define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */
250 #define CLK_PPMULCD1 409 /* Exynos4210 only */
259 #define CLK_DIV_ISP0 450 /* Exynos4x12 only */
260 #define CLK_DIV_ISP1 451 /* Exynos4x12 only */
261 #define CLK_DIV_MCUISP0 452 /* Exynos4x12 only */
262 #define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */
263 #define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
264 #define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
267 #define CLK_DIV_C2C 458 /* Exynos4x12 only */
/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/
H A Dexynos4.h32 #define CLK_MOUT_MPLL_USER_T 17 /* Exynos4x12 only */
33 #define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */
57 #define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */
66 #define CLK_SCLK_SATA 150 /* Exynos4210 only */
79 #define CLK_SCLK_FIMD1 163 /* Exynos4210 only */
80 #define CLK_SCLK_MIPI1 164 /* Exynos4210 only */
85 #define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */
89 #define CLK_SCLK_PWM_ISP 173 /* Exynos4x12 only */
90 #define CLK_SCLK_SPI0_ISP 174 /* Exynos4x12 only */
91 #define CLK_SCLK_SPI1_ISP 175 /* Exynos4x12 only */
92 #define CLK_SCLK_UART_ISP 176 /* Exynos4x12 only */
110 #define CLK_TVENC 270 /* Exynos4210 only */
125 #define CLK_MDNIE0 285 /* Exynos4412 only */
128 #define CLK_FIMD1 288 /* Exynos4210 only */
129 #define CLK_MIE1 289 /* Exynos4210 only */
130 #define CLK_DSIM1 290 /* Exynos4210 only */
131 #define CLK_SMMU_FIMD1 291 /* Exynos4210 only */
135 #define CLK_SATA_PHY 295 /* Exynos4210 only */
142 #define CLK_SATA 302 /* Exynos4210 only */
189 #define CLK_MIPI_HSI 349 /* Exynos4210 only */
192 #define CLK_FIMC_LITE0 353 /* Exynos4x12 only */
193 #define CLK_FIMC_LITE1 354 /* Exynos4x12 only */
194 #define CLK_PPMUISPX 355 /* Exynos4x12 only */
195 #define CLK_PPMUISPMX 356 /* Exynos4x12 only */
196 #define CLK_FIMC_ISP 357 /* Exynos4x12 only */
197 #define CLK_FIMC_DRC 358 /* Exynos4x12 only */
198 #define CLK_FIMC_FD 359 /* Exynos4x12 only */
199 #define CLK_MCUISP 360 /* Exynos4x12 only */
200 #define CLK_GICISP 361 /* Exynos4x12 only */
201 #define CLK_SMMU_ISP 362 /* Exynos4x12 only */
202 #define CLK_SMMU_DRC 363 /* Exynos4x12 only */
203 #define CLK_SMMU_FD 364 /* Exynos4x12 only */
204 #define CLK_SMMU_LITE0 365 /* Exynos4x12 only */
205 #define CLK_SMMU_LITE1 366 /* Exynos4x12 only */
206 #define CLK_MCUCTL_ISP 367 /* Exynos4x12 only */
207 #define CLK_MPWM_ISP 368 /* Exynos4x12 only */
208 #define CLK_I2C0_ISP 369 /* Exynos4x12 only */
209 #define CLK_I2C1_ISP 370 /* Exynos4x12 only */
210 #define CLK_MTCADC_ISP 371 /* Exynos4x12 only */
211 #define CLK_PWM_ISP 372 /* Exynos4x12 only */
212 #define CLK_WDT_ISP 373 /* Exynos4x12 only */
213 #define CLK_UART_ISP 374 /* Exynos4x12 only */
214 #define CLK_ASYNCAXIM 375 /* Exynos4x12 only */
215 #define CLK_SMMU_ISPCX 376 /* Exynos4x12 only */
216 #define CLK_SPI0_ISP 377 /* Exynos4x12 only */
217 #define CLK_SPI1_ISP 378 /* Exynos4x12 only */
218 #define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */
219 #define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */
220 #define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */
221 #define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */
236 #define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */
250 #define CLK_PPMULCD1 409 /* Exynos4210 only */
259 #define CLK_DIV_ISP0 450 /* Exynos4x12 only */
260 #define CLK_DIV_ISP1 451 /* Exynos4x12 only */
261 #define CLK_DIV_MCUISP0 452 /* Exynos4x12 only */
262 #define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */
263 #define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
264 #define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
267 #define CLK_DIV_C2C 458 /* Exynos4x12 only */
/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/
H A Dexynos4.h32 #define CLK_MOUT_MPLL_USER_T 17 /* Exynos4x12 only */
33 #define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */
57 #define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */
66 #define CLK_SCLK_SATA 150 /* Exynos4210 only */
79 #define CLK_SCLK_FIMD1 163 /* Exynos4210 only */
80 #define CLK_SCLK_MIPI1 164 /* Exynos4210 only */
85 #define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */
89 #define CLK_SCLK_PWM_ISP 173 /* Exynos4x12 only */
90 #define CLK_SCLK_SPI0_ISP 174 /* Exynos4x12 only */
91 #define CLK_SCLK_SPI1_ISP 175 /* Exynos4x12 only */
92 #define CLK_SCLK_UART_ISP 176 /* Exynos4x12 only */
110 #define CLK_TVENC 270 /* Exynos4210 only */
125 #define CLK_MDNIE0 285 /* Exynos4412 only */
128 #define CLK_FIMD1 288 /* Exynos4210 only */
129 #define CLK_MIE1 289 /* Exynos4210 only */
130 #define CLK_DSIM1 290 /* Exynos4210 only */
131 #define CLK_SMMU_FIMD1 291 /* Exynos4210 only */
135 #define CLK_SATA_PHY 295 /* Exynos4210 only */
142 #define CLK_SATA 302 /* Exynos4210 only */
189 #define CLK_MIPI_HSI 349 /* Exynos4210 only */
192 #define CLK_FIMC_LITE0 353 /* Exynos4x12 only */
193 #define CLK_FIMC_LITE1 354 /* Exynos4x12 only */
194 #define CLK_PPMUISPX 355 /* Exynos4x12 only */
195 #define CLK_PPMUISPMX 356 /* Exynos4x12 only */
196 #define CLK_FIMC_ISP 357 /* Exynos4x12 only */
197 #define CLK_FIMC_DRC 358 /* Exynos4x12 only */
198 #define CLK_FIMC_FD 359 /* Exynos4x12 only */
199 #define CLK_MCUISP 360 /* Exynos4x12 only */
200 #define CLK_GICISP 361 /* Exynos4x12 only */
201 #define CLK_SMMU_ISP 362 /* Exynos4x12 only */
202 #define CLK_SMMU_DRC 363 /* Exynos4x12 only */
203 #define CLK_SMMU_FD 364 /* Exynos4x12 only */
204 #define CLK_SMMU_LITE0 365 /* Exynos4x12 only */
205 #define CLK_SMMU_LITE1 366 /* Exynos4x12 only */
206 #define CLK_MCUCTL_ISP 367 /* Exynos4x12 only */
207 #define CLK_MPWM_ISP 368 /* Exynos4x12 only */
208 #define CLK_I2C0_ISP 369 /* Exynos4x12 only */
209 #define CLK_I2C1_ISP 370 /* Exynos4x12 only */
210 #define CLK_MTCADC_ISP 371 /* Exynos4x12 only */
211 #define CLK_PWM_ISP 372 /* Exynos4x12 only */
212 #define CLK_WDT_ISP 373 /* Exynos4x12 only */
213 #define CLK_UART_ISP 374 /* Exynos4x12 only */
214 #define CLK_ASYNCAXIM 375 /* Exynos4x12 only */
215 #define CLK_SMMU_ISPCX 376 /* Exynos4x12 only */
216 #define CLK_SPI0_ISP 377 /* Exynos4x12 only */
217 #define CLK_SPI1_ISP 378 /* Exynos4x12 only */
218 #define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */
219 #define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */
220 #define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */
221 #define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */
236 #define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */
250 #define CLK_PPMULCD1 409 /* Exynos4210 only */
259 #define CLK_DIV_ISP0 450 /* Exynos4x12 only */
260 #define CLK_DIV_ISP1 451 /* Exynos4x12 only */
261 #define CLK_DIV_MCUISP0 452 /* Exynos4x12 only */
262 #define CLK_DIV_MCUISP1 453 /* Exynos4x12 only */
263 #define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
264 #define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
267 #define CLK_DIV_C2C 458 /* Exynos4x12 only */
/linux-4.4.14/include/linux/
H A Dfanotify.h6 /* not valid from userspace, only kernel internal */
H A Dstring_helpers.h51 unsigned int flags, const char *only);
54 char *dst, size_t osz, const char *only) string_escape_mem_any_np()
56 return string_escape_mem(src, isz, dst, osz, ESCAPE_ANY_NP, only); string_escape_mem_any_np()
60 unsigned int flags, const char *only) string_escape_str()
62 return string_escape_mem(src, strlen(src), dst, sz, flags, only); string_escape_str()
66 size_t sz, const char *only) string_escape_str_any_np()
68 return string_escape_str(src, dst, sz, ESCAPE_ANY_NP, only); string_escape_str_any_np()
53 string_escape_mem_any_np(const char *src, size_t isz, char *dst, size_t osz, const char *only) string_escape_mem_any_np() argument
59 string_escape_str(const char *src, char *dst, size_t sz, unsigned int flags, const char *only) string_escape_str() argument
65 string_escape_str_any_np(const char *src, char *dst, size_t sz, const char *only) string_escape_str_any_np() argument
H A Dcoredump.h10 * These are the only things you should do on a core-file: use only these
H A Dzsmalloc.h22 * NOTE: These only make a difference when a mapped object spans pages.
27 ZS_MM_RO, /* read-only (no copy-out at unmap time) */
28 ZS_MM_WO /* write-only (no copy-in at map time) */
30 * NOTE: ZS_MM_WO should only be used for initializing new
H A Defi-bgrt.h10 /* The BGRT data itself; only valid if bgrt_image != NULL. */
H A Ddrbd.h155 ERR_INTEGRITY_ALG = 141, /* DRBD 8.2 only */
156 ERR_INTEGRITY_ALG_ND = 142, /* DRBD 8.2 only */
157 ERR_CPU_MASK_PARSE = 143, /* DRBD 8.2 only */
158 ERR_CSUMS_ALG = 144, /* DRBD 8.2 only */
159 ERR_CSUMS_ALG_ND = 145, /* DRBD 8.2 only */
160 ERR_VERIFY_ALG = 146, /* DRBD 8.2 only */
161 ERR_VERIFY_ALG_ND = 147, /* DRBD 8.2 only */
162 ERR_CSUMS_RESYNC_RUNNING= 148, /* DRBD 8.2 only */
163 ERR_VERIFY_RUNNING = 149, /* DRBD 8.2 only */
165 ERR_CONNECTED = 151, /* DRBD 8.3 only */
319 SS_NO_VERIFY_ALG = -14, /* drbd-8.2 only */
320 SS_NEED_CONNECTION = -15, /* drbd-8.2 only */
322 SS_NOT_SUPPORTED = -17, /* drbd-8.2 only */
H A Dsony-laptop.h8 /* used only for communication between v4l and sony-laptop */
/linux-4.4.14/arch/frv/include/uapi/asm/
H A Dioctls.h4 #define TIOCTTYGSTRUCT 0x5426 /* For debugging only */
/linux-4.4.14/arch/arm/mach-ux500/
H A Dste-dma40-db8500.h31 DB8500_DMA_DEV10_MCDE_RX = 10, /* RX only */
72 DB8500_DMA_DEV49_CAC1_TX_HAC1_TX = 49, /* TX only */
73 DB8500_DMA_DEV50_HAC1_TX = 50, /* TX only */
74 DB8500_DMA_MEMCPY_TX_0 = 51, /* TX only */
79 /* 56 -> 60 are channels reserved for memcpy only */
81 DB8500_DMA_DEV62_CAC0_TX_HAC0_TX = 62, /* TX only */
82 DB8500_DMA_DEV63_HAC0_TX = 63, /* TX only */
/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/mfd/
H A Ddbx500-prcmu.h15 #define PRCMU_SDMMCHCLK 2 /* DBx540 only. */
17 #define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */
25 #define PRCMU_CAMCLK 10 /* DBx540 only. */
49 #define PRCMU_G1CLK 34 /* DBx540 only. */
50 #define PRCMU_HVACLK 35 /* DBx540 only. */
73 /* LCD DSI PLL - Ux540 only */
/linux-4.4.14/include/dt-bindings/mfd/
H A Ddbx500-prcmu.h15 #define PRCMU_SDMMCHCLK 2 /* DBx540 only. */
17 #define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */
25 #define PRCMU_CAMCLK 10 /* DBx540 only. */
49 #define PRCMU_G1CLK 34 /* DBx540 only. */
50 #define PRCMU_HVACLK 35 /* DBx540 only. */
73 /* LCD DSI PLL - Ux540 only */
/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/mfd/
H A Ddbx500-prcmu.h15 #define PRCMU_SDMMCHCLK 2 /* DBx540 only. */
17 #define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */
25 #define PRCMU_CAMCLK 10 /* DBx540 only. */
49 #define PRCMU_G1CLK 34 /* DBx540 only. */
50 #define PRCMU_HVACLK 35 /* DBx540 only. */
73 /* LCD DSI PLL - Ux540 only */
/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/mfd/
H A Ddbx500-prcmu.h15 #define PRCMU_SDMMCHCLK 2 /* DBx540 only. */
17 #define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */
25 #define PRCMU_CAMCLK 10 /* DBx540 only. */
49 #define PRCMU_G1CLK 34 /* DBx540 only. */
50 #define PRCMU_HVACLK 35 /* DBx540 only. */
73 /* LCD DSI PLL - Ux540 only */
/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/mfd/
H A Ddbx500-prcmu.h15 #define PRCMU_SDMMCHCLK 2 /* DBx540 only. */
17 #define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */
25 #define PRCMU_CAMCLK 10 /* DBx540 only. */
49 #define PRCMU_G1CLK 34 /* DBx540 only. */
50 #define PRCMU_HVACLK 35 /* DBx540 only. */
73 /* LCD DSI PLL - Ux540 only */
/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/mfd/
H A Ddbx500-prcmu.h15 #define PRCMU_SDMMCHCLK 2 /* DBx540 only. */
17 #define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */
25 #define PRCMU_CAMCLK 10 /* DBx540 only. */
49 #define PRCMU_G1CLK 34 /* DBx540 only. */
50 #define PRCMU_HVACLK 35 /* DBx540 only. */
73 /* LCD DSI PLL - Ux540 only */
/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/mfd/
H A Ddbx500-prcmu.h15 #define PRCMU_SDMMCHCLK 2 /* DBx540 only. */
17 #define PRCMU_SIAMMDSPCLK 3 /* DBx540 only. */
25 #define PRCMU_CAMCLK 10 /* DBx540 only. */
49 #define PRCMU_G1CLK 34 /* DBx540 only. */
50 #define PRCMU_HVACLK 35 /* DBx540 only. */
73 /* LCD DSI PLL - Ux540 only */
/linux-4.4.14/drivers/atm/
H A Dtonga.h14 #define SEPROM_MAGIC 0x0c /* obscure required pattern (ASIC only) */
15 #define SEPROM_DATA 0x02 /* serial EEPROM data (ASIC only) */
16 #define SEPROM_CLK 0x01 /* serial EEPROM clock (ASIC only) */
/linux-4.4.14/arch/x86/include/uapi/asm/
H A Dmman.h4 #define MAP_32BIT 0x40 /* only give out 32bit addresses */
H A Dposix_types_x32.h5 * This file is only used by user-level software, so you need to
/linux-4.4.14/arch/blackfin/mm/
H A Dblackfin_sram.h2 * Local prototypes meant for internal use only
/linux-4.4.14/include/asm-generic/
H A Duser.h4 * This file may define a 'struct user' structure. However, it is only
H A Dparport.h9 * Without ISA support, the driver will only attach
H A Dsyscall.h15 * and only when the caller is sure that the task of interest
39 * It's only valid to call this when @task is known to be blocked.
48 * It's only valid to call this when @task is stopped for system
68 * It's only valid to call this when @task is stopped for tracing on exit
81 * It's only valid to call this when @task is stopped for tracing on exit
98 * It's only valid to call this when @task is stopped for tracing on exit
116 * It's only valid to call this when @task is stopped for tracing on
118 * It's invalid to call this with @i + @n > 6; we only support system calls
136 * It's only valid to call this when @task is stopped for tracing on
138 * It's invalid to call this with @i + @n > 6; we only support system calls
150 * It's only valid to call this when current is stopped on entry to a system
/linux-4.4.14/tools/build/feature/
H A Dtest-libdw-dwarf-unwind.c9 * only compiled. main()
/linux-4.4.14/arch/arm/plat-samsung/include/plat/
H A Dregs-udc.h88 #define S3C2410_UDC_INT_EP4 (1 << 4) /* R/W (clear only) */
89 #define S3C2410_UDC_INT_EP3 (1 << 3) /* R/W (clear only) */
90 #define S3C2410_UDC_INT_EP2 (1 << 2) /* R/W (clear only) */
91 #define S3C2410_UDC_INT_EP1 (1 << 1) /* R/W (clear only) */
92 #define S3C2410_UDC_INT_EP0 (1 << 0) /* R/W (clear only) */
94 #define S3C2410_UDC_USBINT_RESET (1 << 2) /* R/W (clear only) */
95 #define S3C2410_UDC_USBINT_RESUME (1 << 1) /* R/W (clear only) */
96 #define S3C2410_UDC_USBINT_SUSPEND (1 << 0) /* R/W (clear only) */
114 #define S3C2410_UDC_ICSR1_SENTSTL (1 << 5) /* R/W (clear only) */
116 #define S3C2410_UDC_ICSR1_FFLUSH (1 << 3) /* W (set only) */
117 #define S3C2410_UDC_ICSR1_UNDRUN (1 << 2) /* R/W (clear only) */
118 #define S3C2410_UDC_ICSR1_PKTRDY (1 << 0) /* R/W (set only) */
126 #define S3C2410_UDC_OCSR1_SENTSTL (1 << 6) /* R/W (clear only) */
130 #define S3C2410_UDC_OCSR1_OVRRUN (1 << 2) /* R/W (clear only) */
131 #define S3C2410_UDC_OCSR1_PKTRDY (1 << 0) /* R/W (clear only) */
/linux-4.4.14/drivers/net/wireless/hostap/
H A Dhostap_common.h26 #define HFA384X_RID_CNFWDSADDRESS1 0xFC11 /* AP f/w only */
27 #define HFA384X_RID_CNFWDSADDRESS2 0xFC12 /* AP f/w only */
28 #define HFA384X_RID_CNFWDSADDRESS3 0xFC13 /* AP f/w only */
29 #define HFA384X_RID_CNFWDSADDRESS4 0xFC14 /* AP f/w only */
30 #define HFA384X_RID_CNFWDSADDRESS5 0xFC15 /* AP f/w only */
31 #define HFA384X_RID_CNFWDSADDRESS6 0xFC16 /* AP f/w only */
32 #define HFA384X_RID_CNFMULTICASTPMBUFFERING 0xFC17 /* AP f/w only */
43 #define HFA384X_RID_CNFMAXASSOCSTA 0xFC2B /* AP f/w only */
46 #define HFA384X_RID_CNFHOSTAUTHENTICATION 0xFC2E /* AP f/w only */
51 #define HFA384X_RID_CNFAPPCFINFO 0xFC34 /* AP f/w only */
60 * write only */
68 #define HFA384X_RID_FRAGMENTATIONTHRESHOLD0 0xFC90 /* AP f/w only */
69 #define HFA384X_RID_FRAGMENTATIONTHRESHOLD1 0xFC91 /* AP f/w only */
70 #define HFA384X_RID_FRAGMENTATIONTHRESHOLD2 0xFC92 /* AP f/w only */
71 #define HFA384X_RID_FRAGMENTATIONTHRESHOLD3 0xFC93 /* AP f/w only */
72 #define HFA384X_RID_FRAGMENTATIONTHRESHOLD4 0xFC94 /* AP f/w only */
73 #define HFA384X_RID_FRAGMENTATIONTHRESHOLD5 0xFC95 /* AP f/w only */
74 #define HFA384X_RID_FRAGMENTATIONTHRESHOLD6 0xFC96 /* AP f/w only */
75 #define HFA384X_RID_RTSTHRESHOLD0 0xFC97 /* AP f/w only */
76 #define HFA384X_RID_RTSTHRESHOLD1 0xFC98 /* AP f/w only */
77 #define HFA384X_RID_RTSTHRESHOLD2 0xFC99 /* AP f/w only */
78 #define HFA384X_RID_RTSTHRESHOLD3 0xFC9A /* AP f/w only */
79 #define HFA384X_RID_RTSTHRESHOLD4 0xFC9B /* AP f/w only */
80 #define HFA384X_RID_RTSTHRESHOLD5 0xFC9C /* AP f/w only */
81 #define HFA384X_RID_RTSTHRESHOLD6 0xFC9D /* AP f/w only */
82 #define HFA384X_RID_TXRATECONTROL0 0xFC9E /* AP f/w only */
83 #define HFA384X_RID_TXRATECONTROL1 0xFC9F /* AP f/w only */
84 #define HFA384X_RID_TXRATECONTROL2 0xFCA0 /* AP f/w only */
85 #define HFA384X_RID_TXRATECONTROL3 0xFCA1 /* AP f/w only */
86 #define HFA384X_RID_TXRATECONTROL4 0xFCA2 /* AP f/w only */
87 #define HFA384X_RID_TXRATECONTROL5 0xFCA3 /* AP f/w only */
88 #define HFA384X_RID_TXRATECONTROL6 0xFCA4 /* AP f/w only */
114 #define HFA384X_RID_AUTHENTICATESTATION 0xFCE3 /* AP f/w only */
115 #define HFA384X_RID_CHANNELINFOREQUEST 0xFCE4 /* AP f/w only */
137 * only Prism2.5(?) */
154 #define HFA384X_RID_CURRENTTXRATE1 0xFD80 /* AP f/w only */
155 #define HFA384X_RID_CURRENTTXRATE2 0xFD81 /* AP f/w only */
156 #define HFA384X_RID_CURRENTTXRATE3 0xFD82 /* AP f/w only */
157 #define HFA384X_RID_CURRENTTXRATE4 0xFD83 /* AP f/w only */
158 #define HFA384X_RID_CURRENTTXRATE5 0xFD84 /* AP f/w only */
159 #define HFA384X_RID_CURRENTTXRATE6 0xFD85 /* AP f/w only */
160 #define HFA384X_RID_OWNMACADDR 0xFD86 /* AP f/w only */
223 * root only)
/linux-4.4.14/arch/cris/boot/rescue/
H A Dhead_v32.S5 * In practice, this only works for NOR flash (or some convoluted RAM boot)
6 * and hence is not really useful for Artpec-3, so it's Etrax FS / NOR only.
/linux-4.4.14/include/linux/platform_data/
H A Dst_sensors_pdata.h17 * Available only for accelerometer and pressure sensors.
18 * Accelerometer DRDY on LSM330 available only on pin 1 (see datasheet).
H A Dgpio-ts5500.h18 * @strap: The only pin connected to an interrupt in a block is input-only.
H A Dmv_usb.h40 /* only valid for HCD. OTG or Host only*/
H A Dusb-rcar-phy.h16 bool ferrite_bead:1; /* (R8A7778 only) */
25 } ovc_pin[3]; /* (R8A7778 only has 2 ports) */
/linux-4.4.14/include/uapi/linux/
H A Drandom.h19 /* Add to (or subtract from) the entropy count. (Superuser only.) */
22 /* Get the contents of the entropy pool. (Superuser only.) */
27 * (Superuser only.)
31 /* Clear entropy count to 0. (Superuser only.) */
34 /* Clear the entropy pool and associated counters. (Superuser only.) */
H A Dgigaset_dev.h25 /* enable adapter configuration mode (M10x only) */
28 /* set break characters (M105 only) */
H A Dwait.h13 #define __WCLONE 0x80000000 /* Wait only on non-SIGCHLD children */
H A Dam437x-vpfe.h77 /* only if bClampEnable is TRUE */
79 /* only if bClampEnable is TRUE */
81 /* only if bClampEnable is TRUE */
83 /* only if bClampEnable is TRUE */
85 /* only if bClampEnable is FALSE */
H A Datmsap.h65 #define ATM_HL_HLP 0x03 /* high layer profile - UNI 3.0 only */
85 #define ATM_TT_RX 1 /* receive only */
86 #define ATM_TT_TX 2 /* send only */
126 /* only if term_type != ATM_TT_NONE */
128 /* only if term_type != ATM_TT_NONE */
133 /* (only if ipi == NLPID_IEEE802_1_SNAP) */
141 unsigned char hl_length; /* length (only if hl_type == ATM_HL_USER || */
/linux-4.4.14/arch/powerpc/include/asm/
H A Dkeylargo.h22 #define KEYLARGO_FCR5 0x4c /* Pangea only */
43 /* K2 does only extint GPIOs and does 51 of them */
54 /* Hrm... this one is only to be used on Pismo. It seems to also
141 #define KL1_USB2_PMI_ENABLE 0x00000001 /* Intrepid only */
142 #define KL1_AUDIO_SEL_22MCLK 0x00000002 /* KL/Pangea only */
143 #define KL1_USB2_REF_SUSPEND_SEL 0x00000002 /* Intrepid only */
144 #define KL1_USB2_REF_SUSPEND 0x00000004 /* Intrepid only */
145 #define KL1_AUDIO_CLK_ENABLE_BIT 0x00000008 /* KL/Pangea only */
146 #define KL1_USB2_PAD_SUSPEND_SEL 0x00000008 /* Intrepid only */
147 #define KL1_USB2_PAD_SUSPEND0 0x00000010 /* Intrepid only */
148 #define KL1_AUDIO_CLK_OUT_ENABLE 0x00000020 /* KL/Pangea only */
149 #define KL1_USB2_PAD_SUSPEND1 0x00000020 /* Intrepid only */
150 #define KL1_AUDIO_CELL_ENABLE 0x00000040 /* KL/Pangea only */
151 #define KL1_USB2_CELL_ENABLE 0x00000040 /* Intrepid only */
152 #define KL1_AUDIO_CHOOSE 0x00000080 /* KL/Pangea only */
176 #define KL3_SHUTDOWN_PLL_TOTAL 0x00000001 /* KL/Pangea only */
177 #define KL3_SHUTDOWN_PLLKW6 0x00000002 /* KL/Pangea only */
178 #define KL3_IT_SHUTDOWN_PLL3 0x00000002 /* Intrepid only */
179 #define KL3_SHUTDOWN_PLLKW4 0x00000004 /* KL/Pangea only */
180 #define KL3_IT_SHUTDOWN_PLL2 0x00000004 /* Intrepid only */
181 #define KL3_SHUTDOWN_PLLKW35 0x00000008 /* KL/Pangea only */
182 #define KL3_IT_SHUTDOWN_PLL1 0x00000008 /* Intrepid only */
184 #define KL3_IT_ENABLE_PLL3_SHUTDOWN 0x00000010 /* Intrepid only */
185 #define KL3_PLL_RESET 0x00000020 /* KL/Pangea only */
186 #define KL3_IT_ENABLE_PLL2_SHUTDOWN 0x00000020 /* Intrepid only */
187 #define KL3_IT_ENABLE_PLL1_SHUTDOWN 0x00000010 /* Intrepid only */
192 #define KL3_CLK31_ENABLE 0x00000800 /* KL/Pangea only */
196 #define KL3_VIA_CLK16_ENABLE 0x00008000 /* KL/Pangea only */
197 #define KL3_IT_VIA_CLK32_ENABLE 0x00008000 /* Intrepid only */
219 /* Pangea and Intrepid only */
H A Dpte-hash64-4k.h1 /* To be include by pgtable-hash64.h only */
H A Dpte-hash64.h10 * Note: We only support user read/write permissions. Supervisor always
14 * We could create separate kernel read-only if we used the 3 PP bits
30 /* No separate kernel read-only */
/linux-4.4.14/drivers/net/ethernet/hisilicon/hns/
H A Dhns_dsaf_mac.h221 u64 rx_good_pkts; /* only for xgmac */
223 u64 rx_total_pkts; /* only for xgmac */
224 u64 rx_total_bytes; /* only for xgmac */
225 u64 rx_bad_bytes; /* only for gmac */
229 u64 rx_fragment_err; /* only for xgmac */
230 u64 rx_undersize; /* only for xgmac */
232 u64 rx_minto64; /* only for gmac */
240 u64 rx_1519tomax_good; /* only for xgmac */
244 u64 rx_vlan_pkts; /* only for gmac */
245 u64 rx_data_err; /* only for gmac */
246 u64 rx_align_err; /* only for gmac */
247 u64 rx_long_err; /* only for gmac */
249 u64 rx_pfc_tc1; /* only for xgmac */
250 u64 rx_pfc_tc2; /* only for xgmac */
251 u64 rx_pfc_tc3; /* only for xgmac */
252 u64 rx_pfc_tc4; /* only for xgmac */
253 u64 rx_pfc_tc5; /* only for xgmac */
254 u64 rx_pfc_tc6; /* only for xgmac */
255 u64 rx_pfc_tc7; /* only for xgmac */
257 u64 rx_filter_pkts; /* only for gmac */
258 u64 rx_filter_bytes; /* only for gmac */
259 u64 rx_fifo_overrun_err;/* only for gmac */
260 u64 rx_len_err; /* only for gmac */
261 u64 rx_comma_err; /* only for gmac */
262 u64 rx_symbol_err; /* only for xgmac */
263 u64 tx_good_to_sw; /* only for xgmac */
264 u64 tx_bad_to_sw; /* only for xgmac */
265 u64 rx_1731_pkts; /* only for xgmac */
268 u64 tx_good_pkts; /* only for xgmac */
269 u64 tx_total_bytes; /* only for xgmac */
270 u64 tx_total_pkts; /* only for xgmac */
271 u64 tx_bad_bytes; /* only for gmac */
272 u64 tx_bad_pkts; /* only for xgmac */
276 u64 tx_undersize; /* only for xgmac */
277 u64 tx_fragment_err; /* only for xgmac */
278 u64 tx_under_min_pkts; /* only for gmac */
286 u64 tx_1519tomax_good; /* only for xgmac */
287 u64 tx_oversize; /* only for xgmac */
289 u64 tx_underrun_err; /* only for gmac */
290 u64 tx_vlan; /* only for gmac */
291 u64 tx_crc_err; /* only for gmac */
293 u64 tx_pfc_tc1; /* only for xgmac */
294 u64 tx_pfc_tc2; /* only for xgmac */
295 u64 tx_pfc_tc3; /* only for xgmac */
296 u64 tx_pfc_tc4; /* only for xgmac */
297 u64 tx_pfc_tc5; /* only for xgmac */
298 u64 tx_pfc_tc6; /* only for xgmac */
299 u64 tx_pfc_tc7; /* only for xgmac */
300 u64 tx_ctrl; /* only for xgmac */
301 u64 tx_1731_pkts; /* only for xgmac */
302 u64 tx_1588_pkts; /* only for xgmac */
303 u64 rx_good_from_sw; /* only for xgmac */
304 u64 rx_bad_from_sw; /* only for xgmac */
/linux-4.4.14/arch/ia64/include/uapi/asm/
H A Dia64regs.h19 #define _IA64_REG_IP 1016 /* getreg only */
77 #define _IA64_REG_CR_IVR 4161 /* getreg only */
80 #define _IA64_REG_CR_IRR0 4164 /* getreg only */
81 #define _IA64_REG_CR_IRR1 4165 /* getreg only */
82 #define _IA64_REG_CR_IRR2 4166 /* getreg only */
83 #define _IA64_REG_CR_IRR3 4167 /* getreg only */
92 #define _IA64_REG_INDR_CPUID 9000 /* getindreg only */
/linux-4.4.14/arch/alpha/include/asm/
H A Dtimex.h9 /* With only one or two oddballs, we use the RTC as the ticker, selecting
15 * Currently only used on SMP for scheduling.
18 * But this only means we'll force a reschedule every 8 seconds or so,
H A Dparport.h6 * This file should only be included by drivers/parport/parport_pc.c.
/linux-4.4.14/arch/parisc/include/uapi/asm/
H A Dfcntl.h5 #define O_BLKSEEK 000000100 /* HPUX only */
13 #define O_DSYNC 001000000 /* HPUX only */
14 #define O_RSYNC 002000000 /* HPUX only */
/linux-4.4.14/arch/x86/include/asm/
H A Dia32_unistd.h6 * this is for the kernel only.
H A Dsyscalls.h33 /* X86_32 only */
46 /* X86_64 only */
H A Dxor_64.h17 We may also be able to load into the L1 only depending on how the cpu
/linux-4.4.14/arch/alpha/include/uapi/asm/
H A Dstatfs.h6 /* Alpha is the only 64-bit platform with 32-bit statfs. And doesn't
/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/i2c/
H A Di2c.h9 * GPLv2 only
/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/thermal/
H A Dthermal.h7 * GPLv2 only
/linux-4.4.14/include/dt-bindings/i2c/
H A Di2c.h9 * GPLv2 only
/linux-4.4.14/include/dt-bindings/thermal/
H A Dthermal.h7 * GPLv2 only
/linux-4.4.14/include/uapi/linux/netfilter/
H A Dxt_bpf.h15 /* only used in the kernel */
H A Dnf_conntrack_tuple_common.h33 __be16 key; /* GRE key is 32bit, PPtP only uses 16bit */
/linux-4.4.14/include/linux/netfilter/
H A Dnf_conntrack_sane.h14 /* This structure exists only once per master */
/linux-4.4.14/arch/mips/include/asm/mach-bcm63xx/
H A Dbcm63xx_dev_usb_usbd.h8 /* board can only support full speed (USB 1.1) */
/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/i2c/
H A Di2c.h9 * GPLv2 only
/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/thermal/
H A Dthermal.h7 * GPLv2 only
/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/i2c/
H A Di2c.h9 * GPLv2 only
/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/thermal/
H A Dthermal.h7 * GPLv2 only
/linux-4.4.14/arch/parisc/include/asm/
H A Dparport.h5 * This file should only be included by drivers/parport/parport_pc.c.
H A Dpsw.h11 #define PSW_G 0x00000040 /* PA1.x only */
12 #define PSW_O 0x00000080 /* PA2.0 only */
20 #define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */
39 #define PSW_W 0x08000000 /* PA2.0 only */
40 #define PSW_W_BIT 36 /* PA2.0 only */
42 #define PSW_Z 0x40000000 /* PA1.x only */
43 #define PSW_Y 0x80000000 /* PA1.x only */
46 # define PSW_HI_CB 0x000000ff /* PA2.0 only */
H A Dperf.h36 /* Cuda only Images */
44 /* Onyx only Images */
H A Dldcw.h5 /* Because kmalloc only guarantees 8-byte alignment for kmalloc'd data,
6 and GCC only guarantees 8-byte alignment for stack locals, we can't
27 they only require "natural" alignment (4-byte for ldcw, 8-byte for
36 /* LDCW, the only atomic read-write operation PA-RISC has. *sigh*.
/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/i2c/
H A Di2c.h9 * GPLv2 only
/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/thermal/
H A Dthermal.h7 * GPLv2 only
/linux-4.4.14/arch/cris/include/uapi/asm/
H A Dioctls.h4 #define TIOCSERGSTRUCT 0x5458 /* For debugging only */
/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/i2c/
H A Di2c.h9 * GPLv2 only
/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/thermal/
H A Dthermal.h7 * GPLv2 only
/linux-4.4.14/arch/arm/mach-pxa/include/mach/
H A Dregs-uart.h10 #define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
11 #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
13 #define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
14 #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
17 #define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
18 #define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
26 #define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */
27 #define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
29 #define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */
30 #define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */
33 #define BTLSR __REG(0x40200014) /* Line Status Register (read only) */
34 #define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */
42 #define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */
43 #define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */
45 #define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */
46 #define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */
49 #define STLSR __REG(0x40700014) /* Line Status Register (read only) */
58 #define HWRBR __REG(0x41600000) /* Receive Buffer Register (read only) */
59 #define HWTHR __REG(0x41600000) /* Transmit Holding Register (write only) */
61 #define HWIIR __REG(0x41600008) /* Interrupt ID Register (read only) */
62 #define HWFCR __REG(0x41600008) /* FIFO Control Register (write only) */
65 #define HWLSR __REG(0x41600014) /* Line Status Register (read only) */
66 #define HWMSR __REG(0x41600018) /* Modem Status Register (read only) */
69 #define HWFOR __REG(0x41600024) /* Receive FIFO Occupancy Register (read only) */
71 #define HWACR __REG(0x4160002C) /* Auto-Baud Count Register (read only) */
H A Daddr-map.h35 * Dynamic Memory Controller (only on PXA3xx)
47 * DFI Bus for NAND, PXA3xx only
/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/i2c/
H A Di2c.h9 * GPLv2 only
/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/thermal/
H A Dthermal.h7 * GPLv2 only
/linux-4.4.14/arch/arm/mach-s3c24xx/
H A Dgta02.h18 #define GTA02_GPIO_AMP_SHUT S3C2410_GPJ(1) /* v2 + v3 + v4 only */
19 #define GTA02_GPIO_HP_IN S3C2410_GPJ(2) /* v2 + v3 + v4 only */
/linux-4.4.14/include/linux/clk/
H A Dat91_pmc.h36 #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
37 #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
38 #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
39 #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
40 #define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
45 #define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */
46 #define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
47 #define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
79 #define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only] */
81 #define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
85 #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
93 #define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */
113 #define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
117 #define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */
120 #define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */
121 #define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */
122 #define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */
125 #define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */
130 #define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */
134 #define AT91_PMC_USBS_PLLB (1 << 0) /* [AT91SAMN12 only] */
139 #define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */
146 #define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */
181 #define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/
/linux-4.4.14/drivers/scsi/
H A Dsun3_scsi.h24 unsigned short dma_addr_hi; /* vme only */
25 unsigned short dma_addr_lo; /* vme only */
26 unsigned short dma_count_hi; /* vme only */
27 unsigned short dma_count_lo; /* vme only */
28 unsigned short udc_data; /* udc dma data reg (obio only) */
29 unsigned short udc_addr; /* uda dma addr reg (obio only) */
34 unsigned short bpack_hi; /* vme only */
35 unsigned short bpack_lo; /* vme only */
36 unsigned short ivect; /* vme only */
37 unsigned short fifo_count_hi; /* vme only */
/linux-4.4.14/arch/s390/mm/
H A Dhugetlbpage.c23 * read-only, clean, old 111.000100.1 -> 00..1...1...01 __pte_to_pmd()
24 * read-only, clean, young 101.000101.1 -> 01..1...0...01 __pte_to_pmd()
25 * read-only, dirty, old 111.000110.1 -> 10..1...1...01 __pte_to_pmd()
26 * read-only, dirty, young 101.000111.1 -> 11..1...0...01 __pte_to_pmd()
31 * HW-bits: R read-only, I invalid __pte_to_pmd()
61 * read-only, clean, old 00..1...1...01 -> 111.000100.1 __pmd_to_pte()
62 * read-only, clean, young 01..1...0...01 -> 101.000101.1 __pmd_to_pte()
63 * read-only, dirty, old 10..1...1...01 -> 111.000110.1 __pmd_to_pte()
64 * read-only, dirty, young 11..1...0...01 -> 101.000111.1 __pmd_to_pte()
69 * HW-bits: R read-only, I invalid __pmd_to_pte()
/linux-4.4.14/fs/ncpfs/
H A Dncp_fs_sb.h114 void (*write_space)(struct sock* sk); /* STREAM mode only */
118 struct mutex creq_mutex; /* DGRAM only: lock accesses to rcv.creq */
120 unsigned int state; /* STREAM only: receiver state */
129 } buf; /* STREAM only: temporary buffer */
130 unsigned char* ptr; /* STREAM only: pointer to data */
131 size_t len; /* STREAM only: length of data to receive */
134 struct list_head requests; /* STREAM only: queued requests */
135 struct work_struct tq; /* STREAM only: transmitter ready */
136 struct ncp_request_reply* creq; /* STREAM only: currently transmitted entry */
138 struct timer_list timeout_tm; /* DGRAM only: timeout timer */
139 struct work_struct timeout_tq; /* DGRAM only: associated queue, we run timers from process context */
140 int timeout_last; /* DGRAM only: current timeout length */
141 int timeout_retries; /* DGRAM only: retries left */
/linux-4.4.14/drivers/acpi/
H A Dreboot.c18 /* ACPI reset register was only introduced with v2 of the FADT */ acpi_reboot()
31 /* The reset register can only exist in I/O, Memory or PCI config space acpi_reboot()
35 /* The reset register can only live on bus 0. */ acpi_reboot()
/linux-4.4.14/include/linux/mfd/
H A Djanz.h38 /* write-only */
42 /* write-only */
50 /* write-only access to EEPROM chip select */
/linux-4.4.14/drivers/sbus/char/
H A Dmax1617.h9 /* Read-only versions of changeable registers. */
17 /* Write-only versions of the same. */
/linux-4.4.14/sound/aoa/codecs/
H A Dtas-basstreble.h2 * This file is only included exactly once!
96 /* I only save the difference here to the treble table
/linux-4.4.14/drivers/md/
H A Ddm-mpath.h15 struct dm_dev *dev; /* Read-only */
H A Ddm-zero.c16 * Construct a dummy mapping that only returns zeros
34 * Return zeros only on reads
43 /* readahead of null bytes only wastes buffer cache */ zero_map()
/linux-4.4.14/arch/um/include/asm/
H A Dcache.h10 /* XXX: this was taken from x86, now it's completely random. Luckily only
/linux-4.4.14/arch/x86/kernel/cpu/
H A Dumc.c6 * UMC chips appear to be only either 386 or 486,
/linux-4.4.14/arch/x86/um/asm/
H A Ddesc.h4 /* Taken from asm-i386/desc.h, it's the only thing we need. The rest wouldn't
/linux-4.4.14/drivers/clk/socfpga/
H A Dclk.h55 u32 width; /* only valid if div_reg != 0 */
56 u32 shift; /* only valid if div_reg != 0 */
65 u32 width; /* only valid if div_reg != 0 */
66 u32 shift; /* only valid if div_reg != 0 */
/linux-4.4.14/lib/zlib_inflate/
H A Dinffixed.h7 is subject to change. Applications should only use zlib.h.
H A DMakefile5 # This is only the decompression, see zlib_deflate for the
H A Dinfutil.h8 subject to change. Applications should only use zlib.h.
/linux-4.4.14/net/ceph/
H A Dauth_none.h23 struct ceph_none_authorizer au; /* we only need one; it's static */
/linux-4.4.14/include/linux/spi/
H A Dmcp23s08.h21 * if only slaves 0 and 3 are present, their GPIOs range from
26 * NOTE: The interrupt functionality is only supported for i2c
38 * occurred on. If it is not set, the interrupt are only generated for
40 * On devices with only one interrupt output this property is useless.
H A Dds1305.h24 /* set only on ds1306 parts */
27 /* ds1306 only: enable 1 Hz output */
H A Dspi_oc_tiny.h11 * freq and baudwidth are used only if the divider is programmable.
/linux-4.4.14/include/uapi/asm-generic/
H A Dswab.h8 * set __SWAB_64_THRU_32__. In user space, this is only
/linux-4.4.14/include/uapi/linux/netfilter_ipv4/
H A Dipt_CLUSTERIP.h25 /* only relevant for new ones */
/linux-4.4.14/arch/mips/include/asm/
H A Dseccomp.h8 * The generic seccomp code currently allows only a single compat ABI. Until
H A Djazzdma.h16 extern void vdma_stats(void); /* for debugging only */
36 * Note that VDMA_PAGE() works for physical addresses only
92 #define R4030_MODE_BURST (1<<6) /* Rev. 2 only */
93 #define R4030_MODE_FAST_ACK (1<<7) /* Rev. 2 only */
/linux-4.4.14/arch/s390/kvm/
H A Dirq.h7 * it under the terms of the GNU General Public License (version 2 only)
H A DMakefile6 # it under the terms of the GNU General Public License (version 2 only)
/linux-4.4.14/arch/sparc/include/asm/
H A Dscratchpad.h10 /* 0x20 and 0x28, hypervisor only... */
H A Dauxio_32.h18 #define AUXIO_FLPY_DENS 0x20 /* Floppy density, high if set. Read only. */
19 #define AUXIO_FLPY_DCHG 0x10 /* A disk change occurred. Read only. */
21 #define AUXIO_FLPY_DSEL 0x08 /* Drive select/start-motor. Write only. */
25 #define AUXIO_FLPY_TCNT 0x04 /* Floppy terminal count. Write only. */
28 #define AUXIO_FLPY_EJCT 0x02 /* Eject floppy disk. Write only. */
H A Dsunbpp.h13 __volatile__ __u32 p_tst_csr; /* Test Control/Status (DMA2 only) */
40 #define P_OCR_V_ILCK 0x0002 /* Versatec faded. Zebra only. */
41 #define P_OCR_EN_VER 0x0001 /* Enable Versatec (0 - enable). Zebra only. */
51 #define P_OR_V2 0x10 /* ) on Zebra only */
/linux-4.4.14/arch/m68k/include/uapi/asm/
H A Dcachectl.h8 #define FLUSH_SCOPE_ALL 3 /* Flush the whole cache -- superuser only */
/linux-4.4.14/arch/cris/include/asm/
H A Ddelay.h12 /* Use only for very small delays ( < 1 msec). */
/linux-4.4.14/arch/cris/include/uapi/arch-v10/arch/
H A Duser.h24 unsigned long p0; /* Constant zero (only 8 bits). */
25 unsigned long vr; /* Version register (only 8 bits). */
28 unsigned long p4; /* Constant zero (only 16 bits). */
29 unsigned long ccr; /* Condition code register (only 16 bits). */
/linux-4.4.14/arch/h8300/include/asm/
H A Dstring.h4 #ifdef __KERNEL__ /* only set these up for kernel code */
/linux-4.4.14/arch/ia64/include/asm/
H A Dparport.h6 * This file should only be included by drivers/parport/parport_pc.c.
H A Dcache.h19 * The "aligned" directive can only _increase_ alignment, so this is
/linux-4.4.14/arch/m32r/include/asm/
H A Dtimex.h16 * Currently only used on SMP.
/linux-4.4.14/arch/arm/plat-omap/
H A DMakefile10 # omap_device support (OMAP2+ only at the moment)
/linux-4.4.14/arch/arm/mach-omap1/
H A Dmmc.h8 #define OMAP1_MMC2_BASE 0xfffb7c00 /* omap16xx only */
/linux-4.4.14/arch/arm/include/asm/
H A Dexception.h4 * These should only be used for C functions that are called from the low
H A Ddomain.h21 * DOMAIN_IO - domain 2 includes all IO only
22 * DOMAIN_USER - domain 1 includes all user memory only
23 * DOMAIN_KERNEL - domain 0 includes all kernel memory only
27 * only be mapped using supersections and supersections can only
33 * 36-bit addressing and supersections are only available on
H A Dmpu.h28 /* C, B and TEX[2:0] bits only have semantic meanings when grouped */
33 /* Main region should only be shared for SMP */
40 /* Access permission bits of ACR (only define those that we use)*/
/linux-4.4.14/arch/arm/kernel/
H A Delf.c27 /* APCS26 is only allowed if the CPU supports it */ elf_check_arch()
47 * We only support Linux ELF executables, so always set the elf_set_personality()
53 * APCS-26 is only valid for OABI executables elf_set_personality()
65 * and CP1, we only enable access to the iWMMXt coprocessor if the elf_set_personality()
/linux-4.4.14/tools/perf/util/
H A Dfind-vdso-map.c16 /* We care only about private r-x mappings. */ find_vdso_map()
/linux-4.4.14/arch/m68k/include/asm/
H A Dm52xxacr.h18 * configurable cache memory that can be instruction only, data only,
21 * cache only. Cache size varies from 2k up to 16k.
47 #define ACR_USER 0x00000000 /* Allow only user accesses */
48 #define ACR_SUPER 0x00002000 /* Allow supervisor access only */
58 * time. For those cores that only have an instruction cache we just set
72 /* This is the instruction cache only devices (no split cache, no eusp) */
H A Ddsp56k.h22 * 0x0000 means reading only, 0x0011 means
24 * Note that HF2 and HF3 can only be read.
H A Dblinken.h2 ** asm/blinken.h -- m68k blinkenlights support (currently hp300 only)
H A Dmac_via.h197 #define vBufAH 0x0200 /* [VIA only] Buffer A, with handshake. DON'T USE! */
198 #define vDirB 0x0400 /* [VIA only] Data Direction Register B. */
199 #define vDirA 0x0600 /* [VIA only] Data Direction Register A. */
200 #define vT1CL 0x0800 /* [VIA only] Timer one counter low. */
201 #define vT1CH 0x0a00 /* [VIA only] Timer one counter high. */
202 #define vT1LL 0x0c00 /* [VIA only] Timer one latches low. */
203 #define vT1LH 0x0e00 /* [VIA only] Timer one latches high. */
204 #define vT2CL 0x1000 /* [VIA only] Timer two counter low. */
205 #define vT2CH 0x1200 /* [VIA only] Timer two counter high. */
206 #define vSR 0x1400 /* [VIA only] Shift register. */
207 #define vACR 0x1600 /* [VIA only] Auxiliary control register. */
208 #define vPCR 0x1800 /* [VIA only] Peripheral control register. */
216 /* The RBV only decodes the bottom eight address lines; the VIA doesn't
218 /* CSA: in fact, only bits 0,1, and 4 seem to be decoded.
226 #define rExp 0x0001 /* [RBV only] RBV future expansion (always 0) */
227 #define rSIFR 0x0002 /* [RBV only] RBV slot interrupts register. */
229 #define rMonP 0x0010 /* [RBV only] RBV video monitor type. */
230 #define rChpT 0x0011 /* [RBV only] RBV test mode register (reads as 0). */
231 #define rSIER 0x0012 /* [RBV only] RBV slot interrupt enables. */
/linux-4.4.14/arch/metag/
H A DMakefile83 @echo ' uImage.bin - Kernel-only image for U-Boot (bin)'
84 @echo ' uImage.gz - Kernel-only image for U-Boot (gzip)'
85 @echo ' uImage.bz2 - Kernel-only image for U-Boot (bzip2)'
86 @echo ' uImage.xz - Kernel-only image for U-Boot (xz)'
87 @echo ' uImage.lzo - Kernel-only image for U-Boot (lzo)'
/linux-4.4.14/drivers/media/platform/s5p-mfc/
H A Ds5p_mfc_opr.h45 volatile void __iomem *dis_shared_mem_addr;/* only v7 */
64 volatile void __iomem *d_min_third_plane_dpb_size;/* only v8 */
67 volatile void __iomem *d_min_num_dis;/* only v7 */
68 volatile void __iomem *d_min_first_dis_size;/* only v7 */
69 volatile void __iomem *d_min_second_dis_size;/* only v7 */
70 volatile void __iomem *d_min_third_dis_size;/* only v7 */
73 volatile void __iomem *d_post_filter_luma_dpb2;/* only v7 */
76 volatile void __iomem *d_post_filter_chroma_dpb2;/* only v7 */
80 volatile void __iomem *d_first_plane_dpb_stride_size;/* only v8 */
81 volatile void __iomem *d_second_plane_dpb_stride_size;/* only v8 */
82 volatile void __iomem *d_third_plane_dpb_stride_size;/* only v8 */
85 volatile void __iomem *d_third_plane_dpb_size;/* only v8 */
111 volatile void __iomem *d_display_third_plane_addr;/* only v8 */
118 volatile void __iomem *d_display_chroma1_crc;/* only v8 */
119 volatile void __iomem *d_display_luma_crc_top;/* only v6 */
120 volatile void __iomem *d_display_chroma_crc_top;/* only v6 */
121 volatile void __iomem *d_display_luma_crc_bot;/* only v6 */
122 volatile void __iomem *d_display_chroma_crc_bot;/* only v6 */
130 volatile void __iomem *d_decoded_third_plane_addr;/* only v8 */
138 volatile void __iomem *d_decoded_chroma1_crc;/* only v8 */
164 volatile void __iomem *d_display_first_addr;/* only v7 */
165 volatile void __iomem *d_display_second_addr;/* only v7 */
166 volatile void __iomem *d_display_third_addr;/* only v7 */
167 volatile void __iomem *d_decoded_first_addr;/* only v7 */
168 volatile void __iomem *d_decoded_second_addr;/* only v7 */
169 volatile void __iomem *d_decoded_third_addr;/* only v7 */
234 volatile void __iomem *e_stream_buffer_write_pointer; /* only v6 */
/linux-4.4.14/drivers/media/radio/si470x/
H A Dradio-si470x.h66 #define POWERCFG_RDSM 0x0800 /* bits 11..11: RDS Mode (Si4701 only) */
78 #define SYSCONFIG1_RDSIEN 0x8000 /* bits 15..15: RDS Interrupt Enable (Si4701 only) */
80 #define SYSCONFIG1_RDS 0x1000 /* bits 12..12: RDS Enable (Si4701 only) */
104 /* TEST2 only contains reserved bits */
107 /* BOOTCONFIG only contains reserved bits */
110 #define STATUSRSSI_RDSR 0x8000 /* bits 15..15: RDS Ready (Si4701 only) */
114 #define STATUSRSSI_RDSS 0x0800 /* bits 11..11: RDS Synchronized (Si4701 only) */
115 #define STATUSRSSI_BLERA 0x0600 /* bits 10..09: RDS Block A Errors (Si4701 only) */
120 #define READCHAN_BLERB 0xc000 /* bits 15..14: RDS Block D Errors (Si4701 only) */
121 #define READCHAN_BLERC 0x3000 /* bits 13..12: RDS Block C Errors (Si4701 only) */
122 #define READCHAN_BLERD 0x0c00 /* bits 11..10: RDS Block B Errors (Si4701 only) */
126 #define RDSA_RDSA 0xffff /* bits 15..00: RDS Block A Data (Si4701 only) */
129 #define RDSB_RDSB 0xffff /* bits 15..00: RDS Block B Data (Si4701 only) */
132 #define RDSC_RDSC 0xffff /* bits 15..00: RDS Block C Data (Si4701 only) */
135 #define RDSD_RDSD 0xffff /* bits 15..00: RDS Block D Data (Si4701 only) */
/linux-4.4.14/drivers/net/ethernet/ti/
H A Ddavinci_cpdma.h101 CPDMA_CMD_IDLE, /* write-only */
106 CPDMA_STAT_IDLE, /* read-only */
107 CPDMA_STAT_TX_ERR_CHAN, /* read-only */
108 CPDMA_STAT_TX_ERR_CODE, /* read-only */
109 CPDMA_STAT_RX_ERR_CHAN, /* read-only */
110 CPDMA_STAT_RX_ERR_CODE, /* read-only */
/linux-4.4.14/arch/m32r/include/uapi/asm/
H A Dptrace.h38 #define PT_ACC1H 17 /* ISA_DSP_LEVEL2 only */
39 #define PT_ACC1L 18 /* ISA_DSP_LEVEL2 only */
58 #define SPR_CR1 PT_CBR /* read only */
62 #define SPR_CR5 PT_EVB /* part of M32R/E, M32R/I core only */
97 unsigned long acc1h; /* ISA_DSP_LEVEL2 only */
98 unsigned long acc1l; /* ISA_DSP_LEVEL2 only */
H A Dsigcontext.h25 unsigned long sc_acc1h; /* ISA_DSP_LEVEL2 only */
26 unsigned long sc_acc1l; /* ISA_DSP_LEVEL2 only */
/linux-4.4.14/sound/firewire/dice/
H A Ddice-interface.h31 * size values are measured in quadlets. Read-only.
59 * A bitmask with asynchronous events; read-only. When any event(s) happen,
127 * Status of the sample clock; read-only.
136 * Status of all clock sources; read-only.
172 * The measured rate of the current clock source, in Hz; read-only.
178 * read-only.
185 * Supported sample rates and clock sources; read-only.
210 * Names of all clock sources; read-only. Quadlets are byte-swapped. Names
223 * The number of supported capture streams; read-only.
228 * The size of one stream's register block, in quadlets; read-only. The
241 * The number of audio channels; read-only. There will be one quadlet per
247 * The number of MIDI ports, 0-8; read-only. If > 0, there will be one
258 * Names of all audio channels; read-only. Quadlets are byte-swapped. Names
266 * Audio IEC60958 capabilities; read-only. Bitmask with one bit per audio
284 * The number of supported playback streams; read-only.
289 * The size of one stream's register block, in quadlets; read-only. The
309 * The number of audio channels; read-only. There will be one quadlet per
315 * The number of MIDI ports, 0-8; read-only. If > 0, there will be one
321 * Names of all audio channels; read-only. Quadlets are byte-swapped. Names
329 * Audio IEC60958 capabilities; read-only. Bitmask with one bit per audio
347 * Current clock source; read-only.
352 * Clock source is locked (boolean); read-only.
358 * _NONE; read-only.
363 * ADAT user data bits; read-only.
/linux-4.4.14/drivers/usb/musb/
H A DMakefile28 # the kconfig must guarantee that only one of the
30 # PIO only, or DMA (several potential schemes).
/linux-4.4.14/drivers/tty/serial/
H A Dm32r_sio_reg.h39 * XR16C85x only */
45 * XR16C85x only */
50 /* (DLAB=1, 16C660 only) */
60 * XR16c85x only */
80 * XR16C85x only */
85 * XR16C85x only */
90 /* (DLAB=1, 16C660 only) */
99 * XR16c85x only */
/linux-4.4.14/arch/alpha/lib/
H A Dudelay.c14 * Use only for very small delays (< 1 msec).
16 * The active part of our cycle counter is only 32-bits wide, and
/linux-4.4.14/mm/
H A Dmmu_context.c17 * (Note: this routine is intended to be called only
48 * (Note: this routine is intended to be called only
/linux-4.4.14/include/xen/
H A Dxen.h33 /* This functionality exists only for x86. The XEN_PVHVM support exists
34 * only in x86 world - hence on ARM it will be always disabled.
/linux-4.4.14/kernel/sched/
H A DMakefile7 # needed for x86 only. Why this used to be enabled for all architectures is beyond
9 # I turn this off for IA-64 only. Andreas Schwab says it's also needed on m68k
/linux-4.4.14/arch/powerpc/perf/
H A Dhv-gpci.h14 __be32 detail_rc; /* O, only needed when called via *_norets() */
17 * O, size each of counter_value element in bytes, only set for version
H A Dhv-24x7.h27 * only valid for VIRTUAL_PROCESSOR domains, ignored for others.
28 * -1 means "current partition only"
87 /* WARNING: only valid for first result element due to variable sizes
104 /* WARNING: only valid for the first result due to variable sizes of
/linux-4.4.14/arch/sh/lib64/
H A Dudelay.c17 * Use only for very small delays (< 1 msec).
19 * The active part of our cycle counter is only 32-bits wide, and
/linux-4.4.14/arch/metag/lib/
H A Ddelay.c18 * TXTACTCYC is only 24 bits, so on chips with fast clocks it will wrap
20 * but this is only likely with large delay values.
/linux-4.4.14/arch/hexagon/include/uapi/asm/
H A Dsigcontext.h6 * only version 2 as published by the Free Software Foundation.
26 * before the signal handler was invoked. Note: only add new entries
/linux-4.4.14/arch/m32r/kernel/
H A Dvmlinux.lds.S27 /* read-only */
28 _text = .; /* Text and read-only data */
/linux-4.4.14/arch/arm/include/debug/
H A Dux500.S18 * DEBUG_LL only works if only one SOC is built in. We don't use #else below
/linux-4.4.14/arch/arm/mach-ks8695/include/mach/
H A Dhardware.h32 * though only 64KiB is needed. This makes it easier for use with the
33 * head debug code as the initial MMU setup only deals in L1 sections.
/linux-4.4.14/net/ieee802154/
H A Dcore.h10 /* wpan_phy index, internal only */
17 /* protected by RTNL only */
/linux-4.4.14/sound/usb/
H A Dmidi.h20 * structure (out_cables and in_cables only) */
36 * structure (out_cables and in_cables only) */
/linux-4.4.14/drivers/staging/sm750fb/
H A Dddk750_mode.h33 /* Clock Phase. This clock phase only applies to Panel. */
/linux-4.4.14/drivers/thunderbolt/
H A Dnhi_regs.h13 RING_FLAG_ISOCH_ENABLE = 1 << 27, /* TX only? */
21 RING_DESC_ISOCH = 0x1, /* TX only? */
84 * cleared on read. New interrupts are fired only after ALL registers have been
85 * read (even those containing only disabled rings).
/linux-4.4.14/drivers/pci/
H A Dhotplug-pci.c1 /* Core PCI functionality used only by PCI hotplug */
/linux-4.4.14/arch/um/include/shared/
H A Dkern.h12 * only into kernel code, and user-space includes conflict with kernel
/linux-4.4.14/arch/um/kernel/
H A Dkmsg_dump.c15 /* only dump kmsg when no console is available */ kmsg_dumper_stdout()
/linux-4.4.14/arch/xtensa/include/asm/
H A Duser.h16 /* This file usually defines a 'struct user' structure. However, it it only
/linux-4.4.14/arch/cris/arch-v32/lib/
H A Ddelay.c16 * On ETRAX FS, we can check the free-running read-only 100MHz timer
/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/pinctrl/
H A Dat91.h6 * GPLv2 only
H A Dqcom,pmic-gpio.h20 * only S3 and L2 options (1.8V)
32 * only L11 and L4 options (1.8V)
53 * only L2(1.15V) and L5(1.8V) options
76 * only S3 and L6 options (1.8V)
85 * only S4 and L6 options (1.8V)
/linux-4.4.14/include/linux/usb/
H A Dusb_phy_generic.h19 /* sometimes transceivers are accessed only through e.g. ULPI */
H A Dm66592.h35 /* (external controller only) M66592_PLATDATA_XTAL_nnMHZ */
38 /* (external controller only) one = 3.3V, zero = 1.5V */
41 /* (external controller only) set one = WR0_N shorted to WR1_N */
/linux-4.4.14/include/dt-bindings/pinctrl/
H A Dat91.h6 * GPLv2 only
H A Dqcom,pmic-gpio.h20 * only S3 and L2 options (1.8V)
32 * only L11 and L4 options (1.8V)
53 * only L2(1.15V) and L5(1.8V) options
76 * only S3 and L6 options (1.8V)
85 * only S4 and L6 options (1.8V)
/linux-4.4.14/include/linux/regulator/
H A Ddb8500-prcmu.h40 * Exported interface for CPUIdle only. This function is called with all
/linux-4.4.14/arch/mips/include/asm/mach-rm/
H A Dwar.h12 * The RM200C seems to have been shipped only with V2.0 R4600s
/linux-4.4.14/arch/mips/kvm/
H A Dopcode.h19 /* COP0 opcodes (only if COP0 and CO=1): */
/linux-4.4.14/arch/s390/boot/compressed/
H A Dvmlinux.lds.S30 *(.rodata) /* read-only data */
/linux-4.4.14/arch/s390/include/uapi/asm/
H A Dkvm_perf.h8 * it under the terms of the GNU General Public License (version 2 only)
H A Dvirtio-ccw.h7 * it under the terms of the GNU General Public License (version 2 only)
H A Dcmb.h16 * @device_active_only_time: time of device active only
24 * this structure, i.e. the last two members are only set when
41 /* extended format only: */
/linux-4.4.14/arch/sh/include/asm/
H A Dstackprotector.h12 * NOTE: this must only be called from functions that never return,
/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/pinctrl/
H A Dat91.h6 * GPLv2 only
H A Dqcom,pmic-gpio.h20 * only S3 and L2 options (1.8V)
32 * only L11 and L4 options (1.8V)
53 * only L2(1.15V) and L5(1.8V) options
76 * only S3 and L6 options (1.8V)
85 * only S4 and L6 options (1.8V)
/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/pinctrl/
H A Dat91.h6 * GPLv2 only
H A Dqcom,pmic-gpio.h20 * only S3 and L2 options (1.8V)
32 * only L11 and L4 options (1.8V)
53 * only L2(1.15V) and L5(1.8V) options
76 * only S3 and L6 options (1.8V)
85 * only S4 and L6 options (1.8V)
/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/pinctrl/
H A Dat91.h6 * GPLv2 only
H A Dqcom,pmic-gpio.h20 * only S3 and L2 options (1.8V)
32 * only L11 and L4 options (1.8V)
53 * only L2(1.15V) and L5(1.8V) options
76 * only S3 and L6 options (1.8V)
85 * only S4 and L6 options (1.8V)
/linux-4.4.14/arch/ia64/kernel/
H A Dgate.lds.S3 * prelinked to its virtual address, with only one read-only segment and
4 * one execute-only segment (both fit in one page). This script controls
78 * PT_LOAD segment, and set the flags explicitly to make segments read-only.
/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/pinctrl/
H A Dat91.h6 * GPLv2 only
H A Dqcom,pmic-gpio.h20 * only S3 and L2 options (1.8V)
32 * only L11 and L4 options (1.8V)
53 * only L2(1.15V) and L5(1.8V) options
76 * only S3 and L6 options (1.8V)
85 * only S4 and L6 options (1.8V)
/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/pinctrl/
H A Dat91.h6 * GPLv2 only
H A Dqcom,pmic-gpio.h20 * only S3 and L2 options (1.8V)
32 * only L11 and L4 options (1.8V)
53 * only L2(1.15V) and L5(1.8V) options
76 * only S3 and L6 options (1.8V)
85 * only S4 and L6 options (1.8V)
/linux-4.4.14/tools/perf/arch/s390/util/
H A Dheader.c8 * it under the terms of the GNU General Public License (version 2 only)
/linux-4.4.14/tools/testing/selftests/powerpc/pmu/
H A DMakefile11 # loop.S can only be built 64-bit
/linux-4.4.14/drivers/staging/rtl8723au/include/
H A Dieee80211.h101 /* tx: cck only , rx: cck only, hw: cck */
103 /* tx: ofdm only, rx: ofdm & cck, hw: cck & ofdm */
105 /* tx: ofdm only, rx: ofdm only, hw: ofdm only */
107 /* tx: MCS only, rx: MCS & cck, hw: MCS & cck */
109 /* tx: MCS only, rx: MCS & ofdm, hw: ofdm only */
119 /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */
123 /* tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only */
234 * only use 8, and then use extended rates for the remaining supported
/linux-4.4.14/drivers/media/platform/s3c-camif/
H A Dcamif-regs.h80 #define CITRGFMT_IN422 (1 << 31) /* only for s3c24xx */
81 #define CITRGFMT_OUT422 (1 << 30) /* only for s3c24xx */
82 #define CITRGFMT_OUTFORMAT_YCBCR420 (0 << 29) /* only for s3c6410 */
83 #define CITRGFMT_OUTFORMAT_YCBCR422 (1 << 29) /* only for s3c6410 */
84 #define CITRGFMT_OUTFORMAT_YCBCR422I (2 << 29) /* only for s3c6410 */
85 #define CITRGFMT_OUTFORMAT_RGB (3 << 29) /* only for s3c6410 */
86 #define CITRGFMT_OUTFORMAT_MASK (3 << 29) /* only for s3c6410 */
93 /* Preview path only */
120 /* s3c244x preview path only, s3c64xx both */
123 #define CIPRSCCTRL_RGB_FORMAT_24BIT (1 << 30) /* only for s3c244x */
124 #define CIPRSCCTRL_SCALEUP_H (1 << 29) /* only for s3c244x */
125 #define CIPRSCCTRL_SCALEUP_V (1 << 28) /* only for s3c244x */
/linux-4.4.14/arch/x86/um/vdso/
H A Dvdso-layout.lds.S3 * its virtual address, and with only one read-only segment.
56 * PT_LOAD segment, and set the flags explicitly to make segments read-only.
/linux-4.4.14/fs/nls/
H A Dnls_koi8-ru.c5 * The Unicode to charset table has only exact mappings.
23 /* koi8-ru and koi8-u differ only on two characters */ uni2char()
45 /* koi8-ru and koi8-u differ only on two characters */ char2uni()
/linux-4.4.14/include/uapi/linux/nfsd/
H A Dexport.h44 * The NFSEXP_V4ROOT flag causes the kernel to give access only to NFSv4
45 * clients, and only to the single directory that is the root of the
49 * pseudofilesystem, which provides access only to paths leading to each
/linux-4.4.14/arch/mn10300/include/asm/
H A Dserial-regs.h28 #define SC0CTR_CK_TM8UFLOW_8 0x0000 /* - 1/8 timer 8 underflow (serial port 0 only) */
29 #define SC0CTR_CK_TM2UFLOW_2 0x0003 /* - 1/2 timer 2 underflow (serial port 0 only) */
30 #define SC0CTR_CK_TM0UFLOW_8 0x0004 /* - 1/8 timer 0 underflow (serial port 0 only) */
31 #define SC0CTR_CK_TM2UFLOW_8 0x0005 /* - 1/8 timer 2 underflow (serial port 0 only) */
32 #define SC1CTR_CK_TM9UFLOW_8 0x0000 /* - 1/8 timer 9 underflow (serial port 1 only) */
33 #define SC1CTR_CK_TM3UFLOW_2 0x0003 /* - 1/2 timer 3 underflow (serial port 1 only) */
34 #define SC1CTR_CK_TM1UFLOW_8 0x0004 /* - 1/8 timer 1 underflow (serial port 1 only) */
35 #define SC1CTR_CK_TM3UFLOW_8 0x0005 /* - 1/8 timer 3 underflow (serial port 1 only) */
37 #define SC0CTR_CK_TM8UFLOW_8 0x0000 /* - 1/8 timer 8 underflow (serial port 0 only) */
38 #define SC0CTR_CK_TM0UFLOW_8 0x0004 /* - 1/8 timer 0 underflow (serial port 0 only) */
39 #define SC0CTR_CK_TM2UFLOW_8 0x0005 /* - 1/8 timer 2 underflow (serial port 0 only) */
40 #define SC1CTR_CK_TM12UFLOW_8 0x0000 /* - 1/8 timer 12 underflow (serial port 1 only) */
/linux-4.4.14/drivers/scsi/fnic/
H A Dfcpio.h121 * The only firmware requests that will use the rx_id/ox_id fields instead
217 u8 lun[LUN_ADDRESS]; /* FC vNIC only: LUN address */
219 u8 d_id[3]; /* FC vNIC only: Target D_ID */
220 u16 mss; /* FC vNIC only: max burst */
222 u32 r_a_tov; /* FC vNIC only: Res. Alloc Timeout */
223 u32 e_d_tov; /* FC vNIC only: Err Detect Timeout */
265 u8 lun[LUN_ADDRESS]; /* FC vNIC only: LUN address */
267 u8 d_id[3]; /* FC vNIC only: Target D_ID */
268 u16 mss; /* FC vNIC only: max burst */
270 u32 r_a_tov; /* FC vNIC only: Res. Alloc Timeout */
271 u32 e_d_tov; /* FC vNIC only: Error Detect Timeout */
280 * The t_tag field is only needed when the request type is ABT_TASK.
287 u8 lun[LUN_ADDRESS]; /* FC vNIC only: LUN address */
289 u8 d_id[3]; /* FC vNIC only: Target D_ID */
290 u32 r_a_tov; /* FC vNIC only: R_A_TOV in msec */
291 u32 e_d_tov; /* FC vNIC only: E_D_TOV in msec */
404 * fc vnic only
410 u8 s_id[3]; /* FC vNIC only: Source S_ID */
429 * scsi vnic only
440 * fc vnic only
446 u8 s_id[3]; /* FC vNIC only: Source S_ID */
532 u8 lun[LUN_ADDRESS]; /* FC vNIC only: LUN address */
540 u8 s_id[3]; /* FC vNIC only: Source S_ID */
565 u8 lun[LUN_ADDRESS]; /* FC vNIC only: LUN address */
573 u8 s_id[3]; /* FC vNIC only: Source S_ID */
595 u8 s_id[3]; /* FC vNIC only: Source S_ID */
596 u8 lun[LUN_ADDRESS]; /* FC vNIC only: LUN address */
643 * fc vnic only
662 * scsi vnic only
672 * scsi vnic only
/linux-4.4.14/drivers/video/fbdev/
H A Dleo.c139 u32 pickmin; /* SS1 only */
140 u32 pickmax; /* SS1 only */
143 u32 src; /* Copy/Scroll (SS0 only) */
144 u32 dst; /* Copy/Scroll/Fill (SS0 only) */
145 u32 extent; /* Copy/Scroll/Fill size (SS0 only) */
147 u32 setsem; /* SS1 only */
148 u32 clrsem; /* SS1 only */
149 u32 clrpick; /* SS1 only */
150 u32 clrdat; /* SS1 only */
151 u32 alpha; /* SS1 only */
157 u32 dczf; /* SS1 only */
158 u32 dczb; /* SS1 only */
159 u32 dcs; /* SS1 only */
160 u32 dczs; /* SS1 only */
161 u32 pickfb; /* SS1 only */
162 u32 pickbb; /* SS1 only */
163 u32 dcfc; /* SS1 only */
164 u32 forcecol; /* SS1 only */
165 u32 door[8]; /* SS1 only */
166 u32 pick[5]; /* SS1 only */
/linux-4.4.14/include/media/davinci/
H A Dvpss.h33 VPSS_PGLPBK, /* for DM365 only */
34 VPSS_CCDCPG /* for DM365 only */
62 /* DM365 only clocks */
90 /* set sync polarity, only for DM365*/
92 /* set the PG_FRAME_SIZE register, only for DM365 */
/linux-4.4.14/drivers/misc/mei/
H A Dhw-me-regs.h142 /* ME_CB_RW - ME Circular Buffer Read Window register (read only) */
144 /* ME_CSR_HA - ME Control Status Host Access register (read only) */
178 /* ME CB (Circular Buffer) Depth HRA (Host Read Access) - host read only
181 /* ME CB Write Pointer HRA - host read only access to ME_CBWP */
183 /* ME CB Read Pointer HRA - host read only access to ME_CBRP */
185 /* ME Power Gate Isolation Capability HRA - host ready only access */
187 /* ME Reset HRA - host read only access to ME_RST */
189 /* ME Ready HRA - host read only access to ME_RDY */
191 /* ME Interrupt Generate HRA - host read only access to ME_IG */
193 /* ME Interrupt Status HRA - host read only access to ME_IS */
195 /* ME Interrupt Enable HRA - host read only access to ME_IE */
/linux-4.4.14/drivers/media/dvb-core/
H A Ddvb_frontend.h131 * Requesting these devices to LOCK is the only thing required,
228 * @get_afc: Used only by analog TV core. Reports the frequency
307 * @get_afc: Used only by analog TV core. Reports the frequency
375 * callback only if DVBv3 API compatibility is wanted.
379 * implementing this callback only if DVBv3 API
384 * implementing this callback only if DVBv3 API
389 * implementing this callback only if DVBv3 API
392 * FE_DISEQC_RESET_OVERLOAD ioctl (only Satellite)
394 * FE_DISEQC_SEND_MASTER_CMD ioctl (only Satellite).
396 * FE_DISEQC_RECV_SLAVE_REPLY ioctl (only Satellite)
398 * FE_DISEQC_SEND_BURST ioctl (only Satellite).
400 * FE_SET_TONE ioctl (only Satellite).
402 * FE_SET_VOLTAGE ioctl (only Satellite).
404 * FE_ENABLE_HIGH_LNB_VOLTAGE ioctl (only Satellite).
406 * FE_DISHNETWORK_SEND_LEGACY_CMD ioctl (only Satellite).
443 /* these two are only used for the swzigzag code */
484 /* Used only internally at dvb_frontend.c */
502 * @voltage: SEC voltage (only Satellite)
503 * @sectone: SEC tone mode (only Satellite)
518 * @isdbt_partial_reception: ISDB-T partial reception (only ISDB standard)
519 * @isdbt_sb_mode: ISDB-T Sound Broadcast (SB) mode (only ISDB standard)
520 * @isdbt_sb_subchannel: ISDB-T SB subchannel (only ISDB standard)
521 * @isdbt_sb_segment_idx: ISDB-T SB segment index (only ISDB standard)
522 * @isdbt_sb_segment_count: ISDB-T SB segment count (only ISDB standard)
523 * @isdbt_layer_enabled: ISDB Layer enabled (only ISDB standard)
524 * @layer: ISDB per-layer data (only ISDB standard)
532 * signaling data (only ATSC-M/H)
533 * @atscmh_parade_id: Parade identification number (only ATSC-M/H)
535 * parade (only ATSC-M/H)
538 * (only ATSC-M/H)
539 * @atscmh_sgn: Start group number (only ATSC-M/H)
540 * @atscmh_prc: Parade repetition cycle (only ATSC-M/H)
541 * @atscmh_rs_frame_mode: Reed Solomon (RS) frame mode (only ATSC-M/H)
542 * @atscmh_rs_frame_ensemble: RS frame ensemble (only ATSC-M/H)
543 * @atscmh_rs_code_mode_pri: RS code mode pri (only ATSC-M/H)
544 * @atscmh_rs_code_mode_sec: RS code mode sec (only ATSC-M/H)
546 * Block Mode (only ATSC-M/H)
547 * @atscmh_sccc_code_mode_a: SCCC code mode A (only ATSC-M/H)
548 * @atscmh_sccc_code_mode_b: SCCC code mode B (only ATSC-M/H)
549 * @atscmh_sccc_code_mode_c: SCCC code mode C (only ATSC-M/H)
550 * @atscmh_sccc_code_mode_d: SCCC code mode D (only ATSC-M/H)
/linux-4.4.14/arch/x86/math-emu/
H A Dload_store.c166 pop_0(); /* pop only if the number was actually stored FPU_load_store()
176 pop_0(); /* pop only if the number was actually stored FPU_load_store()
186 pop_0(); /* pop only if the number was actually stored FPU_load_store()
212 pop_0(); /* pop only if the number was actually stored FPU_load_store()
219 pop_0(); /* pop only if the number was actually stored FPU_load_store()
226 pop_0(); /* pop only if the number was actually stored FPU_load_store()
233 pop_0(); /* pop only if the number was actually stored FPU_load_store()
288 pop_0(); /* pop only if the number was actually stored FPU_load_store()
302 pop_0(); /* pop only if the number was actually stored FPU_load_store()
316 pop_0(); /* pop only if the number was actually stored FPU_load_store()
/linux-4.4.14/arch/sparc/kernel/
H A Dspiterrs.S20 * UDBE_CE in %g1. It only clears ESTATE_ERR_CE in the ESTATE
39 * error bits as-needed. We only clear them if the UE bit is
40 * set. Likewise, __spitfire_cee_trap below will only do so
45 * present on those chips. UltraSparc-IIi only
115 * only for correctable errors during memory read accesses by
118 * The code below is only for trap level 1 CEE events, as it
119 * is the only situation where we can safely record and log.
140 /* Ok, in this case we only have a correctable error.
141 * Indicate we only wish to capture that state in register
142 * %g1, and we only disable CE error reporting unlike UE
/linux-4.4.14/drivers/media/platform/exynos4-is/
H A Dfimc-is-param.h156 /* (only valid at DMA_INPUT_PLANE_2) */
158 /* (only valid at DMA_INPUT_PLANE_2) */
160 /* (only valid at DMA_INPUT_PLANE_1 & DMA_INPUT_FORMAT_YUV444) */
162 /* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
164 /* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
166 /* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
168 /* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
170 /* (only valid at DMA_INPUT_FORMAT_YUV422 & DMA_INPUT_PLANE_1) */
172 /* (only valid at DMA_INPUT_FORMAT_BAYER) */
213 /* only valid at DMA_INPUT_PLANE_2) */
215 /* only valid at DMA_OUTPUT_PLANE_2) */
217 /* only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1 */
219 /* only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1 */
221 /* only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1 */
223 /* only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1 */
225 /* only valid at DMA_OUTPUT_FORMAT_YUV422 & DMA_OUTPUT_PLANE_1 */
227 /* only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1 */
229 /* only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1 */
231 /* only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1 */
233 /* only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1 */
235 /* only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1 */
237 /* only valid at DMA_OUTPUT_FORMAT_YUV444 & DMA_OUPUT_PLANE_1 */
239 /* only valid at DMA_OUTPUT_FORMAT_RGB */
241 /* only valid at DMA_OUTPUT_FORMAT_BAYER */
457 u32 skip_frames; /* only valid at ISP */

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