Searched refs:num_secondary_tile_mode_states (Results 1 – 3 of 3) sorted by relevance
1327 const u32 num_secondary_tile_mode_states = 16; in gfx_v8_0_tiling_mode_table_init() local1514 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { in gfx_v8_0_tiling_mode_table_init()1804 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { in gfx_v8_0_tiling_mode_table_init()2095 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { in gfx_v8_0_tiling_mode_table_init()2362 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { in gfx_v8_0_tiling_mode_table_init()2630 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { in gfx_v8_0_tiling_mode_table_init()
1010 const u32 num_secondary_tile_mode_states = 16; in gfx_v7_0_tiling_mode_table_init() local1202 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { in gfx_v7_0_tiling_mode_table_init()1487 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { in gfx_v7_0_tiling_mode_table_init()1759 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { in gfx_v7_0_tiling_mode_table_init()
2347 const u32 num_secondary_tile_mode_states = 16; in cik_tiling_mode_table_init() local2500 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { in cik_tiling_mode_table_init()2723 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { in cik_tiling_mode_table_init()3078 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { in cik_tiling_mode_table_init()3301 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { in cik_tiling_mode_table_init()