Searched refs:msel (Results 1 – 4 of 4) sorted by relevance
308 static u32 lpc18xx_pll0_msel2mdec(u32 msel) in lpc18xx_pll0_msel2mdec() argument312 switch (msel) { in lpc18xx_pll0_msel2mdec()317 for (i = msel; i <= LPC18XX_PLL0_MSEL_MAX; i++) in lpc18xx_pll0_msel2mdec()324 static u32 lpc18xx_pll0_msel2seli(u32 msel) in lpc18xx_pll0_msel2seli() argument328 if (msel > 16384) return 1; in lpc18xx_pll0_msel2seli()329 if (msel > 8192) return 2; in lpc18xx_pll0_msel2seli()330 if (msel > 2048) return 4; in lpc18xx_pll0_msel2seli()331 if (msel >= 501) return 8; in lpc18xx_pll0_msel2seli()332 if (msel >= 60) { in lpc18xx_pll0_msel2seli()333 tmp = 1024 / (msel + 9); in lpc18xx_pll0_msel2seli()[all …]
141 u32 msel; in pll_get_rate() local146 msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT; in pll_get_rate()149 return clk->parent->rate / (df + 1) * msel * 2; in pll_get_rate()161 u32 msel; in pll_set_rate() local169 msel = rate / clk->parent->rate / 2; in pll_set_rate()170 clk_reg_write_mask(CGU0_CTL, msel << CGU0_CTL_MSEL_SHIFT, in pll_set_rate()187 u32 msel; in sys_clk_get_rate() local192 msel = (ctl & CGU0_CTL_MSEL_MASK) >> CGU0_CTL_MSEL_SHIFT; in sys_clk_get_rate()197 drate *= msel; in sys_clk_get_rate()217 u32 msel; in sys_clk_round_rate() local[all …]
333 u32 msel; in socfpga_fpga_cfg_mode_get() local335 msel = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_STAT_OFST); in socfpga_fpga_cfg_mode_get()336 msel &= SOCFPGA_FPGMGR_STAT_MSEL_MASK; in socfpga_fpga_cfg_mode_get()337 msel >>= SOCFPGA_FPGMGR_STAT_MSEL_SHIFT; in socfpga_fpga_cfg_mode_get()340 if ((msel >= ARRAY_SIZE(cfgmgr_modes)) || !cfgmgr_modes[msel].valid) in socfpga_fpga_cfg_mode_get()343 return msel; in socfpga_fpga_cfg_mode_get()
1149 u_long msel, pll_ctl; local1158 msel = (pll_ctl >> 9) & 0x3F;1159 if (0 == msel)1160 msel = 64;1164 cached_vco *= msel;