| /linux-4.4.14/drivers/gpu/drm/radeon/ |
| H A D | radeon_clocks.c | 67 struct radeon_pll *mpll = &rdev->clock.mpll; radeon_legacy_get_memory_clock() local
73 fb_div *= mpll->reference_freq; radeon_legacy_get_memory_clock()
107 struct radeon_pll *mpll = &rdev->clock.mpll; radeon_read_clocks_OF() local
145 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; radeon_read_clocks_OF()
146 spll->reference_div = mpll->reference_div = radeon_read_clocks_OF()
182 struct radeon_pll *mpll = &rdev->clock.mpll; radeon_get_clock_info() local
214 if (mpll->reference_div < 2) radeon_get_clock_info()
215 mpll->reference_div = spll->reference_div; radeon_get_clock_info()
229 mpll->reference_freq = 1432; radeon_get_clock_info()
234 mpll->reference_freq = 2700; radeon_get_clock_info()
265 mpll->reference_div = spll->reference_div; radeon_get_clock_info()
327 mpll->min_post_div = 1; radeon_get_clock_info()
328 mpll->max_post_div = 1; radeon_get_clock_info()
329 mpll->min_ref_div = 2; radeon_get_clock_info()
330 mpll->max_ref_div = 0xff; radeon_get_clock_info()
331 mpll->min_feedback_div = 4; radeon_get_clock_info()
332 mpll->max_feedback_div = 0xff; radeon_get_clock_info()
333 mpll->best_vco = 0; radeon_get_clock_info()
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| H A D | radeon_combios.c | 737 struct radeon_pll *mpll = &rdev->clock.mpll; radeon_combios_get_clock_info() local
778 mpll->reference_freq = RBIOS16(pll_info + 0x26); radeon_combios_get_clock_info()
779 mpll->reference_div = RBIOS16(pll_info + 0x28); radeon_combios_get_clock_info()
780 mpll->pll_out_min = RBIOS32(pll_info + 0x2a); radeon_combios_get_clock_info()
781 mpll->pll_out_max = RBIOS32(pll_info + 0x2e); radeon_combios_get_clock_info()
784 mpll->pll_in_min = RBIOS32(pll_info + 0x5a); radeon_combios_get_clock_info()
785 mpll->pll_in_max = RBIOS32(pll_info + 0x5e); radeon_combios_get_clock_info()
788 mpll->pll_in_min = 40; radeon_combios_get_clock_info()
789 mpll->pll_in_max = 500; radeon_combios_get_clock_info()
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| H A D | rv740_dpm.c | 252 u32 reference_clock = rdev->clock.mpll.reference_freq; rv740_populate_mclk_value()
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| H A D | radeon_atombios.c | 1145 struct radeon_pll *mpll = &rdev->clock.mpll; radeon_atom_get_clock_info() local
1224 mpll->reference_freq = radeon_atom_get_clock_info()
1227 mpll->reference_freq = radeon_atom_get_clock_info()
1229 mpll->reference_div = 0; radeon_atom_get_clock_info()
1231 mpll->pll_out_min = radeon_atom_get_clock_info()
1233 mpll->pll_out_max = radeon_atom_get_clock_info()
1237 if (mpll->pll_out_min == 0) { radeon_atom_get_clock_info()
1239 mpll->pll_out_min = 64800; radeon_atom_get_clock_info()
1241 mpll->pll_out_min = 20000; radeon_atom_get_clock_info()
1244 mpll->pll_in_min = radeon_atom_get_clock_info()
1246 mpll->pll_in_max = radeon_atom_get_clock_info()
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| H A D | rv730_dpm.c | 172 u32 reference_clock = rdev->clock.mpll.reference_freq; rv730_populate_mclk_value()
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| H A D | cypress_dpm.c | 443 u32 ref_clk = rdev->clock.mpll.reference_freq; cypress_map_clkf_to_ibias()
559 u32 reference_clock = rdev->clock.mpll.reference_freq; cypress_populate_mclk_value()
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| H A D | rv6xx_dpm.c | 656 u32 ref_clk = rdev->clock.mpll.reference_freq; rv6xx_program_mclk_spread_spectrum_parameters()
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| H A D | rv770_dpm.c | 404 u32 reference_clock = rdev->clock.mpll.reference_freq; rv770_populate_mclk_value()
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| H A D | radeon.h | 263 struct radeon_pll mpll; member in struct:radeon_clock
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| H A D | ci_dpm.c | 2801 u32 reference_clock = rdev->clock.mpll.reference_freq; ci_calculate_mclk_params()
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| H A D | ni_dpm.c | 2242 u32 reference_clock = rdev->clock.mpll.reference_freq; ni_populate_mclk_value()
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| H A D | si_dpm.c | 4930 u32 reference_clock = rdev->clock.mpll.reference_freq; si_populate_mclk_value()
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| /linux-4.4.14/arch/arm/mach-s3c24xx/ |
| H A D | cpufreq-utils.c | 64 if (!IS_ERR(cfg->mpll)) s3c2410_set_fvco()
65 clk_set_rate(cfg->mpll, cfg->pll.frequency); s3c2410_set_fvco()
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| /linux-4.4.14/drivers/clk/samsung/ |
| H A D | clk-s3c2410.c | 38 mpll, upll, enumerator in enum:s3c2410_plls
96 PNAME(fclk_p) = { "mpll", "div_slow" };
151 ALIAS(MPLL, NULL, "mpll"),
197 [mpll] = PLL(pll_s3c2410_mpll, MPLL, "mpll", "xti",
204 DIV(HCLK, "hclk", "mpll", CLKDIVN, 1, 1),
263 [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
386 s3c2410_plls[mpll].rate_table = pll_s3c2410_12mhz_tbl; s3c2410_common_clk_init()
400 s3c244x_common_plls[mpll].rate_table = s3c2410_common_clk_init()
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| H A D | clk-s3c2412.c | 32 mpll, upll, enumerator in enum:s3c2412_plls
126 PNAME(i2sclk_p) = { "erefclk", "mpll" };
127 PNAME(uartclk_p) = { "erefclk", "mpll" };
129 PNAME(msysclk_p) = { "mdivclk", "mpll" };
147 [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
203 ALIAS(MPLL, NULL, "mpll"),
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| H A D | clk-s3c2443.c | 46 mpll, epll, enumerator in enum:s3c2443_plls
112 PNAME(msysclk_p) = { "mpllref", "mpll" };
224 [mpll] = PLL(pll_6552_s3c2416, 0, "mpll", "mpllref",
278 [mpll] = PLL(pll_3000, 0, "mpll", "mpllref",
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| H A D | clk-exynos5410.c | 56 apll, cpll, mpll, enumerator in enum:exynos5410_plls
175 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
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| H A D | clk-s3c2410-dclk.c | 143 static const char *clkout0_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
145 static const char *clkout1_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
148 static const char *clkout0_s3c2412_p[] = { "mpll", "upll", "rtc_clkout",
155 static const char *clkout1_s3c2440_p[] = { "mpll", "upll", "rtc_clkout",
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| H A D | clk-s3c64xx.c | 61 apll, mpll, epll, enumerator in enum:s3c64xx_plls
369 [mpll] = PLL(pll_6552, FOUT_MPLL, "fout_mpll", "fin_pll",
522 pr_info("%s clocks: apll = %lu, mpll = %lu\n" s3c64xx_clk_init()
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| H A D | clk-s5pv210.c | 73 mpll, enumerator in enum:__anon3786
759 [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",
771 [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",
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| H A D | clk-exynos5250.c | 107 apll, mpll, cpll, epll, vpll, gpll, bpll, enumerator in enum:exynos5250_plls
748 [mpll] = PLL_A(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
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| H A D | clk-exynos4.c | 153 apll, mpll, epll, vpll, enumerator in enum:exynos4_plls
1342 [mpll] = PLL_A(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
1353 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
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| H A D | clk-exynos5420.c | 146 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, enumerator in enum:exynos5x_plls
1241 [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
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| /linux-4.4.14/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_atombios.c | 560 struct amdgpu_pll *mpll = &adev->clock.mpll; amdgpu_atombios_get_clock_info() local
641 mpll->reference_freq = amdgpu_atombios_get_clock_info()
643 mpll->reference_div = 0; amdgpu_atombios_get_clock_info()
645 mpll->pll_out_min = amdgpu_atombios_get_clock_info()
647 mpll->pll_out_max = amdgpu_atombios_get_clock_info()
651 if (mpll->pll_out_min == 0) amdgpu_atombios_get_clock_info()
652 mpll->pll_out_min = 64800; amdgpu_atombios_get_clock_info()
654 mpll->pll_in_min = amdgpu_atombios_get_clock_info()
656 mpll->pll_in_max = amdgpu_atombios_get_clock_info()
664 mpll->min_post_div = 1; amdgpu_atombios_get_clock_info()
665 mpll->max_post_div = 1; amdgpu_atombios_get_clock_info()
666 mpll->min_ref_div = 2; amdgpu_atombios_get_clock_info()
667 mpll->max_ref_div = 0xff; amdgpu_atombios_get_clock_info()
668 mpll->min_feedback_div = 4; amdgpu_atombios_get_clock_info()
669 mpll->max_feedback_div = 0xff; amdgpu_atombios_get_clock_info()
670 mpll->best_vco = 0; amdgpu_atombios_get_clock_info()
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| H A D | amdgpu.h | 378 struct amdgpu_pll mpll; member in struct:amdgpu_clock
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| H A D | ci_dpm.c | 2934 u32 reference_clock = adev->clock.mpll.reference_freq; ci_calculate_mclk_params()
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| /linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
| H A D | nv04.c | 288 bool mpll = Preg == 0x4020; setPLL_double_lowregs() local
291 uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) | setPLL_double_lowregs()
306 if (mpll) { setPLL_double_lowregs()
322 Pval |= mpll ? 1 << 12 : 1 << 8; setPLL_double_lowregs()
326 if (mpll) { setPLL_double_lowregs()
340 if (mpll) { setPLL_double_lowregs()
349 if (mpll) { setPLL_double_lowregs()
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| /linux-4.4.14/drivers/clk/imx/ |
| H A D | clk-imx27.c | 33 static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", };
38 "ckih_gate", "mpll", "spll", "cpu_div",
45 static const char *ssi_sel_clks[] = { "spll_gate", "mpll", };
73 clk[IMX27_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX27, "mpll", "mpll_sel", CCM_MPCTL0); _mx27_clocks_init()
76 clk[IMX27_CLK_MPLL_MAIN2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3); _mx27_clocks_init()
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| H A D | clk-imx35.c | 69 ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg, enumerator in enum:mx35_clks
119 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL); _mx35_clocks_init()
122 clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4); _mx35_clocks_init()
127 clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm); _mx35_clocks_init()
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| H A D | clk-imx1.c | 56 clk[IMX1_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX1, "mpll", "clk32_premult", CCM_MPCTL0); _mx1_clocks_init()
57 clk[IMX1_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0); _mx1_clocks_init()
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| H A D | clk-imx31.c | 45 static const char *mcu_main_sel[] = { "spll", "mpll", };
51 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, enumerator in enum:mx31_clks
86 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL); _mx31_clocks_init()
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| H A D | clk-imx25.c | 58 static const char *cpu_sel_clks[] = { "mpll", "mpll_cpu_3_4", };
66 dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg, enumerator in enum:mx25_clks
106 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "mpll", "osc", ccm(CCM_MPCTL)); __mx25_clocks_init()
108 clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4); __mx25_clocks_init()
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| H A D | clk-imx21.c | 55 clk[IMX21_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0); _mx21_clocks_init()
69 clk[IMX21_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX21, "mpll", "mpll_sel", CCM_MPCTL0); _mx21_clocks_init()
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| /linux-4.4.14/sound/soc/samsung/ |
| H A D | s3c2412-i2s.c | 74 clk_set_parent(s3c2412_i2s.iis_cclk, clk_get(NULL, "mpll")); s3c2412_i2s_probe()
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| /linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| H A D | ramnv50.c | 226 struct nvbios_pll mpll; nv50_ram_calc() local
328 ret = nvbios_pll_parse(bios, 0x004008, &mpll); nv50_ram_calc()
329 mpll.vco2.max_freq = 0; nv50_ram_calc()
331 ret = nv04_pll_calc(subdev, &mpll, freq, nv50_ram_calc()
349 r004008 |= (mpll.bias_p << 19) | (P << 22) | (P << 16); nv50_ram_calc()
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| /linux-4.4.14/drivers/cpufreq/ |
| H A D | s3c24xx-cpufreq.c | 143 cfg->mpll = _clk_mpll; s3c_cpufreq_setfvco()
372 _clk_mpll = s3c_cpufreq_clk_get(NULL, "mpll"); s3c_cpufreq_initclks()
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| /linux-4.4.14/drivers/clk/ingenic/ |
| H A D | jz4780-cgu.c | 253 "mpll", CGU_CLK_PLL,
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| /linux-4.4.14/arch/arm/plat-samsung/include/plat/ |
| H A D | cpu-freq-core.h | 122 struct clk *mpll; member in struct:s3c_cpufreq_config
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| /linux-4.4.14/drivers/gpu/drm/nouveau/dispnv04/ |
| H A D | crtc.c | 102 * mpll: 0x4020 + 0x4024
103 * mpll: 0x4038 + 0x403c
107 * bits 20-23: (mpll) something to do with post divider?
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| /linux-4.4.14/drivers/media/platform/exynos4-is/ |
| H A D | fimc-is.c | 50 [ISS_CLK_MPLL] = "mpll",
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| /linux-4.4.14/drivers/clk/mediatek/ |
| H A D | clk-mt8173.c | 1052 PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0x00000001, 0, 21, 0x280, 4, 0x0, 0x284, 0),
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