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Searched refs:mmVGA_RENDER_CONTROL (Results 1 – 8 of 8) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Dvi.c349 vga_render_control = RREG32(mmVGA_RENDER_CONTROL); in vi_read_disabled_bios()
363 WREG32(mmVGA_RENDER_CONTROL, in vi_read_disabled_bios()
375 WREG32(mmVGA_RENDER_CONTROL, vga_render_control); in vi_read_disabled_bios()
Dcik.c900 vga_render_control = RREG32(mmVGA_RENDER_CONTROL); in cik_read_disabled_bios()
914 WREG32(mmVGA_RENDER_CONTROL, in cik_read_disabled_bios()
926 WREG32(mmVGA_RENDER_CONTROL, vga_render_control); in cik_read_disabled_bios()
Ddce_v8_0.c513 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); in dce_v8_0_stop_mc_access()
517 tmp = RREG32(mmVGA_RENDER_CONTROL); in dce_v8_0_stop_mc_access()
519 WREG32(mmVGA_RENDER_CONTROL, tmp); in dce_v8_0_stop_mc_access()
632 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); in dce_v8_0_resume_mc_access()
649 tmp = RREG32(mmVGA_RENDER_CONTROL); in dce_v8_0_set_vga_render_state()
654 WREG32(mmVGA_RENDER_CONTROL, tmp); in dce_v8_0_set_vga_render_state()
Ddce_v11_0.c553 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); in dce_v11_0_stop_mc_access()
557 tmp = RREG32(mmVGA_RENDER_CONTROL); in dce_v11_0_stop_mc_access()
559 WREG32(mmVGA_RENDER_CONTROL, tmp); in dce_v11_0_stop_mc_access()
672 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); in dce_v11_0_resume_mc_access()
689 tmp = RREG32(mmVGA_RENDER_CONTROL); in dce_v11_0_set_vga_render_state()
694 WREG32(mmVGA_RENDER_CONTROL, tmp); in dce_v11_0_set_vga_render_state()
Ddce_v10_0.c565 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); in dce_v10_0_stop_mc_access()
569 tmp = RREG32(mmVGA_RENDER_CONTROL); in dce_v10_0_stop_mc_access()
571 WREG32(mmVGA_RENDER_CONTROL, tmp); in dce_v10_0_stop_mc_access()
684 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); in dce_v10_0_resume_mc_access()
701 tmp = RREG32(mmVGA_RENDER_CONTROL); in dce_v10_0_set_vga_render_state()
706 WREG32(mmVGA_RENDER_CONTROL, tmp); in dce_v10_0_set_vga_render_state()
/linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_d.h5124 #define mmVGA_RENDER_CONTROL 0xc0 macro
Ddce_11_0_d.h6084 #define mmVGA_RENDER_CONTROL 0xc0 macro
Ddce_10_0_d.h6008 #define mmVGA_RENDER_CONTROL 0xc0 macro