Searched refs:mmUVD_SEMA_CNTL (Results 1 – 6 of 6) sorted by relevance
37 #define mmUVD_SEMA_CNTL 0x3d00 macro
43 #define mmUVD_SEMA_CNTL 0x3d00 macro
44 #define mmUVD_SEMA_CNTL 0x3d00 macro
182 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v6_0_hw_init()665 RREG32(mmUVD_SEMA_CNTL)); in uvd_v6_0_print_status()
185 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v5_0_hw_init()673 RREG32(mmUVD_SEMA_CNTL)); in uvd_v5_0_print_status()
189 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); in uvd_v4_2_hw_init()730 RREG32(mmUVD_SEMA_CNTL)); in uvd_v4_2_print_status()