Searched refs:mmUVD_SEMA_CMD (Results 1 – 6 of 6) sorted by relevance
29 #define mmUVD_SEMA_CMD 0x3bc2 macro
506 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CMD, 0)); in uvd_v6_0_ring_emit_semaphore()649 RREG32(mmUVD_SEMA_CMD)); in uvd_v6_0_print_status()
506 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CMD, 0)); in uvd_v5_0_ring_emit_semaphore()657 RREG32(mmUVD_SEMA_CMD)); in uvd_v5_0_print_status()
462 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CMD, 0)); in uvd_v4_2_ring_emit_semaphore()714 RREG32(mmUVD_SEMA_CMD)); in uvd_v4_2_print_status()