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Searched refs:mmSMC_RESP_0 (Results 1 – 13 of 13) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Dkv_smc.c41 if ((RREG32(mmSMC_RESP_0) & SMC_RESP_0__SMC_RESP_MASK) != 0) in amdgpu_kv_notify_message_to_smu()
45 tmp = RREG32(mmSMC_RESP_0) & SMC_RESP_0__SMC_RESP_MASK; in amdgpu_kv_notify_message_to_smu()
Dci_smc.c180 tmp = RREG32(mmSMC_RESP_0); in amdgpu_ci_send_msg_to_smc()
185 tmp = RREG32(mmSMC_RESP_0); in amdgpu_ci_send_msg_to_smc()
Diceland_smc.c178 val = RREG32(mmSMC_RESP_0); in wait_smu_response()
Dfiji_smc.c142 val = RREG32(mmSMC_RESP_0); in wait_smu_response()
Dtonga_smc.c142 val = RREG32(mmSMC_RESP_0); in wait_smu_response()
Dkv_dpm.c3196 RREG32(mmSMC_RESP_0)); in kv_dpm_print_status()
Dci_dpm.c2043 if (RREG32(mmSMC_RESP_0) == 1)
6542 RREG32(mmSMC_RESP_0)); in ci_dpm_print_status()
/linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_7_0_0_d.h91 #define mmSMC_RESP_0 0x95 macro
Dsmu_7_1_1_d.h92 #define mmSMC_RESP_0 0x95 macro
Dsmu_7_1_2_d.h92 #define mmSMC_RESP_0 0x95 macro
Dsmu_7_1_3_d.h95 #define mmSMC_RESP_0 0x95 macro
Dsmu_7_0_1_d.h92 #define mmSMC_RESP_0 0x95 macro
Dsmu_7_1_0_d.h92 #define mmSMC_RESP_0 0x95 macro