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Searched refs:mmMC_SEQ_WR_CTL_D1 (Results 1 – 3 of 3) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_7_1_d.h644 #define mmMC_SEQ_WR_CTL_D1 0xa30 macro
Dgmc_8_1_d.h748 #define mmMC_SEQ_WR_CTL_D1 0xa30 macro
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Dci_dpm.c4587 case mmMC_SEQ_WR_CTL_D1: in ci_check_s0_mc_reg_index()
4705 case mmMC_SEQ_WR_CTL_D1: in ci_register_patching_mc_seq()
4786 WREG32(mmMC_SEQ_WR_CTL_D1_LP, RREG32(mmMC_SEQ_WR_CTL_D1)); in ci_initialize_mc_reg_table()
6510 RREG32(mmMC_SEQ_WR_CTL_D1)); in ci_dpm_print_status()