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Searched refs:mmMC_SEQ_WR_CTL_2_LP (Results 1 – 3 of 3) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/gmc/
Dgmc_7_1_d.h820 #define mmMC_SEQ_WR_CTL_2_LP 0xad6 macro
Dgmc_8_1_d.h924 #define mmMC_SEQ_WR_CTL_2_LP 0xad6 macro
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Dci_dpm.c4606 *out_reg = mmMC_SEQ_WR_CTL_2_LP; in ci_check_s0_mc_reg_index()
4791 WREG32(mmMC_SEQ_WR_CTL_2_LP, RREG32(mmMC_SEQ_WR_CTL_2)); in ci_initialize_mc_reg_table()
6528 RREG32(mmMC_SEQ_WR_CTL_2_LP)); in ci_dpm_print_status()