Searched refs:mmGRPH_PRIMARY_SURFACE_ADDRESS (Results 1 – 6 of 6) sorted by relevance
244 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v8_0_page_flip()247 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v8_0_page_flip()584 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], in dce_v8_0_resume_mc_access()2132 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v8_0_crtc_do_set_base()
285 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v11_0_page_flip()288 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v11_0_page_flip()624 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], in dce_v11_0_resume_mc_access()2196 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
295 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v10_0_page_flip()298 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v10_0_page_flip()636 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], in dce_v10_0_resume_mc_access()2208 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
1562 #define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 macro
2306 #define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 macro
2412 #define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1a04 macro