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Searched refs:mmCRTC_UPDATE_LOCK (Results 1 – 6 of 6) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Ddce_v8_0.c534 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v8_0_stop_mc_access()
537 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); in dce_v8_0_stop_mc_access()
558 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v8_0_stop_mc_access()
562 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); in dce_v8_0_stop_mc_access()
613 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v8_0_resume_mc_access()
615 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); in dce_v8_0_resume_mc_access()
Ddce_v11_0.c574 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v11_0_stop_mc_access()
577 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); in dce_v11_0_stop_mc_access()
598 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v11_0_stop_mc_access()
602 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); in dce_v11_0_stop_mc_access()
653 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v11_0_resume_mc_access()
655 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); in dce_v11_0_resume_mc_access()
Ddce_v10_0.c586 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v10_0_stop_mc_access()
589 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); in dce_v10_0_stop_mc_access()
610 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v10_0_stop_mc_access()
614 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); in dce_v10_0_stop_mc_access()
665 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v10_0_resume_mc_access()
667 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); in dce_v10_0_resume_mc_access()
/linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_d.h508 #define mmCRTC_UPDATE_LOCK 0x1bb5 macro
Ddce_11_0_d.h490 #define mmCRTC_UPDATE_LOCK 0x1bb5 macro
Ddce_10_0_d.h588 #define mmCRTC_UPDATE_LOCK 0x1bb5 macro