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Searched refs:mmCRTC_BLANK_CONTROL (Results 1 – 6 of 6) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Ddce_v8_0.c531 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); in dce_v8_0_stop_mc_access()
536 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); in dce_v8_0_stop_mc_access()
611 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); in dce_v8_0_resume_mc_access()
614 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); in dce_v8_0_resume_mc_access()
Ddce_v11_0.c571 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); in dce_v11_0_stop_mc_access()
576 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); in dce_v11_0_stop_mc_access()
651 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); in dce_v11_0_resume_mc_access()
654 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); in dce_v11_0_resume_mc_access()
Ddce_v10_0.c583 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); in dce_v10_0_stop_mc_access()
588 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); in dce_v10_0_stop_mc_access()
663 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); in dce_v10_0_resume_mc_access()
666 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); in dce_v10_0_resume_mc_access()
/linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_8_0_d.h340 #define mmCRTC_BLANK_CONTROL 0x1b9d macro
Ddce_11_0_d.h322 #define mmCRTC_BLANK_CONTROL 0x1b9d macro
Ddce_10_0_d.h396 #define mmCRTC_BLANK_CONTROL 0x1b9d macro