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Searched refs:mmCP_ME_CNTL (Results 1 – 8 of 8) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Dvi.c721 tmp = RREG32(mmCP_ME_CNTL); in vi_gpu_soft_reset()
725 WREG32(mmCP_ME_CNTL, tmp); in vi_gpu_soft_reset()
864 tmp = RREG32(mmCP_ME_CNTL); in vi_gpu_pci_config_reset()
868 WREG32(mmCP_ME_CNTL, tmp); in vi_gpu_pci_config_reset()
877 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | in vi_gpu_pci_config_reset()
Dcik.c1181 …WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MA… in cik_gpu_soft_reset()
1386 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | in cik_gpu_pci_config_reset()
Dgfx_v7_0.c2745 WREG32(mmCP_ME_CNTL, 0); in gfx_v7_0_cp_gfx_enable()
2747 …WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_M… in gfx_v7_0_cp_gfx_enable()
5064 RREG32(mmCP_ME_CNTL)); in gfx_v7_0_print_status()
5256 …WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MA… in gfx_v7_0_soft_reset()
Dgfx_v8_0.c3110 u32 tmp = RREG32(mmCP_ME_CNTL); in gfx_v8_0_cp_gfx_enable()
3123 WREG32(mmCP_ME_CNTL, tmp); in gfx_v8_0_cp_gfx_enable()
4217 RREG32(mmCP_ME_CNTL)); in gfx_v8_0_print_status()
/linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_d.h518 #define mmCP_ME_CNTL 0x21b6 macro
Dgfx_7_0_d.h505 #define mmCP_ME_CNTL 0x21b6 macro
Dgfx_8_0_d.h571 #define mmCP_ME_CNTL 0x21b6 macro
Dgfx_8_1_d.h571 #define mmCP_ME_CNTL 0x21b6 macro