Searched refs:mmCP_MEC_CNTL (Results 1 – 9 of 9) sorted by relevance
| /linux-4.4.14/drivers/gpu/drm/amd/amdgpu/ |
| D | vi.c | 728 tmp = RREG32(mmCP_MEC_CNTL); in vi_gpu_soft_reset()
731 WREG32(mmCP_MEC_CNTL, tmp); in vi_gpu_soft_reset()
871 tmp = RREG32(mmCP_MEC_CNTL); in vi_gpu_pci_config_reset()
874 WREG32(mmCP_MEC_CNTL, tmp); in vi_gpu_pci_config_reset()
881 WREG32(mmCP_MEC_CNTL, in vi_gpu_pci_config_reset()
|
| D | cz_smc.c | 279 tmp = RREG32(mmCP_MEC_CNTL); in cz_load_mec_firmware()
282 WREG32(mmCP_MEC_CNTL, tmp); in cz_load_mec_firmware()
|
| D | cik.c | 1184 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); in cik_gpu_soft_reset()
1390 WREG32(mmCP_MEC_CNTL, in cik_gpu_pci_config_reset()
|
| D | gfx_v7_0.c | 3058 WREG32(mmCP_MEC_CNTL, 0); in gfx_v7_0_cp_compute_enable()
3060 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v7_0_cp_compute_enable()
5097 RREG32(mmCP_MEC_CNTL)); in gfx_v7_0_print_status()
5259 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); in gfx_v7_0_soft_reset()
|
| D | gfx_v8_0.c | 3382 WREG32(mmCP_MEC_CNTL, 0); in gfx_v8_0_cp_compute_enable()
3384 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v8_0_cp_compute_enable()
4247 RREG32(mmCP_MEC_CNTL)); in gfx_v8_0_print_status()
|
| /linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/gca/ |
| D | gfx_7_2_d.h | 322 #define mmCP_MEC_CNTL 0x208d macro
|
| D | gfx_7_0_d.h | 319 #define mmCP_MEC_CNTL 0x208d macro
|
| D | gfx_8_0_d.h | 357 #define mmCP_MEC_CNTL 0x208d macro
|
| D | gfx_8_1_d.h | 357 #define mmCP_MEC_CNTL 0x208d macro
|