Searched refs:mdp5_cfg (Results 1 - 7 of 7) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/msm/mdp/mdp5/
H A Dmdp5_cfg.h20 * mdp5_cfg
23 * (initialized in mdp5_cfg.c)
25 extern const struct mdp5_cfg_hw *mdp5_cfg;
104 struct mdp5_cfg { struct
113 struct mdp5_cfg *mdp5_cfg_get_config(struct mdp5_cfg_handler *cfg_hnd);
H A Dmdp5_cfg.c15 #include "mdp5_cfg.h"
19 struct mdp5_cfg config;
22 /* mdp5_cfg must be exposed (used in mdp5.xml.h) */
23 const struct mdp5_cfg_hw *mdp5_cfg = NULL; variable in typeref:struct:mdp5_cfg_hw
484 struct mdp5_cfg *mdp5_cfg_get_config(struct mdp5_cfg_handler *cfg_handler) mdp5_cfg_get_config()
521 /* only after mdp5_cfg global pointer's init can we access the hw */ mdp5_cfg_init()
525 mdp5_cfg = cfg_handlers[i].config.hw; mdp5_cfg_init()
529 if (unlikely(!mdp5_cfg)) { mdp5_cfg_init()
537 cfg_handler->config.hw = mdp5_cfg; mdp5_cfg_init()
542 DBG("MDP5: %s hw config selected", mdp5_cfg->name); mdp5_cfg_init()
H A Dmdp5.xml.h203 case 0: return (mdp5_cfg->mdp.base[0]); __offset_MDP()
357 case 0: return (mdp5_cfg->ctl.base[0]); __offset_CTL()
358 case 1: return (mdp5_cfg->ctl.base[1]); __offset_CTL()
359 case 2: return (mdp5_cfg->ctl.base[2]); __offset_CTL()
360 case 3: return (mdp5_cfg->ctl.base[3]); __offset_CTL()
361 case 4: return (mdp5_cfg->ctl.base[4]); __offset_CTL()
543 case SSPP_VIG0: return (mdp5_cfg->pipe_vig.base[0]); __offset_PIPE()
544 case SSPP_VIG1: return (mdp5_cfg->pipe_vig.base[1]); __offset_PIPE()
545 case SSPP_VIG2: return (mdp5_cfg->pipe_vig.base[2]); __offset_PIPE()
546 case SSPP_RGB0: return (mdp5_cfg->pipe_rgb.base[0]); __offset_PIPE()
547 case SSPP_RGB1: return (mdp5_cfg->pipe_rgb.base[1]); __offset_PIPE()
548 case SSPP_RGB2: return (mdp5_cfg->pipe_rgb.base[2]); __offset_PIPE()
549 case SSPP_DMA0: return (mdp5_cfg->pipe_dma.base[0]); __offset_PIPE()
550 case SSPP_DMA1: return (mdp5_cfg->pipe_dma.base[1]); __offset_PIPE()
551 case SSPP_VIG3: return (mdp5_cfg->pipe_vig.base[3]); __offset_PIPE()
552 case SSPP_RGB3: return (mdp5_cfg->pipe_rgb.base[3]); __offset_PIPE()
1068 case 0: return (mdp5_cfg->lm.base[0]); __offset_LM()
1069 case 1: return (mdp5_cfg->lm.base[1]); __offset_LM()
1070 case 2: return (mdp5_cfg->lm.base[2]); __offset_LM()
1071 case 3: return (mdp5_cfg->lm.base[3]); __offset_LM()
1072 case 4: return (mdp5_cfg->lm.base[4]); __offset_LM()
1073 case 5: return (mdp5_cfg->lm.base[5]); __offset_LM()
1259 case 0: return (mdp5_cfg->dspp.base[0]); __offset_DSPP()
1260 case 1: return (mdp5_cfg->dspp.base[1]); __offset_DSPP()
1261 case 2: return (mdp5_cfg->dspp.base[2]); __offset_DSPP()
1262 case 3: return (mdp5_cfg->dspp.base[3]); __offset_DSPP()
1304 case 0: return (mdp5_cfg->pp.base[0]); __offset_PP()
1305 case 1: return (mdp5_cfg->pp.base[1]); __offset_PP()
1306 case 2: return (mdp5_cfg->pp.base[2]); __offset_PP()
1307 case 3: return (mdp5_cfg->pp.base[3]); __offset_PP()
1393 case 0: return (mdp5_cfg->wb.base[0]); __offset_WB()
1394 case 1: return (mdp5_cfg->wb.base[1]); __offset_WB()
1395 case 2: return (mdp5_cfg->wb.base[2]); __offset_WB()
1396 case 3: return (mdp5_cfg->wb.base[3]); __offset_WB()
1397 case 4: return (mdp5_cfg->wb.base[4]); __offset_WB()
1744 case 0: return (mdp5_cfg->intf.base[0]); __offset_INTF()
1745 case 1: return (mdp5_cfg->intf.base[1]); __offset_INTF()
1746 case 2: return (mdp5_cfg->intf.base[2]); __offset_INTF()
1747 case 3: return (mdp5_cfg->intf.base[3]); __offset_INTF()
1748 case 4: return (mdp5_cfg->intf.base[4]); __offset_INTF()
1890 case 0: return (mdp5_cfg->ad.base[0]); __offset_AD()
1891 case 1: return (mdp5_cfg->ad.base[1]); __offset_AD()
H A Dmdp5_smp.c128 * if mdp5_cfg->smp.clients[SSPP_VIG0] = N, pipe2client()
134 return mdp5_cfg->smp.clients[pipe] + plane; pipe2client()
H A Dmdp5_kms.h24 #include "mdp5_cfg.h" /* must be included before mdp5.xml.h */
H A Dmdp5_kms.c474 struct mdp5_cfg *config; mdp5_kms_init()
/linux-4.4.14/drivers/gpu/drm/msm/
H A DMakefile33 mdp/mdp5/mdp5_cfg.o \

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