Searched refs:mc_reg_address (Results 1 – 15 of 15) sorted by relevance
956 cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s0); in cypress_populate_mc_reg_addresses()958 cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s1); in cypress_populate_mc_reg_addresses()971 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RAS_TIMING_LP >> 2; in cypress_set_mc_reg_address_table()972 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RAS_TIMING >> 2; in cypress_set_mc_reg_address_table()975 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_CAS_TIMING_LP >> 2; in cypress_set_mc_reg_address_table()976 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_CAS_TIMING >> 2; in cypress_set_mc_reg_address_table()979 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING_LP >> 2; in cypress_set_mc_reg_address_table()980 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING >> 2; in cypress_set_mc_reg_address_table()983 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING2_LP >> 2; in cypress_set_mc_reg_address_table()984 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING2 >> 2; in cypress_set_mc_reg_address_table()[all …]
1924 switch (table->mc_reg_address[i].s1) { in btc_set_mc_special_registers()1927 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; in btc_set_mc_special_registers()1928 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; in btc_set_mc_special_registers()1940 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; in btc_set_mc_special_registers()1941 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; in btc_set_mc_special_registers()1956 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; in btc_set_mc_special_registers()1957 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; in btc_set_mc_special_registers()1984 table->mc_reg_address[i].s0 = in btc_set_s0_mc_reg_index()1985 btc_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? in btc_set_s0_mc_reg_index()1986 address : table->mc_reg_address[i].s1; in btc_set_s0_mc_reg_index()[all …]
39 SMC_Evergreen_MCRegisterAddress mc_reg_address[SMC_EVERGREEN_MC_REGISTER_ARRAY_SIZE]; member
117 SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; member
57 SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE]; member
2717 switch (table->mc_reg_address[i].s1) { in ni_set_mc_special_registers()2722 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; in ni_set_mc_special_registers()2723 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; in ni_set_mc_special_registers()2733 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; in ni_set_mc_special_registers()2734 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; in ni_set_mc_special_registers()2748 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; in ni_set_mc_special_registers()2749 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; in ni_set_mc_special_registers()2840 table->mc_reg_address[i].s0 = in ni_set_s0_mc_reg_index()2841 ni_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? in ni_set_s0_mc_reg_index()2842 address : table->mc_reg_address[i].s1; in ni_set_s0_mc_reg_index()[all …]
86 SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; member
4313 switch(table->mc_reg_address[i].s1 << 2) { in ci_set_mc_special_registers()4316 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; in ci_set_mc_special_registers()4317 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; in ci_set_mc_special_registers()4327 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; in ci_set_mc_special_registers()4328 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; in ci_set_mc_special_registers()4340 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; in ci_set_mc_special_registers()4341 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; in ci_set_mc_special_registers()4353 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; in ci_set_mc_special_registers()4354 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; in ci_set_mc_special_registers()4468 table->mc_reg_address[i].s0 = in ci_set_s0_mc_reg_index()[all …]
5378 switch (table->mc_reg_address[i].s1 << 2) { in si_set_mc_special_registers()5381 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; in si_set_mc_special_registers()5382 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; in si_set_mc_special_registers()5392 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; in si_set_mc_special_registers()5393 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; in si_set_mc_special_registers()5406 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; in si_set_mc_special_registers()5407 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; in si_set_mc_special_registers()5418 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; in si_set_mc_special_registers()5419 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; in si_set_mc_special_registers()5513 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? in si_set_s0_mc_reg_index()[all …]
672 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; member
4011 reg_table->mc_reg_address[i].s1 = in radeon_atom_init_mc_reg_table()4013 reg_table->mc_reg_address[i].pre_reg_data = in radeon_atom_init_mc_reg_table()4029 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { in radeon_atom_init_mc_reg_table()4033 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { in radeon_atom_init_mc_reg_table()
116 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; member
87 SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE]; member
4482 switch(table->mc_reg_address[i].s1) { in ci_set_mc_special_registers()4485 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS; in ci_set_mc_special_registers()4486 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP; in ci_set_mc_special_registers()4496 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS; in ci_set_mc_special_registers()4497 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP; in ci_set_mc_special_registers()4509 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD; in ci_set_mc_special_registers()4510 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD; in ci_set_mc_special_registers()4522 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1; in ci_set_mc_special_registers()4523 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP; in ci_set_mc_special_registers()4637 table->mc_reg_address[i].s0 = in ci_set_s0_mc_reg_index()[all …]
1465 reg_table->mc_reg_address[i].s1 = in amdgpu_atombios_init_mc_reg_table()1467 reg_table->mc_reg_address[i].pre_reg_data = in amdgpu_atombios_init_mc_reg_table()1483 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { in amdgpu_atombios_init_mc_reg_table()1487 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { in amdgpu_atombios_init_mc_reg_table()