Searched refs:max_tile_pipes (Results 1 – 11 of 11) sorted by relevance
355 *value = rdev->config.cik.max_tile_pipes; in radeon_info_ioctl()357 *value = rdev->config.si.max_tile_pipes; in radeon_info_ioctl()359 *value = rdev->config.cayman.max_tile_pipes; in radeon_info_ioctl()361 *value = rdev->config.evergreen.max_tile_pipes; in radeon_info_ioctl()363 *value = rdev->config.rv770.max_tile_pipes; in radeon_info_ioctl()365 *value = rdev->config.r600.max_tile_pipes; in radeon_info_ioctl()
1192 rdev->config.rv770.max_tile_pipes = 8; in rv770_gpu_init()1212 rdev->config.rv770.max_tile_pipes = 4; in rv770_gpu_init()1236 rdev->config.rv770.max_tile_pipes = 2; in rv770_gpu_init()1256 rdev->config.rv770.max_tile_pipes = 4; in rv770_gpu_init()1318 switch (rdev->config.rv770.max_tile_pipes) { in rv770_gpu_init()1333 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; in rv770_gpu_init()
3248 rdev->config.evergreen.max_tile_pipes = 8; in evergreen_gpu_init()3270 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3292 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3315 rdev->config.evergreen.max_tile_pipes = 2; in evergreen_gpu_init()3337 rdev->config.evergreen.max_tile_pipes = 2; in evergreen_gpu_init()3359 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3387 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3409 rdev->config.evergreen.max_tile_pipes = 8; in evergreen_gpu_init()3431 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3453 rdev->config.evergreen.max_tile_pipes = 2; in evergreen_gpu_init()[all …]
2022 unsigned max_tile_pipes; member2044 unsigned max_tile_pipes; member2071 unsigned max_tile_pipes; member2098 unsigned max_tile_pipes; member2136 unsigned max_tile_pipes; member2167 unsigned max_tile_pipes; member
1996 rdev->config.r600.max_tile_pipes = 8; in r600_gpu_init()2012 rdev->config.r600.max_tile_pipes = 2; in r600_gpu_init()2030 rdev->config.r600.max_tile_pipes = 1; in r600_gpu_init()2045 rdev->config.r600.max_tile_pipes = 4; in r600_gpu_init()2076 switch (rdev->config.r600.max_tile_pipes) { in r600_gpu_init()2092 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; in r600_gpu_init()
3102 rdev->config.si.max_tile_pipes = 12; in si_gpu_init()3119 rdev->config.si.max_tile_pipes = 8; in si_gpu_init()3137 rdev->config.si.max_tile_pipes = 4; in si_gpu_init()3154 rdev->config.si.max_tile_pipes = 4; in si_gpu_init()3171 rdev->config.si.max_tile_pipes = 4; in si_gpu_init()3208 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes; in si_gpu_init()
913 rdev->config.cayman.max_tile_pipes = 8; in cayman_gpu_init()937 rdev->config.cayman.max_tile_pipes = 2; in cayman_gpu_init()
2366 num_pipe_configs = rdev->config.cik.max_tile_pipes; in cik_tiling_mode_table_init()3567 rdev->config.cik.max_tile_pipes = 4; in cik_gpu_init()3584 rdev->config.cik.max_tile_pipes = 16; in cik_gpu_init()3601 rdev->config.cik.max_tile_pipes = 4; in cik_gpu_init()3647 rdev->config.cik.max_tile_pipes = 2; in cik_gpu_init()3682 rdev->config.cik.num_tile_pipes = rdev->config.cik.max_tile_pipes; in cik_gpu_init()
977 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()994 adev->gfx.config.max_tile_pipes = 16; in gfx_v8_0_gpu_early_init()1011 adev->gfx.config.max_tile_pipes = 8; in gfx_v8_0_gpu_early_init()1028 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()1083 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()1117 adev->gfx.config.max_tile_pipes = 4; in gfx_v8_0_gpu_early_init()1138 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v8_0_gpu_early_init()
2072 adev->gfx.config.max_tile_pipes = 4; in gfx_v7_0_gpu_init()2089 adev->gfx.config.max_tile_pipes = 16; in gfx_v7_0_gpu_init()2106 adev->gfx.config.max_tile_pipes = 4; in gfx_v7_0_gpu_init()2151 adev->gfx.config.max_tile_pipes = 2; in gfx_v7_0_gpu_init()2174 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v7_0_gpu_init()
1144 unsigned max_tile_pipes; member