Searched refs:lvds (Results 1 - 56 of 56) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/rcar-du/
H A Drcar_du_lvdsenc.c36 static void rcar_lvds_write(struct rcar_du_lvdsenc *lvds, u32 reg, u32 data) rcar_lvds_write() argument
38 iowrite32(data, lvds->mmio + reg); rcar_lvds_write()
41 static int rcar_du_lvdsenc_start(struct rcar_du_lvdsenc *lvds, rcar_du_lvdsenc_start() argument
51 if (lvds->enabled) rcar_du_lvdsenc_start()
54 ret = clk_prepare_enable(lvds->clock); rcar_du_lvdsenc_start()
68 rcar_lvds_write(lvds, LVDPLLCR, pllcr); rcar_du_lvdsenc_start()
77 rcar_lvds_write(lvds, LVDCTRCR, LVDCTRCR_CTR3SEL_ZERO | rcar_du_lvdsenc_start()
81 if (rcar_du_needs(lvds->dev, RCAR_DU_QUIRK_LVDS_LANES)) rcar_du_lvdsenc_start()
88 rcar_lvds_write(lvds, LVDCHCR, lvdhcr); rcar_du_lvdsenc_start()
96 rcar_lvds_write(lvds, LVDCR0, lvdcr0); rcar_du_lvdsenc_start()
99 rcar_lvds_write(lvds, LVDCR1, LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) | rcar_du_lvdsenc_start()
106 rcar_lvds_write(lvds, LVDCR0, lvdcr0); rcar_du_lvdsenc_start()
111 rcar_lvds_write(lvds, LVDCR0, lvdcr0); rcar_du_lvdsenc_start()
113 lvds->enabled = true; rcar_du_lvdsenc_start()
117 static void rcar_du_lvdsenc_stop(struct rcar_du_lvdsenc *lvds) rcar_du_lvdsenc_stop() argument
119 if (!lvds->enabled) rcar_du_lvdsenc_stop()
122 rcar_lvds_write(lvds, LVDCR0, 0); rcar_du_lvdsenc_stop()
123 rcar_lvds_write(lvds, LVDCR1, 0); rcar_du_lvdsenc_stop()
125 clk_disable_unprepare(lvds->clock); rcar_du_lvdsenc_stop()
127 lvds->enabled = false; rcar_du_lvdsenc_stop()
130 int rcar_du_lvdsenc_enable(struct rcar_du_lvdsenc *lvds, struct drm_crtc *crtc, rcar_du_lvdsenc_enable() argument
134 rcar_du_lvdsenc_stop(lvds); rcar_du_lvdsenc_enable()
138 return rcar_du_lvdsenc_start(lvds, rcrtc); rcar_du_lvdsenc_enable()
143 static int rcar_du_lvdsenc_get_resources(struct rcar_du_lvdsenc *lvds, rcar_du_lvdsenc_get_resources() argument
149 sprintf(name, "lvds.%u", lvds->index); rcar_du_lvdsenc_get_resources()
152 lvds->mmio = devm_ioremap_resource(&pdev->dev, mem); rcar_du_lvdsenc_get_resources()
153 if (IS_ERR(lvds->mmio)) rcar_du_lvdsenc_get_resources()
154 return PTR_ERR(lvds->mmio); rcar_du_lvdsenc_get_resources()
156 lvds->clock = devm_clk_get(&pdev->dev, name); rcar_du_lvdsenc_get_resources()
157 if (IS_ERR(lvds->clock)) { rcar_du_lvdsenc_get_resources()
159 return PTR_ERR(lvds->clock); rcar_du_lvdsenc_get_resources()
168 struct rcar_du_lvdsenc *lvds; rcar_du_lvdsenc_init() local
173 lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL); rcar_du_lvdsenc_init()
174 if (lvds == NULL) { rcar_du_lvdsenc_init()
179 lvds->dev = rcdu; rcar_du_lvdsenc_init()
180 lvds->index = i; rcar_du_lvdsenc_init()
181 lvds->input = i ? RCAR_LVDS_INPUT_DU1 : RCAR_LVDS_INPUT_DU0; rcar_du_lvdsenc_init()
182 lvds->enabled = false; rcar_du_lvdsenc_init()
184 ret = rcar_du_lvdsenc_get_resources(lvds, pdev); rcar_du_lvdsenc_init()
188 rcdu->lvds[i] = lvds; rcar_du_lvdsenc_init()
H A Drcar_du_encoder.c49 if (renc->lvds) rcar_du_encoder_disable()
50 rcar_du_lvdsenc_enable(renc->lvds, encoder->crtc, false); rcar_du_encoder_disable()
57 if (renc->lvds) rcar_du_encoder_enable()
58 rcar_du_lvdsenc_enable(renc->lvds, encoder->crtc, true); rcar_du_encoder_enable()
95 if (renc->lvds) rcar_du_encoder_atomic_check()
142 renc->lvds = rcdu->lvds[0]; rcar_du_encoder_init()
146 renc->lvds = rcdu->lvds[1]; rcar_du_encoder_init()
H A Drcar_du_lvdsenc.h31 int rcar_du_lvdsenc_enable(struct rcar_du_lvdsenc *lvds,
38 static inline int rcar_du_lvdsenc_enable(struct rcar_du_lvdsenc *lvds, rcar_du_lvdsenc_enable() argument
H A Drcar_du_hdmienc.c43 if (hdmienc->renc->lvds) rcar_du_hdmienc_disable()
44 rcar_du_lvdsenc_enable(hdmienc->renc->lvds, encoder->crtc, rcar_du_hdmienc_disable()
55 if (hdmienc->renc->lvds) rcar_du_hdmienc_enable()
56 rcar_du_lvdsenc_enable(hdmienc->renc->lvds, encoder->crtc, rcar_du_hdmienc_enable()
77 if (hdmienc->renc->lvds) rcar_du_hdmienc_atomic_check()
H A Drcar_du_encoder.h36 struct rcar_du_lvdsenc *lvds; member in struct:rcar_du_encoder
H A Drcar_du_drv.h93 struct rcar_du_lvdsenc *lvds[RCAR_DU_MAX_LVDS]; member in struct:rcar_du_device
/linux-4.4.14/drivers/gpu/drm/radeon/
H A Dradeon_combios.c1104 struct radeon_encoder_lvds *lvds = NULL; radeon_legacy_get_lvds_info_from_regs() local
1109 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); radeon_legacy_get_lvds_info_from_regs()
1111 if (!lvds) radeon_legacy_get_lvds_info_from_regs()
1118 lvds->panel_pwr_delay = 200; radeon_legacy_get_lvds_info_from_regs()
1119 lvds->panel_vcc_delay = 2000; radeon_legacy_get_lvds_info_from_regs()
1121 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); radeon_legacy_get_lvds_info_from_regs()
1122 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf; radeon_legacy_get_lvds_info_from_regs()
1123 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf; radeon_legacy_get_lvds_info_from_regs()
1126 lvds->native_mode.vdisplay = radeon_legacy_get_lvds_info_from_regs()
1130 lvds->native_mode.vdisplay = radeon_legacy_get_lvds_info_from_regs()
1134 lvds->native_mode.hdisplay = radeon_legacy_get_lvds_info_from_regs()
1138 lvds->native_mode.hdisplay = radeon_legacy_get_lvds_info_from_regs()
1141 if ((lvds->native_mode.hdisplay < 640) || radeon_legacy_get_lvds_info_from_regs()
1142 (lvds->native_mode.vdisplay < 480)) { radeon_legacy_get_lvds_info_from_regs()
1143 lvds->native_mode.hdisplay = 640; radeon_legacy_get_lvds_info_from_regs()
1144 lvds->native_mode.vdisplay = 480; radeon_legacy_get_lvds_info_from_regs()
1150 lvds->use_bios_dividers = false; radeon_legacy_get_lvds_info_from_regs()
1152 lvds->panel_ref_divider = radeon_legacy_get_lvds_info_from_regs()
1154 lvds->panel_post_divider = (ppll_val >> 16) & 0x7; radeon_legacy_get_lvds_info_from_regs()
1155 lvds->panel_fb_divider = ppll_val & 0x7ff; radeon_legacy_get_lvds_info_from_regs()
1157 if ((lvds->panel_ref_divider != 0) && radeon_legacy_get_lvds_info_from_regs()
1158 (lvds->panel_fb_divider > 3)) radeon_legacy_get_lvds_info_from_regs()
1159 lvds->use_bios_dividers = true; radeon_legacy_get_lvds_info_from_regs()
1161 lvds->panel_vcc_delay = 200; radeon_legacy_get_lvds_info_from_regs()
1164 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, radeon_legacy_get_lvds_info_from_regs()
1165 lvds->native_mode.vdisplay); radeon_legacy_get_lvds_info_from_regs()
1167 return lvds; radeon_legacy_get_lvds_info_from_regs()
1179 struct radeon_encoder_lvds *lvds = NULL; radeon_combios_get_lvds_info() local
1184 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); radeon_combios_get_lvds_info()
1186 if (!lvds) radeon_combios_get_lvds_info()
1195 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19); radeon_combios_get_lvds_info()
1196 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b); radeon_combios_get_lvds_info()
1198 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, radeon_combios_get_lvds_info()
1199 lvds->native_mode.vdisplay); radeon_combios_get_lvds_info()
1201 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c); radeon_combios_get_lvds_info()
1202 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000); radeon_combios_get_lvds_info()
1204 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24); radeon_combios_get_lvds_info()
1205 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf; radeon_combios_get_lvds_info()
1206 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf; radeon_combios_get_lvds_info()
1208 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e); radeon_combios_get_lvds_info()
1209 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30); radeon_combios_get_lvds_info()
1210 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31); radeon_combios_get_lvds_info()
1211 if ((lvds->panel_ref_divider != 0) && radeon_combios_get_lvds_info()
1212 (lvds->panel_fb_divider > 3)) radeon_combios_get_lvds_info()
1213 lvds->use_bios_dividers = true; radeon_combios_get_lvds_info()
1216 lvds->lvds_gen_cntl = 0xff00; radeon_combios_get_lvds_info()
1218 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT; radeon_combios_get_lvds_info()
1221 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE; radeon_combios_get_lvds_info()
1225 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM; radeon_combios_get_lvds_info()
1228 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY; radeon_combios_get_lvds_info()
1231 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY; radeon_combios_get_lvds_info()
1238 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW; radeon_combios_get_lvds_info()
1241 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW; radeon_combios_get_lvds_info()
1244 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW; radeon_combios_get_lvds_info()
1247 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL; radeon_combios_get_lvds_info()
1249 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000); radeon_combios_get_lvds_info()
1256 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) && radeon_combios_get_lvds_info()
1257 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) { radeon_combios_get_lvds_info()
1260 if (hss > lvds->native_mode.hdisplay) radeon_combios_get_lvds_info()
1263 lvds->native_mode.htotal = lvds->native_mode.hdisplay + radeon_combios_get_lvds_info()
1265 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + radeon_combios_get_lvds_info()
1267 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + radeon_combios_get_lvds_info()
1270 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + radeon_combios_get_lvds_info()
1272 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + radeon_combios_get_lvds_info()
1274 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + radeon_combios_get_lvds_info()
1277 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10; radeon_combios_get_lvds_info()
1278 lvds->native_mode.flags = 0; radeon_combios_get_lvds_info()
1280 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); radeon_combios_get_lvds_info()
1286 lvds = radeon_legacy_get_lvds_info_from_regs(rdev); radeon_combios_get_lvds_info()
1289 if (lvds) radeon_combios_get_lvds_info()
1290 encoder->native_mode = lvds->native_mode; radeon_combios_get_lvds_info()
1291 return lvds; radeon_combios_get_lvds_info()
H A Dradeon_legacy_encoders.c62 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; radeon_legacy_lvds_update() local
63 panel_pwr_delay = lvds->panel_pwr_delay; radeon_legacy_lvds_update()
64 if (lvds->bl_dev) radeon_legacy_lvds_update()
65 backlight_level = lvds->backlight_level; radeon_legacy_lvds_update()
67 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; radeon_legacy_lvds_update() local
68 panel_pwr_delay = lvds->panel_pwr_delay; radeon_legacy_lvds_update()
69 if (lvds->bl_dev) radeon_legacy_lvds_update()
70 backlight_level = lvds->backlight_level; radeon_legacy_lvds_update()
143 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; radeon_legacy_lvds_dpms() local
144 lvds->dpms_mode = mode; radeon_legacy_lvds_dpms()
146 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; radeon_legacy_lvds_dpms() local
147 lvds->dpms_mode = mode; radeon_legacy_lvds_dpms()
200 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; radeon_legacy_lvds_mode_set() local
201 if (lvds) { radeon_legacy_lvds_mode_set()
202 DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl); radeon_legacy_lvds_mode_set()
203 lvds_gen_cntl = lvds->lvds_gen_cntl; radeon_legacy_lvds_mode_set()
206 lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) | radeon_legacy_lvds_mode_set()
207 (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT)); radeon_legacy_lvds_mode_set()
294 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; radeon_legacy_set_backlight_level() local
295 if (lvds->backlight_level > 0) radeon_legacy_set_backlight_level()
296 dpms_mode = lvds->dpms_mode; radeon_legacy_set_backlight_level()
299 lvds->backlight_level = level; radeon_legacy_set_backlight_level()
301 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; radeon_legacy_set_backlight_level() local
302 if (lvds->backlight_level > 0) radeon_legacy_set_backlight_level()
303 dpms_mode = lvds->dpms_mode; radeon_legacy_set_backlight_level()
306 lvds->backlight_level = level; radeon_legacy_set_backlight_level()
432 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; radeon_legacy_backlight_init() local
433 lvds->bl_dev = bd; radeon_legacy_backlight_init()
435 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; radeon_legacy_backlight_init() local
436 lvds->bl_dev = bd; radeon_legacy_backlight_init()
463 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; radeon_legacy_backlight_exit() local
464 bd = lvds->bl_dev; radeon_legacy_backlight_exit()
465 lvds->bl_dev = NULL; radeon_legacy_backlight_exit()
467 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; radeon_legacy_backlight_exit() local
468 bd = lvds->bl_dev; radeon_legacy_backlight_exit()
469 lvds->bl_dev = NULL; radeon_legacy_backlight_exit()
H A Dradeon_atombios.c1636 struct radeon_encoder_atom_dig *lvds = NULL; radeon_atombios_get_lvds_info() local
1643 lvds = radeon_atombios_get_lvds_info()
1646 if (!lvds) radeon_atombios_get_lvds_info()
1649 lvds->native_mode.clock = radeon_atombios_get_lvds_info()
1651 lvds->native_mode.hdisplay = radeon_atombios_get_lvds_info()
1653 lvds->native_mode.vdisplay = radeon_atombios_get_lvds_info()
1655 lvds->native_mode.htotal = lvds->native_mode.hdisplay + radeon_atombios_get_lvds_info()
1657 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + radeon_atombios_get_lvds_info()
1659 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + radeon_atombios_get_lvds_info()
1661 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + radeon_atombios_get_lvds_info()
1663 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + radeon_atombios_get_lvds_info()
1665 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + radeon_atombios_get_lvds_info()
1667 lvds->panel_pwr_delay = radeon_atombios_get_lvds_info()
1669 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc; radeon_atombios_get_lvds_info()
1673 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC; radeon_atombios_get_lvds_info()
1675 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC; radeon_atombios_get_lvds_info()
1677 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC; radeon_atombios_get_lvds_info()
1679 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE; radeon_atombios_get_lvds_info()
1681 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN; radeon_atombios_get_lvds_info()
1683 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize); radeon_atombios_get_lvds_info()
1684 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize); radeon_atombios_get_lvds_info()
1687 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); radeon_atombios_get_lvds_info()
1689 lvds->lcd_ss_id = lvds_info->info.ucSS_Id; radeon_atombios_get_lvds_info()
1691 encoder->native_mode = lvds->native_mode; radeon_atombios_get_lvds_info()
1694 lvds->linkb = true; radeon_atombios_get_lvds_info()
1696 lvds->linkb = false; radeon_atombios_get_lvds_info()
1749 lvds->native_mode.width_mm = panel_res_record->usHSize; radeon_atombios_get_lvds_info()
1750 lvds->native_mode.height_mm = panel_res_record->usVSize; radeon_atombios_get_lvds_info()
1763 return lvds; radeon_atombios_get_lvds_info()
H A Dradeon_legacy_crtc.c799 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; radeon_set_pll() local
800 if (lvds) { radeon_set_pll()
801 if (lvds->use_bios_dividers) { radeon_set_pll()
802 pll_ref_div = lvds->panel_ref_divider; radeon_set_pll()
803 pll_fb_post_div = (lvds->panel_fb_divider | radeon_set_pll()
804 (lvds->panel_post_divider << 16)); radeon_set_pll()
H A Dradeon_mode.h381 /* legacy lvds */
431 /* atom lvds/edp */
/linux-4.4.14/drivers/gpu/drm/msm/mdp/mdp4/
H A Dmdp4_lcdc_encoder.c46 struct lcdc_platform_data *lcdc_pdata = mdp4_find_pdata("lvds.0"); bs_init()
49 dev_err(dev->dev, "could not find lvds pdata\n"); bs_init()
56 DBG("lvds : bus scale client: %08x", mdp4_lcdc_encoder->bsc); bs_init()
475 reg = devm_regulator_get(dev->dev, "lvds-vccs-3p3v"); mdp4_lcdc_encoder_init()
478 dev_err(dev->dev, "failed to get lvds-vccs-3p3v: %d\n", ret); mdp4_lcdc_encoder_init()
483 reg = devm_regulator_get(dev->dev, "lvds-pll-vdda"); mdp4_lcdc_encoder_init()
486 dev_err(dev->dev, "failed to get lvds-pll-vdda: %d\n", ret); mdp4_lcdc_encoder_init()
491 reg = devm_regulator_get(dev->dev, "lvds-vdda"); mdp4_lcdc_encoder_init()
494 dev_err(dev->dev, "failed to get lvds-vdda: %d\n", ret); mdp4_lcdc_encoder_init()
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
H A Datombios_encoders.c1919 struct amdgpu_encoder_atom_dig *lvds = NULL; amdgpu_atombios_encoder_get_lcd_info() local
1926 lvds = amdgpu_atombios_encoder_get_lcd_info()
1929 if (!lvds) amdgpu_atombios_encoder_get_lcd_info()
1932 lvds->native_mode.clock = amdgpu_atombios_encoder_get_lcd_info()
1934 lvds->native_mode.hdisplay = amdgpu_atombios_encoder_get_lcd_info()
1936 lvds->native_mode.vdisplay = amdgpu_atombios_encoder_get_lcd_info()
1938 lvds->native_mode.htotal = lvds->native_mode.hdisplay + amdgpu_atombios_encoder_get_lcd_info()
1940 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + amdgpu_atombios_encoder_get_lcd_info()
1942 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + amdgpu_atombios_encoder_get_lcd_info()
1944 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + amdgpu_atombios_encoder_get_lcd_info()
1946 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + amdgpu_atombios_encoder_get_lcd_info()
1948 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + amdgpu_atombios_encoder_get_lcd_info()
1950 lvds->panel_pwr_delay = amdgpu_atombios_encoder_get_lcd_info()
1952 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc; amdgpu_atombios_encoder_get_lcd_info()
1956 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC; amdgpu_atombios_encoder_get_lcd_info()
1958 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC; amdgpu_atombios_encoder_get_lcd_info()
1960 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC; amdgpu_atombios_encoder_get_lcd_info()
1962 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE; amdgpu_atombios_encoder_get_lcd_info()
1964 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN; amdgpu_atombios_encoder_get_lcd_info()
1966 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize); amdgpu_atombios_encoder_get_lcd_info()
1967 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize); amdgpu_atombios_encoder_get_lcd_info()
1970 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); amdgpu_atombios_encoder_get_lcd_info()
1972 lvds->lcd_ss_id = lvds_info->info.ucSS_Id; amdgpu_atombios_encoder_get_lcd_info()
1974 encoder->native_mode = lvds->native_mode; amdgpu_atombios_encoder_get_lcd_info()
1977 lvds->linkb = true; amdgpu_atombios_encoder_get_lcd_info()
1979 lvds->linkb = false; amdgpu_atombios_encoder_get_lcd_info()
2032 lvds->native_mode.width_mm = panel_res_record->usHSize; amdgpu_atombios_encoder_get_lcd_info()
2033 lvds->native_mode.height_mm = panel_res_record->usVSize; amdgpu_atombios_encoder_get_lcd_info()
2046 return lvds; amdgpu_atombios_encoder_get_lcd_info()
H A Damdgpu_mode.h419 /* atom lvds/edp */
/linux-4.4.14/drivers/staging/xgifb/
H A Dvb_init.c874 struct XGI21_LVDSCapStruct *lvds; xgifb_read_vbios() local
912 lvds = &xgifb_info->lvds_data; xgifb_read_vbios()
915 lvds->LVDS_Capability = vbios[i] | (vbios[i + 1] << 8); xgifb_read_vbios()
916 lvds->LVDSHT = vbios[i + 2] | (vbios[i + 3] << 8); xgifb_read_vbios()
917 lvds->LVDSVT = vbios[i + 4] | (vbios[i + 5] << 8); xgifb_read_vbios()
918 lvds->LVDSHDE = vbios[i + 6] | (vbios[i + 7] << 8); xgifb_read_vbios()
919 lvds->LVDSVDE = vbios[i + 8] | (vbios[i + 9] << 8); xgifb_read_vbios()
920 lvds->LVDSHFP = vbios[i + 10] | (vbios[i + 11] << 8); xgifb_read_vbios()
921 lvds->LVDSVFP = vbios[i + 12] | (vbios[i + 13] << 8); xgifb_read_vbios()
922 lvds->LVDSHSYNC = vbios[i + 14] | (vbios[i + 15] << 8); xgifb_read_vbios()
923 lvds->LVDSVSYNC = vbios[i + 16] | (vbios[i + 17] << 8); xgifb_read_vbios()
924 lvds->VCLKData1 = vbios[i + 18]; xgifb_read_vbios()
925 lvds->VCLKData2 = vbios[i + 19]; xgifb_read_vbios()
926 lvds->PSC_S1 = vbios[i + 20]; xgifb_read_vbios()
927 lvds->PSC_S2 = vbios[i + 21]; xgifb_read_vbios()
928 lvds->PSC_S3 = vbios[i + 22]; xgifb_read_vbios()
929 lvds->PSC_S4 = vbios[i + 23]; xgifb_read_vbios()
930 lvds->PSC_S5 = vbios[i + 24]; xgifb_read_vbios()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dg84.c38 .outp.internal.lvds = nv50_sor_output_new,
H A Dg94.c38 .outp.internal.lvds = nv50_sor_output_new,
H A Dgk104.c38 .outp.internal.lvds = nv50_sor_output_new,
H A Dgk110.c38 .outp.internal.lvds = nv50_sor_output_new,
H A Dgm107.c38 .outp.internal.lvds = nv50_sor_output_new,
H A Dgm204.c38 .outp.internal.lvds = nv50_sor_output_new,
H A Dgt200.c38 .outp.internal.lvds = nv50_sor_output_new,
H A Dpriv.h20 int (*lvds)(struct nvkm_disp *, int index, struct dcb_output *, member in struct:nvkm_disp_func_outp
H A Dgt215.c38 .outp.internal.lvds = nv50_sor_output_new,
H A Dnv50.h63 int (*lvds)(struct nvkm_disp *, int index, struct dcb_output *, member in struct:nv50_disp_func_outp
H A Drootnv50.c146 nvif_ioctl(object, "disp sor lvds script size %d\n", size); nv50_disp_root_mthd_()
148 nvif_ioctl(object, "disp sor lvds script " nv50_disp_root_mthd_()
H A Dbase.c331 case DCB_OUTPUT_LVDS : ctor = outps->lvds; break; nvkm_disp_ctor()
H A Dnv50.c65 return disp->func->outp.internal.lvds(base, index, dcb, poutp); nv50_disp_outp_internal_lvds_()
135 .outp.internal.lvds = nv50_disp_outp_internal_lvds_,
826 .outp.internal.lvds = nv50_sor_output_new,
H A Dgf119.c521 .outp.internal.lvds = nv50_sor_output_new,
/linux-4.4.14/drivers/gpu/drm/gma500/
H A Dpsb_intel_display.c235 u32 lvds = REG_READ(LVDS); psb_intel_crtc_mode_set() local
237 lvds &= ~LVDS_PIPEB_SELECT; psb_intel_crtc_mode_set()
239 lvds |= LVDS_PIPEB_SELECT; psb_intel_crtc_mode_set()
241 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; psb_intel_crtc_mode_set()
246 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); psb_intel_crtc_mode_set()
248 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; psb_intel_crtc_mode_set()
255 REG_WRITE(LVDS, lvds); psb_intel_crtc_mode_set()
H A Dmdfld_output.c32 #include "tc35876x-dsi-lvds.h"
H A Dpsb_intel_lvds.c163 dev_info(dev->dev, "Backlight lvds set brightness %08x\n", psb_lvds_pwm_set_brightness()
694 u32 lvds; psb_intel_lvds_init() local
806 lvds = REG_READ(LVDS); psb_intel_lvds_init()
807 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; psb_intel_lvds_init()
810 if (crtc && (lvds & LVDS_PORT_EN)) { psb_intel_lvds_init()
822 dev_err(dev->dev, "Found no modes on the lvds, ignoring the LVDS\n"); psb_intel_lvds_init()
H A Dcdv_intel_lvds.c619 u32 lvds; cdv_intel_lvds_init() local
741 lvds = REG_READ(LVDS); cdv_intel_lvds_init()
742 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; cdv_intel_lvds_init()
745 if (crtc && (lvds & LVDS_PORT_EN)) { cdv_intel_lvds_init()
758 ("Found no modes on the lvds, ignoring the LVDS\n"); cdv_intel_lvds_init()
H A Dcdv_intel_display.c525 /* Is pipe b lvds ? */ cdv_update_wm()
749 u32 lvds = REG_READ(LVDS); cdv_intel_crtc_mode_set() local
751 lvds |= cdv_intel_crtc_mode_set()
759 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; cdv_intel_crtc_mode_set()
761 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); cdv_intel_crtc_mode_set()
768 REG_WRITE(LVDS, lvds); cdv_intel_crtc_mode_set()
H A Doaktrail.h202 u8 pt; /* panel type, 4 bit field, 0=lvds, 1=mipi */
H A Dgma_display.c661 /* lvds has its own version of prepare see psb_intel_lvds_prepare */ gma_encoder_prepare()
669 /* lvds has its own version of commit see psb_intel_lvds_commit */ gma_encoder_commit()
H A Dmdfld_device.c24 #include "tc35876x-dsi-lvds.h"
H A Doaktrail_lvds.c405 dev_err(dev->dev, "Found no modes on the lvds, ignoring the LVDS\n"); oaktrail_lvds_init()
H A Dmdfld_dsi_output.c34 #include "tc35876x-dsi-lvds.h"
H A Dtc35876x-dsi-lvds.c28 #include "tc35876x-dsi-lvds.h"
H A Dmdfld_dsi_dpi.c32 #include "tc35876x-dsi-lvds.h"
H A Dpsb_intel_sdvo.c2548 /* In default case sdvo lvds is false */ psb_intel_sdvo_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/
H A Dnv50_display.c1940 struct nv50_disp_sor_lvds_script_v0 lvds; nv50_sor_mode_set() member in struct:__anon4394
1941 } lvds = { nv50_sor_mode_set() local
1979 lvds.lvds.script |= 0x0100; nv50_sor_mode_set()
1981 lvds.lvds.script |= 0x0200; nv50_sor_mode_set()
1985 lvds.lvds.script |= 0x0100; nv50_sor_mode_set()
1988 lvds.lvds.script |= 0x0100; nv50_sor_mode_set()
1991 if (lvds.lvds.script & 0x0100) { nv50_sor_mode_set()
1993 lvds.lvds.script |= 0x0200; nv50_sor_mode_set()
1996 lvds.lvds.script |= 0x0200; nv50_sor_mode_set()
2000 lvds.lvds.script |= 0x0200; nv50_sor_mode_set()
2003 nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds)); nv50_sor_mode_set()
H A Dnouveau_bios.c546 * It seems the old style lvds script pointer is reused nouveau_bios_parse_lvds_table()
1035 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds)); parse_bit_structure()
1148 /* length not exact: this is long enough to get lvds members */ parse_bmp_structure()
1208 * Never observed in use with lvds scripts, but is reused for parse_bmp_structure()
/linux-4.4.14/drivers/pinctrl/berlin/
H A Dberlin-bg2q.c32 BERLIN_PINCTRL_FUNCTION(0x3, "lvds")),
36 BERLIN_PINCTRL_FUNCTION(0x3, "lvds")),
165 BERLIN_PINCTRL_FUNCTION(0x1, "lvds"),
197 BERLIN_PINCTRL_FUNCTION(0x4, "lvds")),
/linux-4.4.14/drivers/gpu/drm/i915/
H A Dintel_lvds.c184 * special lvds dither control bit on pch-split platforms, dithering is intel_pre_enable_lvds()
828 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); intel_dual_link_lvds_callback()
943 u32 lvds; intel_lvds_init() local
970 lvds = I915_READ(lvds_reg); intel_lvds_init()
973 if ((lvds & LVDS_DETECTED) == 0) intel_lvds_init()
983 if ((lvds & LVDS_PORT_EN) == 0) { intel_lvds_init()
1141 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; intel_lvds_init()
1144 if (crtc && (lvds & LVDS_PORT_EN)) { intel_lvds_init()
1164 DRM_DEBUG_KMS("detected %s-link lvds configuration\n", intel_lvds_init()
H A Dintel_sdvo.c1230 /* lvds has a special fixed output timing. */ intel_sdvo_pre_enable()
2987 /* In default case sdvo lvds is false */ intel_sdvo_init()
H A Dintel_display.c10597 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); i9xx_crtc_clock_get() local
10598 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); i9xx_crtc_clock_get()
10604 if (lvds & LVDS_CLKB_POWER_UP) i9xx_crtc_clock_get()
12050 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", intel_dump_pipe_config()
13951 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port intel_crtc_init()
14707 DRM_INFO("applying lvds SSC disable quirk\n"); quirk_ssc_force_disable()
/linux-4.4.14/drivers/video/fbdev/intelfb/
H A Dintelfb.h206 u32 lvds; member in struct:intelfb_hwstate
H A Dintelfbhw.c580 hw->lvds = INREG(LVDS); intelfbhw_read_hw_state()
665 int lvds) calc_vclock()
808 printk(" LVDS: 0x%08x\n", hw->lvds); intelfbhw_print_hw_state()
664 calc_vclock(int index, int m1, int m2, int n, int p1, int p2, int lvds) calc_vclock() argument
/linux-4.4.14/drivers/gpu/drm/imx/
H A Dimx-drm-core.c516 if (of_node_cmp(np->name, "lvds-channel") == 0) { compare_of()
/linux-4.4.14/drivers/gpu/drm/nouveau/dispnv04/
H A Dcrtc.c522 /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */ nv_crtc_mode_set_regs()
538 * bit6: lvds, head A nv_crtc_mode_set_regs()
H A Ddfp.c523 NV_DEBUG(drm, "Setting dpms mode %d on lvds encoder (output %d)\n", nv04_lvds_dpms()
/linux-4.4.14/drivers/video/fbdev/
H A Dfsl-diu-fb.c457 * Takes the name of a monitor port ("dvi", "lvds", or "dlvds") and returns
476 else if (strncmp(s, "lvds", 4) == 0) fsl_diu_name_to_port()
2010 "(\"dvi\", \"lvds\", or \"dlvds\") if supported by the platform");
/linux-4.4.14/drivers/video/fbdev/via/
H A Dhw.c1722 /*If viafb_LCD2_ON, on cx700, internal lvds's information set_display_channel()
/linux-4.4.14/drivers/video/fbdev/sis/
H A Dinit301.c2309 /* Special Timing: 848x480 and 856x480 parallel lvds panels */ SiS_GetVCLK2Ptr()
5379 /* is lvds if really LVDS, or 301B-DH with external LVDS transmitter */ SiS_SetGroup1_LVDS()

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