Searched refs:lcdc (Results 1 - 21 of 21) sorted by relevance

/linux-4.4.14/drivers/video/fbdev/omap/
H A Dlcdc.c33 #include <mach/lcdc.h>
40 #include "lcdc.h"
42 #define MODULE_NAME "lcdc"
80 } lcdc; variable in typeref:struct:omap_lcd_controller
84 lcdc.irq_mask |= mask; enable_irqs()
89 lcdc.irq_mask &= ~mask; disable_irqs()
120 l |= lcdc.irq_mask | OMAP_LCDC_IRQ_DONE; /* enabled IRQs */ enable_controller()
142 init_completion(&lcdc.last_frame_complete); disable_controller()
144 if (!wait_for_completion_timeout(&lcdc.last_frame_complete, disable_controller()
146 dev_err(lcdc.fbdev->dev, "timeout waiting for FRAME DONE\n"); disable_controller()
157 dev_err(lcdc.fbdev->dev, reset_controller()
166 dev_err(lcdc.fbdev->dev, reset_controller()
173 * in lcdc.fbdev and fbdev->var.
184 struct omapfb_plane_struct *plane = lcdc.fbdev->fb_info[0]->par; setup_lcd_dma()
185 struct fb_var_screeninfo *var = &lcdc.fbdev->fb_info[0]->var; setup_lcd_dma()
189 src = lcdc.vram_phys + lcdc.frame_offset; setup_lcd_dma()
194 lcdc.color_mode == OMAPFB_COLOR_YUV420 || setup_lcd_dma()
195 (lcdc.xres & 1)) setup_lcd_dma()
199 xelem = lcdc.xres * lcdc.bpp / 8 / esize; setup_lcd_dma()
200 yelem = lcdc.yres; setup_lcd_dma()
209 xelem = lcdc.yres * lcdc.bpp / 16; setup_lcd_dma()
210 yelem = lcdc.xres; setup_lcd_dma()
217 dev_dbg(lcdc.fbdev->dev, setup_lcd_dma()
223 int bpp = lcdc.bpp; setup_lcd_dma()
229 if (lcdc.color_mode == OMAPFB_COLOR_YUV420) setup_lcd_dma()
233 lcdc.screen_width * bpp / 8 / esize); setup_lcd_dma()
261 complete(&lcdc.last_frame_complete); lcdc_irq_handler()
265 complete(&lcdc.palette_load_complete); lcdc_irq_handler()
296 struct fb_var_screeninfo *var = &lcdc.fbdev->fb_info[0]->var; omap_lcdc_setup_plane()
297 struct lcd_panel *panel = lcdc.fbdev->panel; omap_lcdc_setup_plane()
310 dev_dbg(lcdc.fbdev->dev, omap_lcdc_setup_plane()
317 lcdc.frame_offset = offset; omap_lcdc_setup_plane()
318 lcdc.xres = width; omap_lcdc_setup_plane()
319 lcdc.yres = height; omap_lcdc_setup_plane()
320 lcdc.screen_width = screen_width; omap_lcdc_setup_plane()
321 lcdc.color_mode = color_mode; omap_lcdc_setup_plane()
325 lcdc.bpp = 8; omap_lcdc_setup_plane()
326 lcdc.palette_code = 0x3000; omap_lcdc_setup_plane()
327 lcdc.palette_size = 512; omap_lcdc_setup_plane()
330 lcdc.bpp = 16; omap_lcdc_setup_plane()
331 lcdc.palette_code = 0x4000; omap_lcdc_setup_plane()
332 lcdc.palette_size = 32; omap_lcdc_setup_plane()
335 lcdc.bpp = 16; omap_lcdc_setup_plane()
336 lcdc.palette_code = 0x4000; omap_lcdc_setup_plane()
337 lcdc.palette_size = 32; omap_lcdc_setup_plane()
340 if (lcdc.ext_mode) { omap_lcdc_setup_plane()
341 lcdc.bpp = 12; omap_lcdc_setup_plane()
346 if (lcdc.ext_mode) { omap_lcdc_setup_plane()
347 lcdc.bpp = 16; omap_lcdc_setup_plane()
358 dev_dbg(lcdc.fbdev->dev, "invalid color mode %d\n", color_mode); omap_lcdc_setup_plane()
363 if (lcdc.ext_mode) { omap_lcdc_setup_plane()
368 if (lcdc.update_mode == OMAPFB_AUTO_UPDATE) { omap_lcdc_setup_plane()
380 dev_dbg(lcdc.fbdev->dev, omap_lcdc_enable_plane()
382 plane, enable, lcdc.update_mode, lcdc.ext_mode); omap_lcdc_enable_plane()
398 palette = (u16 *)lcdc.palette_virt; load_palette()
401 *(u16 *)palette |= lcdc.palette_code; load_palette()
403 omap_set_lcd_dma_b1(lcdc.palette_phys, load_palette()
404 lcdc.palette_size / 4 + 1, 1, OMAP_DMA_DATA_TYPE_S32); load_palette()
409 init_completion(&lcdc.palette_load_complete); load_palette()
413 if (!wait_for_completion_timeout(&lcdc.palette_load_complete, load_palette()
415 dev_err(lcdc.fbdev->dev, "timeout waiting for FRAME DONE\n"); load_palette()
420 omap_set_lcd_dma_single_transfer(lcdc.ext_mode); load_palette()
429 if (lcdc.color_mode != OMAPFB_COLOR_CLUT_8BPP || regno > 255) omap_lcdc_setcolreg()
432 palette = (u16 *)lcdc.palette_virt; omap_lcdc_setcolreg()
455 lck = clk_get_rate(lcdc.lcd_ck); calc_ck_div()
464 dev_warn(lcdc.fbdev->dev, "pixclock %d kHz too low.\n", calc_ck_div()
472 struct lcd_panel *panel = lcdc.fbdev->panel; setup_regs()
508 lck = clk_get_rate(lcdc.lcd_ck); setup_regs()
513 dev_warn(lcdc.fbdev->dev, setup_regs()
538 if (mode != lcdc.update_mode) { omap_lcdc_set_update_mode()
551 lcdc.update_mode = mode; omap_lcdc_set_update_mode()
556 lcdc.update_mode = mode; omap_lcdc_set_update_mode()
568 return lcdc.update_mode; omap_lcdc_get_update_mode()
591 if (lcdc.dma_callback) omap_lcdc_set_dma_callback()
594 lcdc.dma_callback = callback; omap_lcdc_set_dma_callback()
595 lcdc.dma_callback_data = data; omap_lcdc_set_dma_callback()
603 lcdc.dma_callback = NULL; omap_lcdc_free_dma_callback()
609 if (lcdc.dma_callback) lcdc_dma_handler()
610 lcdc.dma_callback(lcdc.dma_callback_data); lcdc_dma_handler()
615 lcdc.palette_virt = dma_alloc_writecombine(lcdc.fbdev->dev, alloc_palette_ram()
616 MAX_PALETTE_SIZE, &lcdc.palette_phys, GFP_KERNEL); alloc_palette_ram()
617 if (lcdc.palette_virt == NULL) { alloc_palette_ram()
618 dev_err(lcdc.fbdev->dev, "failed to alloc palette memory\n"); alloc_palette_ram()
621 memset(lcdc.palette_virt, 0, MAX_PALETTE_SIZE); alloc_palette_ram()
628 dma_free_writecombine(lcdc.fbdev->dev, MAX_PALETTE_SIZE, free_palette_ram()
629 lcdc.palette_virt, lcdc.palette_phys); free_palette_ram()
636 struct lcd_panel *panel = lcdc.fbdev->panel; alloc_fbmem()
644 lcdc.vram_size = frame_size; alloc_fbmem()
645 lcdc.vram_virt = dma_alloc_writecombine(lcdc.fbdev->dev, alloc_fbmem()
646 lcdc.vram_size, &lcdc.vram_phys, GFP_KERNEL); alloc_fbmem()
647 if (lcdc.vram_virt == NULL) { alloc_fbmem()
648 dev_err(lcdc.fbdev->dev, "unable to allocate FB DMA memory\n"); alloc_fbmem()
652 region->paddr = lcdc.vram_phys; alloc_fbmem()
653 region->vaddr = lcdc.vram_virt; alloc_fbmem()
656 memset(lcdc.vram_virt, 0, lcdc.vram_size); alloc_fbmem()
663 dma_free_writecombine(lcdc.fbdev->dev, lcdc.vram_size, free_fbmem()
664 lcdc.vram_virt, lcdc.vram_phys); free_fbmem()
670 dev_err(lcdc.fbdev->dev, "no memory regions defined\n"); setup_fbmem()
675 dev_err(lcdc.fbdev->dev, "only one plane is supported\n"); setup_fbmem()
690 lcdc.irq_mask = 0; omap_lcdc_init()
692 lcdc.fbdev = fbdev; omap_lcdc_init()
693 lcdc.ext_mode = ext_mode; omap_lcdc_init()
701 lcdc.lcd_ck = clk_get(fbdev->dev, "lcd_ck"); omap_lcdc_init()
702 if (IS_ERR(lcdc.lcd_ck)) { omap_lcdc_init()
704 r = PTR_ERR(lcdc.lcd_ck); omap_lcdc_init()
722 r = clk_set_rate(lcdc.lcd_ck, rate); omap_lcdc_init()
727 clk_enable(lcdc.lcd_ck); omap_lcdc_init()
760 free_irq(OMAP_LCDC_IRQ, lcdc.fbdev); omap_lcdc_init()
762 clk_disable(lcdc.lcd_ck); omap_lcdc_init()
764 clk_put(lcdc.lcd_ck); omap_lcdc_init()
771 if (!lcdc.ext_mode) omap_lcdc_cleanup()
775 free_irq(OMAP_LCDC_IRQ, lcdc.fbdev); omap_lcdc_cleanup()
776 clk_disable(lcdc.lcd_ck); omap_lcdc_cleanup()
777 clk_put(lcdc.lcd_ck); omap_lcdc_cleanup()
H A DMakefile7 objs-yy := omapfb_main.o lcdc.o
H A Dsossi.c31 #include "lcdc.h"
H A Domapfb_main.c38 #include "lcdc.h"
/linux-4.4.14/drivers/pinctrl/qcom/
H A Dpinctrl-msm8660.c736 FUNCTION(lcdc),
755 PINGROUP(0, lcdc, dsub, _, _, _, _, _),
756 PINGROUP(1, lcdc, dsub, _, _, _, _, _),
757 PINGROUP(2, lcdc, dsub, _, _, _, _, _),
758 PINGROUP(3, lcdc, dsub, _, _, _, _, _),
759 PINGROUP(4, lcdc, dsub, _, _, _, _, _),
760 PINGROUP(5, lcdc, dsub, _, _, _, _, _),
761 PINGROUP(6, lcdc, dsub, _, _, _, _, _),
762 PINGROUP(7, lcdc, dsub, _, _, _, _, _),
763 PINGROUP(8, lcdc, dsub, _, _, _, _, _),
764 PINGROUP(9, lcdc, dsub, _, _, _, _, _),
765 PINGROUP(10, lcdc, dsub, _, _, _, _, _),
766 PINGROUP(11, lcdc, dsub, _, _, _, _, _),
767 PINGROUP(12, lcdc, dsub, _, _, _, _, _),
768 PINGROUP(13, lcdc, dsub, _, _, _, _, _),
769 PINGROUP(14, lcdc, dsub, _, _, _, _, _),
770 PINGROUP(15, lcdc, dsub, _, _, _, _, _),
771 PINGROUP(16, lcdc, dsub, _, _, _, _, _),
772 PINGROUP(17, lcdc, dsub, _, _, _, _, _),
773 PINGROUP(18, lcdc, dsub, _, _, _, _, _),
774 PINGROUP(19, lcdc, dsub, _, _, _, _, _),
775 PINGROUP(20, lcdc, dsub, _, _, _, _, _),
776 PINGROUP(21, lcdc, dsub, _, _, _, _, _),
777 PINGROUP(22, lcdc, dsub, _, _, _, _, _),
778 PINGROUP(23, lcdc, dsub, _, _, _, _, _),
779 PINGROUP(24, lcdc, dsub, _, _, _, _, _),
780 PINGROUP(25, lcdc, dsub, _, _, _, _, _),
781 PINGROUP(26, lcdc, dsub, _, _, _, _, _),
782 PINGROUP(27, lcdc, dsub, _, _, _, _, _),
/linux-4.4.14/drivers/gpu/drm/tilcdc/
H A Dtilcdc_slave_compat.c200 struct device_node *slave = NULL, *lcdc = NULL; tilcdc_convert_slave_node() local
212 lcdc = of_find_matching_node(NULL, tilcdc_of_match); tilcdc_convert_slave_node()
215 if (!slave || !of_device_is_available(lcdc)) tilcdc_convert_slave_node()
243 if (!strncmp("lcdc", (char *)prop->value, prop->length)) for_each_child_of_node()
244 if (tilcdc_prop_str_update(prop, lcdc->full_name, &kft)) for_each_child_of_node()
260 of_node_put(lcdc);
/linux-4.4.14/arch/arm/mach-omap1/include/mach/
H A Dlcdc.h2 * arch/arm/mach-omap1/include/mach/lcdc.h
4 * Extracted from drivers/video/omap/lcdc.c
/linux-4.4.14/drivers/video/fbdev/
H A Dsh_mobile_lcdcfb.h43 struct sh_mobile_lcdc_chan *lcdc; member in struct:sh_mobile_lcdc_entity
56 struct sh_mobile_lcdc_priv *lcdc; member in struct:sh_mobile_lcdc_chan
H A Dsh_mobile_lcdcfb.c293 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]); lcdc_write_chan()
295 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] + lcdc_write_chan()
302 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] + lcdc_write_chan_mirror()
309 return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]); lcdc_read_chan()
315 iowrite32(data, ovl->channel->lcdc->base + reg); lcdc_write_overlay()
316 iowrite32(data, ovl->channel->lcdc->base + reg + SIDE_B_OFFSET); lcdc_write_overlay()
409 lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT); lcdc_sys_write_index()
410 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0); lcdc_sys_write_index()
411 lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA | lcdc_sys_write_index()
413 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0); lcdc_sys_write_index()
420 lcdc_write(ch->lcdc, _LDDWD0R, data | LDDWDxR_WDACT | LDDWDxR_RSW); lcdc_sys_write_data()
421 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0); lcdc_sys_write_data()
422 lcdc_write(ch->lcdc, _LDDWAR, LDDWAR_WA | lcdc_sys_write_data()
424 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0); lcdc_sys_write_data()
431 lcdc_write(ch->lcdc, _LDDRDR, LDDRDR_RSR); lcdc_sys_read_data()
432 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0); lcdc_sys_read_data()
433 lcdc_write(ch->lcdc, _LDDRAR, LDDRAR_RA | lcdc_sys_read_data()
436 lcdc_wait_bit(ch->lcdc, _LDSR, LDSR_AS, 0); lcdc_sys_read_data()
438 return lcdc_read(ch->lcdc, _LDDRDR) & LDDRDR_DRD_MASK; lcdc_sys_read_data()
470 sh_mobile_lcdc_clk_on(ch->lcdc); sh_mobile_lcdc_deferred_io()
491 dma_map_sg(ch->lcdc->dev, ch->sglist, nr_pages, DMA_TO_DEVICE); sh_mobile_lcdc_deferred_io()
495 dma_unmap_sg(ch->lcdc->dev, ch->sglist, nr_pages, sh_mobile_lcdc_deferred_io()
773 ldintr = lcdc_read(ch->lcdc, _LDINTR); sh_mobile_lcdc_wait_for_vsync()
775 lcdc_write(ch->lcdc, _LDINTR, ldintr); sh_mobile_lcdc_wait_for_vsync()
791 /* start or stop the lcdc */ sh_mobile_lcdc_start_stop()
871 lcdc_write(ovl->channel->lcdc, LDBCR, LDBCR_UPC(ovl->index)); sh_mobile_lcdc_overlay_setup()
873 lcdc_write(ovl->channel->lcdc, LDBCR, sh_mobile_lcdc_overlay_setup()
936 lcdc_write(ovl->channel->lcdc, LDBCR, LDBCR_UPC(ovl->index)); sh_mobile_lcdc_overlay_setup()
952 lcdc_write(ovl->channel->lcdc, LDBCR, sh_mobile_lcdc_overlay_setup()
1235 /* stop the lcdc */ sh_mobile_lcdc_stop()
1543 lcdc_write(ovl->channel->lcdc, LDBCR, LDBCR_UPC(ovl->index)); sh_mobile_lcdc_overlay_pan()
1548 lcdc_write(ovl->channel->lcdc, LDBCR, sh_mobile_lcdc_overlay_pan()
1625 return dma_mmap_coherent(ovl->channel->lcdc->dev, vma, ovl->fb_mem, sh_mobile_lcdc_overlay_mmap()
1658 struct sh_mobile_lcdc_priv *lcdc = ovl->channel->lcdc; sh_mobile_lcdc_overlay_fb_register() local
1670 dev_info(lcdc->dev, "registered %s/overlay %u as %dx%d %dbpp.\n", sh_mobile_lcdc_overlay_fb_register()
1671 dev_name(lcdc->dev), ovl->index, info->var.xres, sh_mobile_lcdc_overlay_fb_register()
1697 struct sh_mobile_lcdc_priv *priv = ovl->channel->lcdc; sh_mobile_lcdc_overlay_fb_init()
1824 struct sh_mobile_lcdc_priv *priv = ch->lcdc; sh_mobile_lcdc_pan()
1869 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS); sh_mobile_lcdc_pan()
1871 lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_MRS); sh_mobile_lcdc_pan()
1977 struct sh_mobile_lcdc_priv *p = ch->lcdc; sh_mobile_lcdc_check_var()
2034 sh_mobile_lcdc_stop(ch->lcdc); sh_mobile_lcdc_set_par()
2049 ret = sh_mobile_lcdc_start(ch->lcdc); sh_mobile_lcdc_set_par()
2077 struct sh_mobile_lcdc_priv *p = ch->lcdc; sh_mobile_lcdc_blank()
2114 return dma_mmap_coherent(ch->lcdc->dev, vma, ch->fb_mem, sh_mobile_lcdc_mmap()
2153 dev_err(ch->lcdc->dev, "cannot allocate sglist\n"); sh_mobile_lcdc_channel_fb_register()
2164 dev_info(ch->lcdc->dev, "registered %s/%s as %dx%d %dbpp.\n", sh_mobile_lcdc_channel_fb_register()
2165 dev_name(ch->lcdc->dev), (ch->cfg->chan == LCDC_CHAN_MAINLCD) ? sh_mobile_lcdc_channel_fb_register()
2171 sh_mobile_lcdc_clk_off(ch->lcdc); sh_mobile_lcdc_channel_fb_register()
2195 struct sh_mobile_lcdc_priv *priv = ch->lcdc; sh_mobile_lcdc_channel_fb_init()
2395 if (&ch->lcdc->notifier != nb) sh_mobile_lcdc_notify()
2404 sh_mobile_lcdc_stop(ch->lcdc); sh_mobile_lcdc_notify()
2412 sh_mobile_lcdc_start(ch->lcdc); sh_mobile_lcdc_notify()
2468 ch->tx_dev->lcdc = NULL; sh_mobile_lcdc_remove()
2545 struct device *dev = ovl->channel->lcdc->dev; sh_mobile_lcdc_overlay_init()
2601 struct device *dev = ch->lcdc->dev; sh_mobile_lcdc_channel_init()
2692 ch->tx_dev->lcdc = ch; sh_mobile_lcdc_channel_init()
2745 ch->lcdc = priv; sh_mobile_lcdc_probe()
H A Dsh7760fb.c480 "sh7760-lcdc", &par->vsync); sh7760fb_probe()
515 strcpy(info->fix.id, "sh7760-lcdc"); sh7760fb_probe()
580 .name = "sh7760-lcdc",
H A Datmel_lcdfb.c984 { .compatible = "atmel,at91sam9261-lcdc" , .data = &at91sam9261_config, },
985 { .compatible = "atmel,at91sam9263-lcdc" , .data = &at91sam9263_config, },
986 { .compatible = "atmel,at91sam9g10-lcdc" , .data = &at91sam9g10_config, },
987 { .compatible = "atmel,at91sam9g45-lcdc" , .data = &at91sam9g45_config, },
988 { .compatible = "atmel,at91sam9g45es-lcdc" , .data = &at91sam9g45es_config, },
989 { .compatible = "atmel,at91sam9rl-lcdc" , .data = &at91sam9rl_config, },
990 { .compatible = "atmel,at32ap-lcdc" , .data = &at32ap_config, },
H A Dsh_mobile_hdmi.c847 struct sh_mobile_lcdc_chan *ch = hdmi->entity.lcdc; sh_hdmi_read_edid()
1179 struct sh_mobile_lcdc_chan *ch = hdmi->entity.lcdc; sh_hdmi_edid_work_fn()
/linux-4.4.14/arch/arm/mach-omap2/
H A Domap_hwmod_33xx_data.c258 /* lcdc */
268 .name = "lcdc",
273 .name = "lcdc",
/linux-4.4.14/arch/sh/boards/mach-sh7763rdp/
H A Dsetup.c143 .name = "sh7760-lcdc",
/linux-4.4.14/drivers/gpu/drm/rockchip/
H A Drockchip_drm_vop.h164 * display output interface supported by rockchip lcdc
/linux-4.4.14/arch/sh/boards/mach-se/7724/
H A Dsetup.c58 * When you use 1280 x 720 lcdc output,
59 * you should change OSC6 lcdc clock from 25.175MHz to 74.25MHz,
/linux-4.4.14/drivers/power/avs/
H A Drockchip-io-domain.c213 "lcdc", /* LCDC_VDD */
/linux-4.4.14/arch/arm/mach-omap1/
H A Dlcd_dma.c33 #include <mach/lcdc.h>
/linux-4.4.14/arch/arm/mach-davinci/
H A Dda830.c273 .name = "lcdc",
H A Dda850.c310 .name = "lcdc",
/linux-4.4.14/arch/avr32/mach-at32ap/
H A Dat32ap700x.c1495 /* Default to "full" lcdc control signals and 24bit */ at32_add_device_lcdc()

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