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Searched refs:lanes (Results 1 – 105 of 105) sorted by relevance

/linux-4.4.14/drivers/staging/media/omap4iss/
Diss_csiphy.c40 reg |= (phy->lanes.data[i].pol ? in csiphy_lanes_config()
42 reg |= (phy->lanes.data[i].pos << in csiphy_lanes_config()
48 reg |= phy->lanes.clk.pol ? CSI2_COMPLEXIO_CFG_CLOCK_POL : 0; in csiphy_lanes_config()
49 reg |= phy->lanes.clk.pos << CSI2_COMPLEXIO_CFG_CLOCK_POSITION_SHIFT; in csiphy_lanes_config()
127 struct iss_csiphy_lanes_cfg *lanes; in omap4iss_csiphy_config() local
132 lanes = &subdevs->bus.csi2.lanecfg; in omap4iss_csiphy_config()
179 if (lanes->data[i].pos == 0) in omap4iss_csiphy_config()
182 if (lanes->data[i].pol > 1 || in omap4iss_csiphy_config()
183 lanes->data[i].pos > (csi2->phy->max_data_lanes + 1)) in omap4iss_csiphy_config()
186 if (used_lanes & (1 << lanes->data[i].pos)) in omap4iss_csiphy_config()
[all …]
Diss_csiphy.h41 struct iss_csiphy_lanes_cfg lanes; member
/linux-4.4.14/drivers/media/platform/omap3isp/
Dispcsiphy.c170 struct isp_csiphy_lanes_cfg *lanes; in omap3isp_csiphy_config() local
185 lanes = &buscfg->bus.ccp2.lanecfg; in omap3isp_csiphy_config()
187 lanes = &buscfg->bus.csi2.lanecfg; in omap3isp_csiphy_config()
191 if (lanes->data[i].pol > 1 || lanes->data[i].pos > 3) in omap3isp_csiphy_config()
194 if (used_lanes & (1 << lanes->data[i].pos)) in omap3isp_csiphy_config()
197 used_lanes |= 1 << lanes->data[i].pos; in omap3isp_csiphy_config()
200 if (lanes->clk.pol > 1 || lanes->clk.pos > 3) in omap3isp_csiphy_config()
203 if (lanes->clk.pos == 0 || used_lanes & (1 << lanes->clk.pos)) in omap3isp_csiphy_config()
249 reg |= (lanes->data[i].pol << in omap3isp_csiphy_config()
251 reg |= (lanes->data[i].pos << in omap3isp_csiphy_config()
[all …]
/linux-4.4.14/drivers/video/fbdev/omap2/dss/
Dhdmi_common.c19 u32 lanes[8]; in hdmi_parse_lanes_of() local
21 if (len / sizeof(u32) != ARRAY_SIZE(lanes)) { in hdmi_parse_lanes_of()
26 r = of_property_read_u32_array(ep, "lanes", lanes, in hdmi_parse_lanes_of()
27 ARRAY_SIZE(lanes)); in hdmi_parse_lanes_of()
33 r = hdmi_phy_parse_lanes(phy, lanes); in hdmi_parse_lanes_of()
Dhdmi_phy.c42 int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes) in hdmi_phy_parse_lanes() argument
50 dx = lanes[i]; in hdmi_phy_parse_lanes()
51 dy = lanes[i + 1]; in hdmi_phy_parse_lanes()
Ddsi.c380 struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; member
1841 if (dsi->lanes[t].function == functions[i]) in dsi_set_lane_config()
1848 polarity = dsi->lanes[t].polarity; in dsi_set_lane_config()
1973 unsigned p = dsi->lanes[i].polarity; in dsi_cio_enable_lane_override()
2026 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED; in dsi_cio_wait_tx_clk_esc_reset()
2067 if (dsi->lanes[i].function != DSI_LANE_UNUSED) in dsi_get_lane_mask()
2129 if (dsi->lanes[i].function == DSI_LANE_UNUSED) in dsi_cio_init()
3179 if (dsi->lanes[i].function == DSI_LANE_UNUSED) in dsi_enter_ulps()
3765 struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; in dsi_configure_pins() local
3785 lanes[i].function = DSI_LANE_UNUSED; in dsi_configure_pins()
[all …]
Dhdmi.h320 int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes);
/linux-4.4.14/arch/arm/boot/dts/
Domap3-n9.dts32 clock-lanes = <0>;
33 data-lanes = <1 2>;
48 clock-lanes = <2>;
49 data-lanes = <1 3>;
Domap3-n950.dts32 clock-lanes = <0>;
33 data-lanes = <1 2>;
48 clock-lanes = <2>;
49 data-lanes = <3 1>;
Dspear1310.dtsi93 num-lanes = <1>;
111 num-lanes = <1>;
129 num-lanes = <1>;
Dexynos5440.dtsi299 num-lanes = <4>;
320 num-lanes = <4>;
Dk2e.dtsi104 num-lanes = <2>;
Dtegra30-cardhu.dtsi54 nvidia,num-lanes = <4>;
58 nvidia,num-lanes = <1>;
63 nvidia,num-lanes = <1>;
Dtegra30-apalis.dtsi23 nvidia,num-lanes = <4>;
27 nvidia,num-lanes = <1>;
31 nvidia,num-lanes = <1>;
Dspear1340.dtsi58 num-lanes = <1>;
Domap4-sdp.dts647 lanes = <0 1 2 3 4 5>;
672 lanes = <0 1 2 3 4 5>;
Dtegra30.dtsi60 nvidia,num-lanes = <2>;
73 nvidia,num-lanes = <2>;
86 nvidia,num-lanes = <2>;
Dexynos4412-trats2.dts309 data-lanes = <1 2 3 4>;
329 data-lanes = <1>;
455 data-lanes = <1>;
507 data-lanes = <1 2 3 4>;
Darmada-xp-mv78230.dtsi86 * configured as x4 or quad x1 lanes. One unit is
Dkeystone.dtsi291 num-lanes = <2>;
Dtegra20.dtsi621 nvidia,num-lanes = <2>;
634 nvidia,num-lanes = <2>;
Darmada-xp-mv78460.dtsi104 * configured as x4 or quad x1 lanes. Two units are
Darmada-xp-mv78260.dtsi87 * configured as x4 or quad x1 lanes. One unit is
Dtegra124.dtsi67 nvidia,num-lanes = <2>;
80 nvidia,num-lanes = <1>;
Dtegra124-jetson-tk1.dts1668 nvidia,lanes = "pcie-0", "pcie-1";
1674 nvidia,lanes = "pcie-2", "pcie-3",
1681 nvidia,lanes = "sata-0";
Dtegra30-beaver.dts33 nvidia,num-lanes = <2>;
37 nvidia,num-lanes = <2>;
42 nvidia,num-lanes = <2>;
Domap5-cm-t54.dts676 lanes = <1 0 3 2 5 4 7 6>;
Ddra7.dtsi231 num-lanes = <1>;
266 num-lanes = <1>;
Dimx6qdl.dtsi179 num-lanes = <1>;
Dimx6sx.dtsi1252 num-lanes = <1>;
/linux-4.4.14/Documentation/devicetree/bindings/media/i2c/
Dnokia,smia.txt35 - clock-lanes: <0>
36 - data-lanes: <1..n>
57 clock-lanes = <0>;
58 data-lanes = <1 2>;
Dtc358743.txt16 - data-lanes: should be <1 2 3 4> for four-lane operation,
18 - clock-lanes: should be <0>
42 data-lanes = <1 2 3 4>;
43 clock-lanes = <0>;
/linux-4.4.14/Documentation/devicetree/bindings/pci/
Ddesignware-pcie.txt17 - num-lanes: number of lanes to use
20 - num-lanes: number of lanes to use (this property should be specified unless
Dnvidia,tegra20-pcie.txt88 - If lanes 0 to 3 are used:
91 - If lanes 4 or 5 are used:
120 - nvidia,num-lanes: Number of lanes to use for this port. Valid combinations
122 - Root port 0 uses 4 lanes, root port 1 is unused.
123 - Both root ports use 2 lanes.
171 nvidia,num-lanes = <2>;
185 nvidia,num-lanes = <2>;
Dsamsung,exynos5440-pcie.txt34 num-lanes = <4>;
54 num-lanes = <4>;
Dti-pci.txt22 num-lanes,
47 num-lanes = <1>;
Dfsl,imx6q-pcie.txt29 num-lanes = <1>;
Dhisilicon-pcie.txt35 num-lanes = <8>;
Dlayerscape-pci.txt41 num-lanes = <4>;
Dmvebu-pci.txt78 multiple lanes. If this property is not found, we assume that the
/linux-4.4.14/Documentation/devicetree/bindings/media/
Dsamsung-mipi-csis.txt13 - bus-width : maximum number of data lanes supported (SoC specific);
42 - data-lanes : (required) an array specifying active physical MIPI-CSI2
43 data input lanes and their mapping to logical lanes; the
77 data-lanes = <1>, <2>;
Dvideo-interfaces.txt93 - data-lanes: an array of physical data lane indexes. Position of an entry
96 "data-lanes = <1 2>;", assuming the clock lane is on hardware lane 0.
98 - clock-lanes: an array of physical clock lane indexes. Position of an entry
100 physical lane, e.g. for a MIPI CSI-2 bus we could have "clock-lanes = <0>;",
109 - lane-polarities: an array of polarities of the lanes starting from the clock
110 lane and followed by the data lanes in the same order as in data-lanes.
112 should be the combined length of data-lanes and clock-lanes properties.
206 clock-lanes = <0>;
207 data-lanes = <1 2>;
227 clock-lanes = <0>;
[all …]
Dsamsung-s5k5baf.txt34 - data-lanes : (optional) specifies MIPI CSI-2 data lanes as covered in
55 data-lanes = <1>;
Dti,omap3isp.txt50 data-lanes : an array of data lanes from 1 to 3. The length can
52 clock-lanes : the clock lane (from 1 to 3). (required on CSI-2)
Dsamsung-s5k6a3.txt32 - data-lanes : (optional) specifies MIPI CSI-2 data lanes as covered in
Dsamsung-s5c73m3.txt48 - data-lanes : (optional) specifies MIPI CSI-2 data lanes as covered in
84 data-lanes = <1 2 3 4>;
Dsamsung-fimc.txt152 data-lanes = <1 2 3 4>;
204 data-lanes = <1 2 3 4>;
/linux-4.4.14/Documentation/devicetree/bindings/pinctrl/
Dnvidia,tegra124-xusb-padctl.txt4 The Tegra XUSB pad controller manages a set of lanes, each of which can be
34 Each subnode describes groups of lanes along with parameters and pads that
48 - nvidia,lanes: An array of strings. Each string is the name of a lane.
56 Note that not all of these properties are valid for all lanes. Lanes can be
111 nvidia,lanes = "pcie-0", "pcie-1";
117 nvidia,lanes = "pcie-2", "pcie-3",
124 nvidia,lanes = "sata-0";
/linux-4.4.14/Documentation/devicetree/bindings/display/ti/
Dti,omap5-dss.txt73 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
95 - lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
Dti,omap4-dss.txt92 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
114 - lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
Dti,dra7-dss.txt68 - lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
Dti,omap3-dss.txt82 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
/linux-4.4.14/drivers/gpu/drm/tegra/
Ddsi.c38 unsigned int lanes; member
71 unsigned int lanes; member
490 return dsi->master->lanes + dsi->lanes; in tegra_dsi_get_lanes()
493 return dsi->lanes + dsi->slave->lanes; in tegra_dsi_get_lanes()
495 return dsi->lanes; in tegra_dsi_get_lanes()
528 DSI_CONTROL_LANES(dsi->lanes - 1) | in tegra_dsi_configure()
612 unsigned int lanes = state->lanes; in tegra_dsi_configure() local
616 delay = DIV_ROUND_UP(delay * mul, div * lanes); in tegra_dsi_configure()
620 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes); in tegra_dsi_configure()
621 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes); in tegra_dsi_configure()
[all …]
Dsor.c1438 u8 rate, lanes; in tegra_sor_edp_enable() local
1456 lanes = link.num_lanes; in tegra_sor_edp_enable()
1465 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); in tegra_sor_edp_enable()
/linux-4.4.14/drivers/media/platform/soc_camera/
Dsh_mobile_csi2.c148 if (priv->client->lanes != 1) in sh_csi2_g_mbus_config()
152 switch (priv->client->lanes) { in sh_csi2_g_mbus_config()
232 if (priv->client->lanes == 1) in sh_csi2_hwinit()
239 if (!priv->client->lanes || priv->client->lanes > 4) in sh_csi2_hwinit()
243 tmp |= (1 << priv->client->lanes) - 1; in sh_csi2_hwinit()
/linux-4.4.14/drivers/nubus/
Dnubus.c211 dir->mask = board->lanes; in nubus_get_root_dir()
222 dir->mask = dev->board->lanes; in nubus_get_func_dir()
234 dir->mask = board->lanes; in nubus_get_board_dir()
732 nubus_rewind(&rp, 4, board->lanes); in nubus_find_rom_dir()
733 if (nubus_get_rom(&rp, 4, board->lanes) != NUBUS_TEST_PATTERN) { in nubus_find_rom_dir()
738 board->lanes); in nubus_find_rom_dir()
747 nubus_rewind(&romdir, ROM_DIR_OFFSET, board->lanes); in nubus_find_rom_dir()
750 dir.mask = board->lanes; in nubus_find_rom_dir()
794 nubus_move(&board->directory, nubus_expand32(board->doffset), board->lanes); in nubus_find_rom_dir()
847 board->lanes = bytelanes; in nubus_add_board()
/linux-4.4.14/drivers/gpu/drm/gma500/
Dintel_bios.c102 switch (edp_link_params->lanes) { in parse_edp()
104 dev_priv->edp.lanes = 1; in parse_edp()
107 dev_priv->edp.lanes = 2; in parse_edp()
111 dev_priv->edp.lanes = 4; in parse_edp()
115 dev_priv->edp.lanes, dev_priv->edp.rate, dev_priv->edp.bpp); in parse_edp()
Dintel_bios.h468 u8 lanes:4; member
Dpsb_drv.h610 int lanes; member
/linux-4.4.14/drivers/pci/host/
Dpci-xgene.c209 u32 *lanes, u32 *speed) in xgene_pcie_linkup() argument
220 *lanes = val32 >> 26; in xgene_pcie_linkup()
486 u32 val, lanes = 0, speed = 0; in xgene_pcie_setup() local
503 xgene_pcie_linkup(port, &lanes, &speed); in xgene_pcie_setup()
508 lanes, speed + 1); in xgene_pcie_setup()
Dpcie-designware.c494 ret = of_property_read_u32(np, "num-lanes", &pp->lanes); in dw_pcie_host_init()
496 pp->lanes = 0; in dw_pcie_host_init()
717 switch (pp->lanes) { in dw_pcie_setup_rc()
731 dev_err(pp->dev, "num-lanes %u: invalid value\n", pp->lanes); in dw_pcie_setup_rc()
739 switch (pp->lanes) { in dw_pcie_setup_rc()
Dpci-tegra.c314 unsigned int lanes; member
1366 static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes, in tegra_pcie_get_xbar_config() argument
1372 switch (lanes) { in tegra_pcie_get_xbar_config()
1384 switch (lanes) { in tegra_pcie_get_xbar_config()
1401 switch (lanes) { in tegra_pcie_get_xbar_config()
1581 u32 lanes = 0, mask = 0; in tegra_pcie_parse_dt() local
1689 lanes |= value << (index << 3); in tegra_pcie_parse_dt()
1712 rp->lanes = value; in tegra_pcie_parse_dt()
1722 err = tegra_pcie_get_xbar_config(pcie, lanes, &pcie->xbar_config); in tegra_pcie_parse_dt()
1795 port->index, port->lanes); in tegra_pcie_enable()
Dpcie-designware.h46 u32 lanes; member
DKconfig99 and have varied lanes from x1 to x8.
/linux-4.4.14/include/media/
Dsh_mobile_csi2.h33 unsigned char lanes; /* bitmask[3:0] */ member
Dsmiapp.h71 unsigned int lanes; /* Number of CSI-2 lanes */ member
/linux-4.4.14/drivers/media/i2c/
Dtc358743.c687 unsigned lanes = tc358743_num_csi_lanes_needed(sd); in tc358743_set_csi() local
693 if (lanes < 1) in tc358743_set_csi()
695 if (lanes < 1) in tc358743_set_csi()
697 if (lanes < 2) in tc358743_set_csi()
699 if (lanes < 3) in tc358743_set_csi()
701 if (lanes < 4) in tc358743_set_csi()
715 ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) | in tc358743_set_csi()
716 ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) | in tc358743_set_csi()
717 ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) | in tc358743_set_csi()
718 ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) | in tc358743_set_csi()
[all …]
Dsmiapp-pll.h42 uint8_t lanes; member
Dsmiapp-pll.c418 lane_op_clock_ratio = pll->csi2.lanes; in smiapp_pll_calculate()
430 * (pll->csi2.lanes / lane_op_clock_ratio); in smiapp_pll_calculate()
/linux-4.4.14/drivers/gpu/drm/panel/
Dpanel-simple.c1235 unsigned int lanes; member
1263 .lanes = 4,
1291 .lanes = 4,
1319 .lanes = 4,
1348 .lanes = 4,
1388 dsi->lanes = desc->lanes; in panel_simple_dsi_probe()
Dpanel-sharp-lq101r1sx01.c381 dsi->lanes = 4; in sharp_panel_probe()
Dpanel-samsung-s6e8aa0.c990 dsi->lanes = 4; in s6e8aa0_probe()
/linux-4.4.14/arch/x86/crypto/sha-mb/
Dsha1_mb_mgr_flush_avx2.S127 # If bit (32+3) is set, then all lanes are empty
156 # copy idx to empty lanes
257 ## if bit 32+3 is set, then all lanes are empty
/linux-4.4.14/Documentation/devicetree/bindings/display/bridge/
Dps8622.txt10 - lane-count: number of DP lanes to use
/linux-4.4.14/drivers/pinctrl/
Dpinctrl-tegra-xusb.c69 const struct tegra_xusb_padctl_lane *lanes; member
309 lane = &padctl->soc->lanes[group]; in tegra_xusb_padctl_pinmux_set()
343 lane = &padctl->soc->lanes[group]; in tegra_xusb_padctl_pinconf_group_get()
382 lane = &padctl->soc->lanes[group]; in tegra_xusb_padctl_pinconf_group_set()
865 .lanes = tegra124_lanes,
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Damdgpu_dpm.h83 u8 amdgpu_encode_pci_lane_width(u32 lanes);
Damdgpu_dpm.c947 u8 amdgpu_encode_pci_lane_width(u32 lanes) in amdgpu_encode_pci_lane_width() argument
951 if (lanes > 16) in amdgpu_encode_pci_lane_width()
954 return encoded_lanes[lanes]; in amdgpu_encode_pci_lane_width()
/linux-4.4.14/arch/arm/mach-omap2/
Ddisplay.c113 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes) in omap4_dsi_mux_pads() argument
138 reg |= (lanes << enable_shift) & enable_mask; in omap4_dsi_mux_pads()
139 reg |= (lanes << pipd_shift) & pipd_mask; in omap4_dsi_mux_pads()
/linux-4.4.14/include/linux/
Dnubus.h42 unsigned char lanes; member
/linux-4.4.14/drivers/net/ethernet/ti/
Dnetcp_xgbepcsr.c315 void __iomem *sw_regs, u32 lanes, in netcp_xgbe_check_link_status() argument
323 for (i = 0; i < lanes; i++) { in netcp_xgbe_check_link_status()
/linux-4.4.14/drivers/gpu/drm/msm/dsi/
Ddsi_host.c130 unsigned int lanes; member
518 u8 lanes = msm_host->lanes; in dsi_calc_clk_rate() local
528 if (lanes > 0) { in dsi_calc_clk_rate()
529 msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes); in dsi_calc_clk_rate()
686 DBG("lane number=%d", msm_host->lanes); in dsi_ctrl_config()
687 if (msm_host->lanes == 2) { in dsi_ctrl_config()
1293 msm_host->lanes = dsi->lanes; in dsi_host_attach()
/linux-4.4.14/drivers/edac/
Dppc4xx_edac.c442 unsigned int lane, lanes; in ppc4xx_edac_generate_lane_message() local
455 for (lanes = 0, lane = first_lane; lane < lane_count; lane++) { in ppc4xx_edac_generate_lane_message()
459 (lanes++ ? ", " : ""), lane); in ppc4xx_edac_generate_lane_message()
470 n = snprintf(buffer, size, "%s; ", lanes ? "" : "None"); in ppc4xx_edac_generate_lane_message()
/linux-4.4.14/arch/arm64/boot/dts/freescale/
Dfsl-ls2080a.dtsi400 num-lanes = <4>;
423 num-lanes = <4>;
446 num-lanes = <8>;
469 num-lanes = <4>;
/linux-4.4.14/drivers/scsi/ufs/
Dufs-qcom.c717 int lanes = max_t(u32, p->lane_rx, p->lane_tx); in ufs_qcom_get_speed_mode() local
724 if (!lanes) in ufs_qcom_get_speed_mode()
725 lanes = 1; in ufs_qcom_get_speed_mode()
734 p->hs_rate == PA_HS_MODE_B ? "B" : "A", gear, lanes); in ufs_qcom_get_speed_mode()
738 "PWM", gear, lanes); in ufs_qcom_get_speed_mode()
/linux-4.4.14/drivers/gpu/drm/exynos/
Dexynos_drm_dsi.c279 u32 lanes; member
669 | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1) in exynos_dsi_enable_clock()
750 reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK | in exynos_dsi_enable_lane()
841 lanes_mask = BIT(dsi->lanes) - 1; in exynos_dsi_init_link()
1307 exynos_dsi_enable_lane(dsi, BIT(dsi->lanes) - 1); in exynos_dsi_init()
1365 dsi->lanes = device->lanes; in exynos_dsi_host_attach()
/linux-4.4.14/Documentation/nvdimm/
Dbtt.txt145 c. The concept of lanes
154 there are more CPUs than the max number of available lanes, than lanes are
190 at the same time, duplicating another free entry for two lanes.
/linux-4.4.14/include/drm/
Ddrm_mipi_dsi.h156 unsigned int lanes; member
/linux-4.4.14/Documentation/devicetree/bindings/display/exynos/
Dexynos_dp.txt50 number of lanes supported by the panel.
/linux-4.4.14/arch/x86/crypto/
Dsha512-avx2-asm.S49 # This code schedules 1 blocks at a time, with 4 lanes per block
235 # Move to appropriate lanes for calculating w[16] and w[17]
237 # Move to appropriate lanes for calculating w[18] and w[19]
240 # Calculate w[16] and w[17] in both 128 bit lanes
242 # Calculate sigma1 for w[16] and w[17] on both 128 bit lanes
Dsha256-avx-asm.S47 # This code schedules 1 block at a time, with 4 lanes per block
Dsha256-avx2-asm.S48 # This code schedules 2 blocks at a time, with 4 lanes per block
/linux-4.4.14/Documentation/devicetree/bindings/phy/
Dapm-xgene-phy.txt4 PHY (pair of lanes) has its own node.
/linux-4.4.14/drivers/gpu/drm/radeon/
Dr600_dpm.h234 u8 r600_encode_pci_lane_width(u32 lanes);
Drv770.c1975 u32 link_width_cntl, lanes, speed_cntl, tmp; in rv770_pcie_gen2_enable() local
2003 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; in rv770_pcie_gen2_enable()
2006 link_width_cntl |= lanes | LC_RECONFIG_NOW | in rv770_pcie_gen2_enable()
Dr600_dpm.c1359 u8 r600_encode_pci_lane_width(u32 lanes) in r600_encode_pci_lane_width() argument
1363 if (lanes > 16) in r600_encode_pci_lane_width()
1366 return encoded_lanes[lanes]; in r600_encode_pci_lane_width()
Dr300.c499 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes) in rv370_set_pcie_lanes() argument
511 switch (lanes) { in rv370_set_pcie_lanes()
Dr600.c4352 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes) in r600_set_pcie_lanes() argument
4368 switch (lanes) { in r600_set_pcie_lanes()
4392 DRM_ERROR("invalid pcie lane request: %d\n", lanes); in r600_set_pcie_lanes()
4444 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; in r600_pcie_gen2_enable() local
4486 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT; in r600_pcie_gen2_enable()
4489 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN; in r600_pcie_gen2_enable()
Dradeon_asic.h179 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
368 extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
Dradeon.h1964 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
/linux-4.4.14/drivers/media/i2c/smiapp/
Dsmiapp-core.c1269 sensor->platform_data->lanes - 1); in smiapp_power_on()
2698 pll->csi2.lanes = sensor->platform_data->lanes; in smiapp_init()
3007 pdata->lanes = bus_cfg->bus.mipi_csi2.num_data_lanes; in smiapp_get_pdata()
3008 dev_dbg(dev, "lanes %u\n", pdata->lanes); in smiapp_get_pdata()
/linux-4.4.14/drivers/gpu/drm/i915/
Dintel_bios.c564 switch (edp_link_params->lanes) { in parse_edp()
576 edp_link_params->lanes); in parse_edp()
Dintel_bios.h554 u8 lanes:4; member
/linux-4.4.14/Documentation/devicetree/bindings/powerpc/fsl/
Dinterlaken-lac.txt28 through SerDes lanes.
/linux-4.4.14/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra20-host1x.txt195 up with in order to support up to 8 data lanes
/linux-4.4.14/crypto/
DKconfig681 multiple data lanes concurrently with SIMD instructions for
684 the data lanes filled to get performance benefit. If the data
685 lanes remain unfilled, a flush operation will be initiated to