Searched refs:k0 (Results 1 - 36 of 36) sorted by relevance

/linux-4.4.14/arch/mips/kernel/
H A Dbmips_vec.S41 la k0, 1f
43 or k0, k1
44 jr k0
51 li k0, ST0_IE | ST0_BEV | STATUSF_IP1
52 mtc0 k0, CP0_STATUS
55 li k0, 0xff400000
56 mtc0 k0, $22, 6
62 or k0, k1
64 sw k1, 0(k0)
69 la k0, bmips_reset_nmi_vec
71 or k0, k1
72 jr k0
89 mfc0 k0, CP0_STATUS
90 and k0, k1
91 beqz k0, bmips_smp_entry
94 mfc0 k0, CP0_PRID
96 andi k0, 0xff00
97 bne k0, k1, 1f
101 mfc0 k0, $22
102 and k0, k1
103 bnez k0, bmips_smp_entry
113 mfc0 k0, CP0_STATUS
115 or k0, k1
116 xor k0, k1
117 mtc0 k0, CP0_STATUS
121 la k0, nmi_handler
122 jr k0
138 li k0, 0x30000000
139 mtc0 k0, CP0_STATUS
143 mfc0 k0, CP0_CONFIG
144 ori k0, 0x07
145 xori k0, 0x04
146 mtc0 k0, CP0_CONFIG
148 mfc0 k0, CP0_PRID
149 andi k0, 0xff00
152 bne k0, k1, 2f
155 li k0, 0x80000000
161 1: cache Index_Store_Tag_I, 0(k0)
162 addiu k0, 16
163 bne k0, k1, 1b
171 bne k0, k1, 3f
173 la k0, ebase
174 lw k0, 0(k0)
175 mtc0 k0, $15, 1
180 la k0, 1f
181 jr k0
183 la k0, bmips_enable_xks01
184 jalr k0
188 la k0, plat_wired_tlb_setup
189 jalr k0
195 la k0, bmips_smp_boot_sp
196 lw sp, 0(k0)
197 la k0, bmips_smp_boot_gp
198 lw gp, 0(k0)
199 la k0, start_secondary
200 jr k0
221 mfc0 k0, CP0_STATUS
222 ori k0, 0x01
223 xori k0, 0x01
224 mtc0 k0, CP0_STATUS
H A Dgenex.S36 mfc0 k0, CP0_INDEX
43 PTR_L k0, exception_handlers(k1)
44 jr k0
59 li k0, 31<<2
64 beq k1, k0, handle_vced
65 li k0, 14<<2
66 beq k1, k0, handle_vcei
71 PTR_L k0, exception_handlers(k1)
72 jr k0
81 MFC0 k0, CP0_BADVADDR
83 and k0, k1 # ... really needed?
85 cache Index_Store_Tag_D, (k0)
86 cache Hit_Writeback_Inv_SD, (k0)
88 PTR_LA k0, vced_count
89 lw k1, (k0)
91 sw k1, (k0)
96 MFC0 k0, CP0_BADVADDR
97 cache Hit_Writeback_Inv_SD, (k0) # also cleans pi
99 PTR_LA k0, vcei_count
100 lw k1, (k0)
102 sw k1, (k0)
141 MFC0 k0, CP0_EPC
143 ori k0, 0x1f /* 32 byte rollback region */
144 xori k0, 0x1f
145 bne k0, k1, 9f
146 MTC0 k0, CP0_EPC
167 mfc0 k0, CP0_STATUS
169 and k0, ST0_IEP
170 bnez k0, 1f
172 mfc0 k0, CP0_EPC
174 j k0
177 and k0, ST0_IE
178 bnez k0, 1f
276 MTC0 k0, CP0_DESAVE
277 mfc0 k0, CP0_DEBUG
279 sll k0, k0, 30 # Check for SDBBP.
280 bgez k0, ejtag_return
282 PTR_LA k0, ejtag_debug_buffer
283 LONG_S k1, 0(k0)
288 PTR_LA k0, ejtag_debug_buffer
289 LONG_L k1, 0(k0)
292 MFC0 k0, CP0_DESAVE
331 mfc0 k0, CP0_STATUS
332 ori k0, k0, ST0_EXL
334 and k0, k0, k1
335 mtc0 k0, CP0_STATUS
459 MFC0 k0, CP0_EPC
460 PTR_SRL k0, _PAGE_SHIFT + 1
461 PTR_SLL k0, _PAGE_SHIFT + 1
462 or k1, k0
481 and k0, k1, 1
482 beqz k0, 1f
483 xor k1, k0
484 lhu k0, (k1)
486 ins k1, k0, 16, 16
487 lui k0, 0x007d
489 ori k0, 0x6b3c
491 lui k0, 0x7c03
493 ori k0, 0xe83b
495 andi k0, k1, 1
496 bnez k0, handle_ri
497 lui k0, 0x7c03
499 ori k0, 0xe83b
503 bne k0, k1, handle_ri /* if not ours */
509 MFC0 k0, CP0_EPC
514 LONG_ADDIU k0, 4
515 jr k0
519 LONG_ADDIU k0, 4 /* stall on $k0 */
522 LONG_ADDIU k0, 4
525 MTC0 k0, CP0_EPC
H A Dcps-vec.S74 mfc0 k0, CP0_STATUS
75 and k0, k0, ST0_NMI
76 beqz k0, not_nmi
80 PTR_LA k0, nmi_handler
81 jr k0
249 PTR_LA k0, ejtag_debug_handler
250 jr k0
H A Docteon_switch.S420 * safely modify v1,k0, k1,$10-$15, and $24. It will
436 v3mulu k0, $0, $0
438 sd k0, PT_MTP(sp) /* PT_MTP has P0 */
439 v3mulu k0, $0, $0
443 sd k0, PT_MTP+16(sp) /* PT_MTP+16 has P2 */
444 v3mulu k0, $0, $0
447 sd k0, PT_MPL+8(sp) /* PT_MPL+8 has MPL1 */
507 ld k0, PT_MPL+16(sp) /* MPL2 */
514 mtm2 k0 /* MPL2 */
H A Dentry.S51 lw k0, TI_R2_EMUL_RET($28)
52 bnez k0, restore_all_from_r2_emul
H A Dptrace.c300 /* k0/k1 are copied as zero. */ gpr32_get()
346 /* k0/k1 are ignored. */ gpr32_set()
379 /* k0/k1 are copied as zero. */ gpr64_get()
421 /* k0/k1 are ignored. */ gpr64_set()
H A Dkgdb.c82 { "k0", GDB_SIZEOF_REG, offsetof(struct pt_regs, regs[26]) },
H A Dtraps.c1900 unsigned int k0 = 26; set_except_vector() local
1905 UASM_i_LA(&buf, k0, handler); set_except_vector()
1906 uasm_i_jr(&buf, k0); set_except_vector()
H A Dpm-cps.c85 t8, t9, k0, k1, gp, sp, fp, ra, enumerator in enum:mips_reg
/linux-4.4.14/arch/sh/boards/mach-hp6xx/
H A Dpm_wakeup.S15 * k0 scratch
20 #define k0 r0 define
26 and #127, k0
27 mov.b k0, @k1
30 mov.w 6f, k0
31 mov.w k0, @k1
/linux-4.4.14/arch/mips/mm/
H A Dcex-sb1.S48 * (0x170-0x17f) are used to preserve k0, k1, and ra.
55 * save/restore k0 and k1 from low memory (Useg is direct
61 sd k0,0x170($0)
74 sll k0,k1,1
86 * k0 has C0_ERRCTL << 1, which puts 'DC' at bit 31. Any
94 bltz k0,unrecoverable
95 sll k0,1
98 * k0 has C0_ERRCTL << 2, which puts 'IC' at bit 31. If an
102 bgez k0,unrecoverable
110 mfc0 k0,C0_CERR_I /* delay slot */
112 and k1,k0
114 andi k0,0x1fe0
121 cache Index_Invalidate_I,(0<<13)(k0)
122 cache Index_Invalidate_I,(1<<13)(k0)
123 cache Index_Invalidate_I,(2<<13)(k0)
124 cache Index_Invalidate_I,(3<<13)(k0)
130 ld k0,0x170($0)
143 mfc0 k0,CP0_CONFIG
145 and k0,k0,k1
146 ori k0,k0,CONF_CM_UNCACHED
147 mtc0 k0,CP0_CONFIG
155 mfc0 k0, CP0_STATUS
156 sll k0, k0, 3 # check CU0 (kernel?)
157 bltz k0, 2f
/linux-4.4.14/arch/mips/kvm/
H A Dlocore.S55 /* k0/k1 not being used in host kernel context */
88 * XXXKYMA k0/k1 not saved, not being used if we got here through
135 li k0, (ST0_EXL | KSU_USER | ST0_BEV)
136 mtc0 k0, CP0_STATUS
140 LONG_L k0, VCPU_GUEST_EBASE(k1)
141 mtc0 k0, CP0_EBASE
148 li k0, (ST0_EXL | KSU_USER | ST0_IE)
150 or k0, k0, v0
151 mtc0 k0, CP0_STATUS
172 LONG_L k0, (t3)
173 andi k0, k0, 0xff
174 mtc0 k0, CP0_ENTRYHI
209 /* k0/k1 loaded up later */
217 LONG_L k0, VCPU_LO(k1)
218 mtlo k0
220 LONG_L k0, VCPU_HI(k1)
221 mthi k0
224 /* Restore the guest's k0/k1 registers */
225 LONG_L k0, VCPU_R26(k1)
233 mtc0 k0, CP0_ERROREPC #01: Save guest k0
236 mfc0 k0, CP0_EBASE #02: Get EBASE
237 INT_SRL k0, k0, 10 #03: Get rid of CPUNum
238 INT_SLL k0, k0, 10 #04
239 LONG_S k1, 0x3000(k0) #05: Save k1 @ offset 0x3000
240 INT_ADDIU k0, k0, 0x2000 #06: Exception handler is
242 j k0 #07: jump to the function
284 /* Guest k0/k1 saved later */
298 /* Finally save guest k0/k1 to VCPU */
324 mfc0 k0,CP0_EPC
325 LONG_S k0, VCPU_PC(k1)
327 mfc0 k0, CP0_BADVADDR
328 LONG_S k0, VCPU_HOST_CP0_BADVADDR(k1)
330 mfc0 k0, CP0_CAUSE
331 LONG_S k0, VCPU_HOST_CP0_CAUSE(k1)
333 mfc0 k0, CP0_ENTRYHI
334 LONG_S k0, VCPU_HOST_ENTRYHI(k1)
343 or k0, v0, ST0_BEV
346 mtc0 k0, CP0_STATUS
349 LONG_L k0, VCPU_HOST_EBASE(k1)
350 mtc0 k0,CP0_EBASE
411 LONG_L k0, PT_HOST_USERLOCAL(sp)
412 mtc0 k0, CP0_DDATA_LO
415 PTR_LI k0, 0x2000000F
416 mtc0 k0, CP0_HWRENA
434 * XXXKYMA: k0/k1 could have been blown away if we processed
460 or k0, v1, ST0_BEV
462 mtc0 k0, CP0_STATUS
491 LONG_L k0, (t3)
492 andi k0, k0, 0xff
493 mtc0 k0,CP0_ENTRYHI
534 LONG_L k0, VCPU_HI(k1)
535 mthi k0
537 LONG_L k0, VCPU_LO(k1)
538 mtlo k0
540 LONG_L k0, VCPU_R26(k1)
551 LONG_L k0, PT_HOST_USERLOCAL(k1)
552 mtc0 k0, CP0_DDATA_LO
555 LONG_L k0, PT_HOST_ASID(sp)
556 andi k0, 0xff
557 mtc0 k0,CP0_ENTRYHI
568 INT_SRA k0, v0, 2
569 move $2, k0
595 /* Host k0/k1 were not saved */
601 LONG_L k0, PT_HI(k1)
602 mthi k0
604 LONG_L k0, PT_LO(k1)
605 mtlo k0
608 PTR_LI k0, 0x2000000F
609 mtc0 k0, CP0_HWRENA
/linux-4.4.14/arch/mips/include/asm/
H A Dpm.h38 mfc0 k0, CP0_STATUS variable
39 LONG_S k0, PT_STATUS(sp) variable
47 LONG_L k0, PT_STATUS(sp)
48 mtc0 k0, CP0_STATUS variable
79 mfc0 k0, CP0_PAGEMASK, 2 /* SegCtl0 */
80 LONG_S k0, SSS_SEGCTL0(t1) variable
81 mfc0 k0, CP0_PAGEMASK, 3 /* SegCtl1 */ variable
82 LONG_S k0, SSS_SEGCTL1(t1) variable
83 mfc0 k0, CP0_PAGEMASK, 4 /* SegCtl2 */ variable
84 LONG_S k0, SSS_SEGCTL2(t1) variable
98 LONG_L k0, SSS_SEGCTL0(t1)
99 mtc0 k0, CP0_PAGEMASK, 2 /* SegCtl0 */ variable
100 LONG_L k0, SSS_SEGCTL1(t1) variable
101 mtc0 k0, CP0_PAGEMASK, 3 /* SegCtl1 */ variable
102 LONG_L k0, SSS_SEGCTL2(t1) variable
103 mtc0 k0, CP0_PAGEMASK, 4 /* SegCtl2 */ variable
H A Dstackframe.h88 ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG
98 LONG_SRL k0, SMP_CPUID_PTRSHIFT variable
99 LONG_ADDU k1, k0
116 move k0, ra
125 1: move ra, k0
126 li k0, 3
127 mtc0 k0, $22
150 mfc0 k0, CP0_STATUS
151 sll k0, 3 /* extract cu0 bit */ variable
153 bltz k0, 8f
177 MFC0 k0, CP0_ENTRYHI variable
178 MTC0 k0, CP0_ENTRYHI variable
184 8: move k0, sp
187 .set at=k0
190 move k0, sp
193 LONG_S k0, PT_R29(sp) variable
317 LONG_L k0, PT_EPC(sp)
319 jr k0
H A Dregdef.h53 #define k0 $26 /* kernel scratch */ macro
96 #define k0 $26 /* kernel temporary */ macro
H A Dptrace.h23 * system call/exception. As usual the registers k0/k1 aren't being saved.
/linux-4.4.14/arch/sh/kernel/cpu/sh3/
H A Dentry.S37 * jmp @k0 ! control-transfer instruction
71 #define k0 r0 define
85 * k0 scratch
200 mov.l 2f, k0
201 mov.l @k0, k0
202 jmp @k0
266 mov k3, k0 ! Calculate IMASK-bits
267 shlr2 k0
268 and #0x3c, k0
269 cmp/eq #0x3c, k0
271 shll2 k0
272 mov g_imask, k0
274 6: or k0, k2 ! Set the IMASK-bits
306 ! k0 returns original sp (after roll back)
313 mov r15, k0
314 shll k0
316 shll k0
319 stc r0_bank, k0
320 cmp/hs k0, k1 ! test k1 (saved PC) >= k0 (saved r0)
324 add #-2, k0
325 add r15, k0
326 ldc k0, spc ! PC = saved r0 + r15 - 2
331 stc ssr, k0 ! Is it from kernel space?
332 shll k0 ! Check MD bit (bit30) by shifting it into...
333 shll k0 ! ...the T bit
335 mov r15, k0 ! save original stack to k0
355 mova exception_data, k0
357 ! Setup stack and save DSP context (k0 contains original r15 on return)
359 PREF(k0)
387 ! k0 contains original stack pointer*
403 mov.l k0, @-r15 ! original stack pointer in k0
444 mova exception_data, k0
446 ! Setup stack and save DSP context (k0 contains original r15 on return)
448 PREF(k0)
H A Dswsusp.S16 #define k0 r0 define
116 stc r2_bank, k0 ! fetch old sp from r2_bank0
/linux-4.4.14/arch/mips/boot/compressed/
H A Dhead.S55 PTR_LA k0, decompress_kernel
56 jr k0
63 PTR_LI k0, KERNEL_ENTRY
64 jr k0
/linux-4.4.14/arch/mips/mti-sead3/
H A Dsead3-init.c81 * 3C1A8000 lui k0,0x8000 mips_nmi_setup()
82 * 375A0381 ori k0,k0,0x381 mips_nmi_setup()
83 * 03400008 jr k0 mips_nmi_setup()
/linux-4.4.14/crypto/
H A Dtea.c65 u32 k0, k1, k2, k3; tea_encrypt() local
73 k0 = ctx->KEY[0]; tea_encrypt()
82 y += ((z << 4) + k0) ^ (z + sum) ^ ((z >> 5) + k1); tea_encrypt()
93 u32 k0, k1, k2, k3; tea_decrypt() local
101 k0 = ctx->KEY[0]; tea_decrypt()
112 y -= ((z << 4) + k0) ^ (z + sum) ^ ((z >> 5) + k1); tea_decrypt()
H A Dvmac.c244 #define k0 (*(((u32 *)kl)+INDEX_LOW)) poly_step_func() macro
257 p += MUL32(a2, k0); poly_step_func()
263 p += MUL32(a3, k0); poly_step_func()
267 p += MUL32(a0, k0); poly_step_func()
277 p += MUL32(a1, k0); poly_step_func()
290 #undef k0 poly_step_func() macro
/linux-4.4.14/arch/sh/kernel/cpu/shmobile/
H A Dsleep.S21 * k0 scratch
24 #define k0 r0 define
253 mov.l 1f, k0
254 and k0, k1
260 mov.l @(SH_SLEEP_SR, k1), k0
261 ldc k0, sr
/linux-4.4.14/drivers/staging/skein/
H A Dthreefish_block.c8 u64 k0 = key_ctx->key[0], k1 = key_ctx->key[1], threefish_encrypt_256() local
15 b0 += b1 + k0; threefish_encrypt_256()
71 b3 += k0 + 2; threefish_encrypt_256()
98 b2 += b3 + k0 + t1; threefish_encrypt_256()
120 b1 += k0 + t1; threefish_encrypt_256()
147 b0 += b1 + k0; threefish_encrypt_256()
203 b3 += k0 + 7; threefish_encrypt_256()
231 b2 += b3 + k0 + t0; threefish_encrypt_256()
252 b1 += k0 + t0; threefish_encrypt_256()
280 b0 += b1 + k0; threefish_encrypt_256()
336 b3 += k0 + 12; threefish_encrypt_256()
363 b2 += b3 + k0 + t2; threefish_encrypt_256()
385 b1 += k0 + t2; threefish_encrypt_256()
412 b0 += b1 + k0; threefish_encrypt_256()
468 b3 += k0 + 17; threefish_encrypt_256()
492 output[2] = b2 + k0 + t1; threefish_encrypt_256()
501 u64 k0 = key_ctx->key[0], k1 = key_ctx->key[1], threefish_decrypt_256() local
511 b2 -= k0 + t1; threefish_decrypt_256()
545 b3 -= k0 + 17; threefish_decrypt_256()
608 b0 -= b1 + k0; threefish_decrypt_256()
643 b1 -= k0 + t2; threefish_decrypt_256()
682 b2 -= b3 + k0 + t2; threefish_decrypt_256()
717 b3 -= k0 + 12; threefish_decrypt_256()
780 b0 -= b1 + k0; threefish_decrypt_256()
816 b1 -= k0 + t0; threefish_decrypt_256()
854 b2 -= b3 + k0 + t0; threefish_decrypt_256()
890 b3 -= k0 + 7; threefish_decrypt_256()
953 b0 -= b1 + k0; threefish_decrypt_256()
988 b1 -= k0 + t1; threefish_decrypt_256()
1027 b2 -= b3 + k0 + t1; threefish_decrypt_256()
1062 b3 -= k0 + 2; threefish_decrypt_256()
1125 b0 -= b1 + k0; threefish_decrypt_256()
1146 u64 k0 = key_ctx->key[0], k1 = key_ctx->key[1], threefish_encrypt_512() local
1155 b0 += b1 + k0; threefish_encrypt_512()
1270 b7 += k0 + 2; threefish_encrypt_512()
1323 b6 += b7 + k0 + t1; threefish_encrypt_512()
1370 b5 += k0 + t1; threefish_encrypt_512()
1423 b4 += b5 + k0; threefish_encrypt_512()
1470 b3 += k0; threefish_encrypt_512()
1523 b2 += b3 + k0; threefish_encrypt_512()
1570 b1 += k0; threefish_encrypt_512()
1623 b0 += b1 + k0; threefish_encrypt_512()
1738 b7 += k0 + 11; threefish_encrypt_512()
1791 b6 += b7 + k0 + t1; threefish_encrypt_512()
1838 b5 += k0 + t1; threefish_encrypt_512()
1891 b4 += b5 + k0; threefish_encrypt_512()
1938 b3 += k0; threefish_encrypt_512()
1991 b2 += b3 + k0; threefish_encrypt_512()
2038 b1 += k0; threefish_encrypt_512()
2090 output[0] = b0 + k0; threefish_encrypt_512()
2107 u64 k0 = key_ctx->key[0], k1 = key_ctx->key[1], threefish_decrypt_512() local
2117 b0 -= k0; threefish_decrypt_512()
2192 b1 -= k0; threefish_decrypt_512()
2254 b2 -= b3 + k0; threefish_decrypt_512()
2323 b3 -= k0; threefish_decrypt_512()
2385 b4 -= b5 + k0; threefish_decrypt_512()
2454 b5 -= k0 + t1; threefish_decrypt_512()
2516 b6 -= b7 + k0 + t1; threefish_decrypt_512()
2585 b7 -= k0 + 11; threefish_decrypt_512()
2735 b0 -= b1 + k0; threefish_decrypt_512()
2804 b1 -= k0; threefish_decrypt_512()
2866 b2 -= b3 + k0; threefish_decrypt_512()
2935 b3 -= k0; threefish_decrypt_512()
2997 b4 -= b5 + k0; threefish_decrypt_512()
3066 b5 -= k0 + t1; threefish_decrypt_512()
3128 b6 -= b7 + k0 + t1; threefish_decrypt_512()
3197 b7 -= k0 + 2; threefish_decrypt_512()
3347 b0 -= b1 + k0; threefish_decrypt_512()
3372 u64 k0 = key_ctx->key[0], k1 = key_ctx->key[1], threefish_encrypt_1024() local
3385 b0 += b1 + k0; threefish_encrypt_1024()
3620 b15 += k0 + 2; threefish_encrypt_1024()
3725 b14 += b15 + k0 + t1; threefish_encrypt_1024()
3824 b13 += k0 + t1; threefish_encrypt_1024()
3929 b12 += b13 + k0; threefish_encrypt_1024()
4028 b11 += k0; threefish_encrypt_1024()
4133 b10 += b11 + k0; threefish_encrypt_1024()
4232 b9 += k0; threefish_encrypt_1024()
4337 b8 += b9 + k0; threefish_encrypt_1024()
4436 b7 += k0; threefish_encrypt_1024()
4541 b6 += b7 + k0; threefish_encrypt_1024()
4640 b5 += k0; threefish_encrypt_1024()
4745 b4 += b5 + k0; threefish_encrypt_1024()
4844 b3 += k0; threefish_encrypt_1024()
4949 b2 += b3 + k0; threefish_encrypt_1024()
5048 b1 += k0; threefish_encrypt_1024()
5153 b0 += b1 + k0; threefish_encrypt_1024()
5388 b15 += k0 + 19; threefish_encrypt_1024()
5478 output[14] = b14 + k0 + t0; threefish_encrypt_1024()
5493 u64 k0 = key_ctx->key[0], k1 = key_ctx->key[1], threefish_decrypt_1024() local
5520 b14 -= k0 + t0; threefish_decrypt_1024()
5621 b15 -= k0 + 19; threefish_decrypt_1024()
5927 b0 -= b1 + k0; threefish_decrypt_1024()
6064 b1 -= k0; threefish_decrypt_1024()
6194 b2 -= b3 + k0; threefish_decrypt_1024()
6331 b3 -= k0; threefish_decrypt_1024()
6461 b4 -= b5 + k0; threefish_decrypt_1024()
6598 b5 -= k0; threefish_decrypt_1024()
6728 b6 -= b7 + k0; threefish_decrypt_1024()
6865 b7 -= k0; threefish_decrypt_1024()
6995 b8 -= b9 + k0; threefish_decrypt_1024()
7132 b9 -= k0; threefish_decrypt_1024()
7262 b10 -= b11 + k0; threefish_decrypt_1024()
7399 b11 -= k0; threefish_decrypt_1024()
7529 b12 -= b13 + k0; threefish_decrypt_1024()
7666 b13 -= k0 + t1; threefish_decrypt_1024()
7796 b14 -= b15 + k0 + t1; threefish_decrypt_1024()
7933 b15 -= k0 + 2; threefish_decrypt_1024()
8239 b0 -= b1 + k0; threefish_decrypt_1024()
/linux-4.4.14/arch/mips/netlogic/common/
H A Dreset.S146 * We use scratch reg 6/7 to save k0/k1 and check for NMI first.
161 dmtc0 k0, $22, 6
163 mfc0 k0, CP0_STATUS
165 and k1, k0, k1
169 ld k0, BOOT_NMI_HANDLER(k1)
170 jr k0
/linux-4.4.14/arch/score/include/uapi/asm/
H A Dptrace.h40 * system call/exception. As usual the registers k0/k1 aren't being saved.
/linux-4.4.14/arch/mips/include/uapi/asm/
H A Dreg.h43 * k0/k1 unsaved
95 * k0/k1 unsaved
/linux-4.4.14/arch/mips/cavium-octeon/
H A Docteon_boot.h30 /* k0 is used for global data - needs to be passed to other cores */
/linux-4.4.14/arch/x86/include/asm/
H A Dsegment.h260 "1: movl %k0,%%" #seg " \n" \
263 "2: xorl %k0,%k0 \n" \
/linux-4.4.14/arch/ia64/include/asm/
H A Dkregs.h15 #define IA64_KR_IO_BASE 0 /* ar.k0: legacy I/O base address */
/linux-4.4.14/drivers/watchdog/
H A Docteon-wdt-main.c138 * cause corruption of k0 in the saved registers. Since we're octeon_wdt_build_stage1()
311 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
/linux-4.4.14/arch/ia64/kernel/
H A Dsetup.c420 * value firmware left in ar.k0. io_port_init()
422 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute io_port_init()
425 * *physical* address in ar.k0 to mmap the appropriate area from io_port_init()
429 * ar.k0 is not involved in kernel I/O port accesses, which can use io_port_init()
/linux-4.4.14/drivers/net/wireless/brcm80211/brcmsmac/
H A Dtypes.h119 * 0 4329a0/k0
/linux-4.4.14/arch/x86/include/asm/fpu/
H A Dtypes.h192 * k0-k7 (opmask state).
/linux-4.4.14/arch/sh/kernel/
H A Dentry-common.S26 * jmp @k0 ! control-transfer instruction
/linux-4.4.14/drivers/isdn/hardware/eicon/
H A Dio.c190 DBG_FTL(("t8 0x%08x t9 0x%08x k0 0x%08x k1 0x%08x", dump_trap_frame()

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