Searched refs:jt_offset (Results 1 – 10 of 10) sorted by relevance
56 uint32_t jt_offset; /* jt location */ member74 uint32_t jt_offset; /* jt location */ member98 uint32_t jt_offset; /* jt location */ member
99 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset)); in amdgpu_ucode_print_gfx_hdr()134 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset)); in amdgpu_ucode_print_rlc_hdr()187 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset)); in amdgpu_ucode_print_sdma_hdr()
404 gpu_addr += le32_to_cpu(header->jt_offset) << 2; in fiji_smu_populate_single_firmware_entry()
687 gpu_addr += le32_to_cpu(header->jt_offset) << 2; in amdgpu_cgs_get_firmware_info()
406 gpu_addr += le32_to_cpu(header->jt_offset) << 2; in tonga_smu_populate_single_firmware_entry()
469 gpu_addr += le32_to_cpu(header->jt_offset) << 2; in cz_smu_populate_single_firmware_entry()
4336 table_offset = le32_to_cpu(hdr->jt_offset); in gfx_v7_0_init_cp_pg_table()4344 table_offset = le32_to_cpu(hdr->jt_offset); in gfx_v7_0_init_cp_pg_table()4352 table_offset = le32_to_cpu(hdr->jt_offset); in gfx_v7_0_init_cp_pg_table()4360 table_offset = le32_to_cpu(hdr->jt_offset); in gfx_v7_0_init_cp_pg_table()4368 table_offset = le32_to_cpu(hdr->jt_offset); in gfx_v7_0_init_cp_pg_table()
186 uint32_t jt_offset; /* jt location */ member205 uint32_t jt_offset; /* jt location */ member
99 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset)); in radeon_ucode_print_gfx_hdr()149 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset)); in radeon_ucode_print_sdma_hdr()
6877 table_offset = le32_to_cpu(hdr->jt_offset); in cik_init_cp_pg_table()6883 table_offset = le32_to_cpu(hdr->jt_offset); in cik_init_cp_pg_table()6889 table_offset = le32_to_cpu(hdr->jt_offset); in cik_init_cp_pg_table()6895 table_offset = le32_to_cpu(hdr->jt_offset); in cik_init_cp_pg_table()6901 table_offset = le32_to_cpu(hdr->jt_offset); in cik_init_cp_pg_table()