Searched refs:ixSMC_SYSCON_RESET_CNTL (Results 1 – 11 of 11) sorted by relevance
| /linux-4.4.14/drivers/gpu/drm/amd/amdgpu/ |
| D | fiji_smc.c | 349 uint32_t val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
351 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);
568 val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); in fiji_smu_start_in_protection_mode()
570 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val); in fiji_smu_start_in_protection_mode()
585 val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); in fiji_smu_start_in_protection_mode()
587 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val); in fiji_smu_start_in_protection_mode()
674 val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); in fiji_smu_start_in_non_protection_mode()
676 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val); in fiji_smu_start_in_non_protection_mode()
691 val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); in fiji_smu_start_in_non_protection_mode()
693 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val); in fiji_smu_start_in_non_protection_mode()
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| D | tonga_smc.c | 349 uint32_t val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL);
351 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val);
570 val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); in tonga_smu_start_in_protection_mode()
572 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val); in tonga_smu_start_in_protection_mode()
587 val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); in tonga_smu_start_in_protection_mode()
589 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val); in tonga_smu_start_in_protection_mode()
675 val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); in tonga_smu_start_in_non_protection_mode()
677 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val); in tonga_smu_start_in_non_protection_mode()
692 val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); in tonga_smu_start_in_non_protection_mode()
694 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val); in tonga_smu_start_in_non_protection_mode()
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| D | ci_smc.c | 119 u32 tmp = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); in amdgpu_ci_start_smc()
122 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, tmp); in amdgpu_ci_start_smc()
127 u32 tmp = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); in amdgpu_ci_reset_smc()
130 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, tmp); in amdgpu_ci_reset_smc()
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| D | iceland_smc.c | 126 uint32_t val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); in iceland_start_smc()
129 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val); in iceland_start_smc()
134 uint32_t val = RREG32_SMC(ixSMC_SYSCON_RESET_CNTL); in iceland_reset_smc()
137 WREG32_SMC(ixSMC_SYSCON_RESET_CNTL, val); in iceland_reset_smc()
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| D | ci_dpm.c | 6546 RREG32_SMC(ixSMC_SYSCON_RESET_CNTL)); in ci_dpm_print_status()
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| /linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/smu/ |
| D | smu_7_0_0_d.h | 126 #define ixSMC_SYSCON_RESET_CNTL 0x80000000 macro
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| D | smu_7_1_1_d.h | 127 #define ixSMC_SYSCON_RESET_CNTL 0x80000000 macro
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| D | smu_7_1_2_d.h | 127 #define ixSMC_SYSCON_RESET_CNTL 0x80000000 macro
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| D | smu_7_1_3_d.h | 130 #define ixSMC_SYSCON_RESET_CNTL 0x80000000 macro
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| D | smu_7_0_1_d.h | 127 #define ixSMC_SYSCON_RESET_CNTL 0x80000000 macro
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| D | smu_7_1_0_d.h | 127 #define ixSMC_SYSCON_RESET_CNTL 0x80000000 macro
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