H A D | mISDNisar.c | 33 #include "isar.h" 51 waitforHIA(struct isar_hw *isar, int timeout) waitforHIA() argument 54 u8 val = isar->read_reg(isar->hw, ISAR_HIA); waitforHIA() 59 val = isar->read_reg(isar->hw, ISAR_HIA); waitforHIA() 61 pr_debug("%s: HIA after %dus\n", isar->name, timeout - t); waitforHIA() 67 * if msg is NULL use isar->buf 70 send_mbox(struct isar_hw *isar, u8 his, u8 creg, u8 len, u8 *msg) send_mbox() argument 72 if (!waitforHIA(isar, 1000)) send_mbox() 75 isar->write_reg(isar->hw, ISAR_CTRL_H, creg); send_mbox() 76 isar->write_reg(isar->hw, ISAR_CTRL_L, len); send_mbox() 77 isar->write_reg(isar->hw, ISAR_WADR, 0); send_mbox() 79 msg = isar->buf; send_mbox() 81 isar->write_fifo(isar->hw, ISAR_MBOX, msg, len); send_mbox() 82 if (isar->ch[0].bch.debug & DEBUG_HW_BFIFO) { send_mbox() 87 isar->log, 256, 1); send_mbox() 88 pr_debug("%s: %s %02x: %s\n", isar->name, send_mbox() 89 __func__, l, isar->log); send_mbox() 94 isar->write_reg(isar->hw, ISAR_HIS, his); send_mbox() 95 waitforHIA(isar, 1000); send_mbox() 101 * if msg is NULL use isar->buf 104 rcv_mbox(struct isar_hw *isar, u8 *msg) rcv_mbox() argument 107 msg = isar->buf; rcv_mbox() 108 isar->write_reg(isar->hw, ISAR_RADR, 0); rcv_mbox() 109 if (msg && isar->clsb) { rcv_mbox() 110 isar->read_fifo(isar->hw, ISAR_MBOX, msg, isar->clsb); rcv_mbox() 111 if (isar->ch[0].bch.debug & DEBUG_HW_BFIFO) { rcv_mbox() 114 while (l < (int)isar->clsb) { rcv_mbox() 115 hex_dump_to_buffer(msg + l, isar->clsb - l, 32, rcv_mbox() 116 1, isar->log, 256, 1); rcv_mbox() 117 pr_debug("%s: %s %02x: %s\n", isar->name, rcv_mbox() 118 __func__, l, isar->log); rcv_mbox() 123 isar->write_reg(isar->hw, ISAR_IIA, 0); rcv_mbox() 127 get_irq_infos(struct isar_hw *isar) get_irq_infos() argument 129 isar->iis = isar->read_reg(isar->hw, ISAR_IIS); get_irq_infos() 130 isar->cmsb = isar->read_reg(isar->hw, ISAR_CTRL_H); get_irq_infos() 131 isar->clsb = isar->read_reg(isar->hw, ISAR_CTRL_L); get_irq_infos() 132 pr_debug("%s: rcv_mbox(%02x,%02x,%d)\n", isar->name, get_irq_infos() 133 isar->iis, isar->cmsb, isar->clsb); get_irq_infos() 142 poll_mbox(struct isar_hw *isar, int maxdelay) poll_mbox() argument 147 irq = isar->read_reg(isar->hw, ISAR_IRQBIT); poll_mbox() 153 get_irq_infos(isar); poll_mbox() 154 rcv_mbox(isar, NULL); poll_mbox() 157 isar->name, isar->clsb, maxdelay - t); poll_mbox() 162 ISARVersion(struct isar_hw *isar) ISARVersion() argument 167 isar->write_reg(isar->hw, ISAR_IRQBIT, 0); ISARVersion() 168 isar->buf[0] = ISAR_MSG_HWVER; ISARVersion() 169 isar->buf[1] = 0; ISARVersion() 170 isar->buf[2] = 1; ISARVersion() 171 if (!send_mbox(isar, ISAR_HIS_VNR, 0, 3, NULL)) ISARVersion() 173 if (!poll_mbox(isar, 1000)) ISARVersion() 175 if (isar->iis == ISAR_IIS_VNR) { ISARVersion() 176 if (isar->clsb == 1) { ISARVersion() 177 ver = isar->buf[0] & 0xf; ISARVersion() 186 load_firmware(struct isar_hw *isar, const u8 *buf, int size) load_firmware() argument 188 u32 saved_debug = isar->ch[0].bch.debug; load_firmware() 201 if (1 != isar->version) { load_firmware() 203 isar->name, isar->version); load_firmware() 207 isar->ch[0].bch.debug &= ~DEBUG_HW_BFIFO; load_firmware() 209 isar->name, size / 2, size); load_firmware() 213 spin_lock_irqsave(isar->hwlock, flags); load_firmware() 214 isar->write_reg(isar->hw, ISAR_IRQBIT, 0); load_firmware() 215 spin_unlock_irqrestore(isar->hwlock, flags); load_firmware() 226 isar->name, size, cnt + left); load_firmware() 230 spin_lock_irqsave(isar->hwlock, flags); load_firmware() 231 if (!send_mbox(isar, ISAR_HIS_DKEY, blk_head.d_key & 0xff, load_firmware() 237 if (!poll_mbox(isar, 1000)) { load_firmware() 242 spin_unlock_irqrestore(isar->hwlock, flags); load_firmware() 243 if ((isar->iis != ISAR_IIS_DKEY) || isar->cmsb || isar->clsb) { load_firmware() 245 isar->iis, isar->cmsb, isar->clsb); load_firmware() 255 mp = isar->buf; load_firmware() 262 pr_debug("%s: load %3d words at %04x\n", isar->name, load_firmware() 271 spin_lock_irqsave(isar->hwlock, flags); load_firmware() 272 if (!send_mbox(isar, ISAR_HIS_FIRM, 0, nom, NULL)) { load_firmware() 277 if (!poll_mbox(isar, 1000)) { load_firmware() 282 spin_unlock_irqrestore(isar->hwlock, flags); load_firmware() 283 if ((isar->iis != ISAR_IIS_FIRM) || load_firmware() 284 isar->cmsb || isar->clsb) { load_firmware() 286 isar->iis, isar->cmsb, isar->clsb); load_firmware() 292 isar->name, blk_head.len); load_firmware() 294 isar->ch[0].bch.debug = saved_debug; load_firmware() 299 isar->buf[0] = 0xff; load_firmware() 300 isar->buf[1] = 0xfe; load_firmware() 301 isar->bstat = 0; load_firmware() 302 spin_lock_irqsave(isar->hwlock, flags); load_firmware() 303 if (!send_mbox(isar, ISAR_HIS_STDSP, 0, 2, NULL)) { load_firmware() 308 if (!poll_mbox(isar, 1000)) { load_firmware() 313 if ((isar->iis != ISAR_IIS_STDSP) || isar->cmsb || isar->clsb) { load_firmware() 315 isar->iis, isar->cmsb, isar->clsb); load_firmware() 319 pr_debug("%s: ISAR start dsp success\n", isar->name); load_firmware() 323 isar->write_reg(isar->hw, ISAR_IRQBIT, ISAR_IRQSTA); load_firmware() 324 spin_unlock_irqrestore(isar->hwlock, flags); load_firmware() 326 while ((!isar->bstat) && cnt) { load_firmware() 336 isar->name, isar->bstat); load_firmware() 341 isar->iis = 0; load_firmware() 342 spin_lock_irqsave(isar->hwlock, flags); load_firmware() 343 if (!send_mbox(isar, ISAR_HIS_DIAG, ISAR_CTRL_STST, 0, NULL)) { load_firmware() 348 spin_unlock_irqrestore(isar->hwlock, flags); load_firmware() 350 while ((isar->iis != ISAR_IIS_DIAG) && cnt) { load_firmware() 360 if ((isar->cmsb == ISAR_CTRL_STST) && (isar->clsb == 1) load_firmware() 361 && (isar->buf[0] == 0)) load_firmware() 362 pr_debug("%s: ISAR selftest OK\n", isar->name); load_firmware() 365 isar->cmsb, isar->clsb, isar->buf[0]); load_firmware() 369 spin_lock_irqsave(isar->hwlock, flags); load_firmware() 370 isar->iis = 0; load_firmware() 371 if (!send_mbox(isar, ISAR_HIS_DIAG, ISAR_CTRL_SWVER, 0, NULL)) { load_firmware() 376 spin_unlock_irqrestore(isar->hwlock, flags); load_firmware() 378 while ((isar->iis != ISAR_IIS_DIAG) && cnt) { load_firmware() 388 if ((isar->cmsb == ISAR_CTRL_SWVER) && (isar->clsb == 1)) { load_firmware() 390 isar->name, isar->buf[0]); load_firmware() 393 " cnt(%d)\n", isar->name, isar->cmsb, load_firmware() 394 isar->clsb, cnt); load_firmware() 399 spin_lock_irqsave(isar->hwlock, flags); load_firmware() 400 isar_setup(isar); load_firmware() 401 spin_unlock_irqrestore(isar->hwlock, flags); load_firmware() 404 spin_lock_irqsave(isar->hwlock, flags); load_firmware() 406 isar->ch[0].bch.debug = saved_debug; load_firmware() 409 isar->write_reg(isar->hw, ISAR_IRQBIT, 0); load_firmware() 410 spin_unlock_irqrestore(isar->hwlock, flags); load_firmware() 673 sel_bch_isar(struct isar_hw *isar, u8 dpath) sel_bch_isar() argument 675 struct isar_ch *base = &isar->ch[0]; sel_bch_isar() 734 check_send(struct isar_hw *isar, u8 rdm) check_send() argument 738 pr_debug("%s: rdm %x\n", isar->name, rdm); check_send() 740 ch = sel_bch_isar(isar, 1); check_send() 750 ch = sel_bch_isar(isar, 2); check_send() 1050 mISDNisar_irq(struct isar_hw *isar) mISDNisar_irq() argument 1054 get_irq_infos(isar); mISDNisar_irq() 1055 switch (isar->iis & ISAR_IIS_MSCMSD) { mISDNisar_irq() 1057 ch = sel_bch_isar(isar, isar->iis >> 6); mISDNisar_irq() 1062 isar->name, isar->iis, isar->cmsb, mISDNisar_irq() 1063 isar->clsb); mISDNisar_irq() 1064 isar->write_reg(isar->hw, ISAR_IIA, 0); mISDNisar_irq() 1068 isar->write_reg(isar->hw, ISAR_IIA, 0); mISDNisar_irq() 1069 isar->bstat |= isar->cmsb; mISDNisar_irq() 1070 check_send(isar, isar->cmsb); mISDNisar_irq() 1074 ch = sel_bch_isar(isar, isar->iis >> 6); mISDNisar_irq() 1076 if (isar->cmsb == BSTEV_TBO) mISDNisar_irq() 1078 if (isar->cmsb == BSTEV_RBO) mISDNisar_irq() 1083 isar->name, isar->iis >> 6, isar->cmsb); mISDNisar_irq() 1084 isar->write_reg(isar->hw, ISAR_IIA, 0); mISDNisar_irq() 1087 ch = sel_bch_isar(isar, isar->iis >> 6); mISDNisar_irq() 1089 rcv_mbox(isar, NULL); mISDNisar_irq() 1091 isar_pump_statev_modem(ch, isar->cmsb); mISDNisar_irq() 1093 isar_pump_statev_fax(ch, isar->cmsb); mISDNisar_irq() 1096 tt = isar->cmsb | 0x30; mISDNisar_irq() 1109 isar->name, ch->bch.state, mISDNisar_irq() 1110 isar->cmsb); mISDNisar_irq() 1113 isar->name, isar->iis, isar->cmsb, mISDNisar_irq() 1114 isar->clsb); mISDNisar_irq() 1115 isar->write_reg(isar->hw, ISAR_IIA, 0); mISDNisar_irq() 1119 ch = sel_bch_isar(isar, isar->iis >> 6); mISDNisar_irq() 1121 rcv_mbox(isar, NULL); mISDNisar_irq() 1125 isar->name, isar->iis, isar->cmsb, mISDNisar_irq() 1126 isar->clsb); mISDNisar_irq() 1127 isar->write_reg(isar->hw, ISAR_IIA, 0); mISDNisar_irq() 1133 rcv_mbox(isar, NULL); mISDNisar_irq() 1136 rcv_mbox(isar, NULL); mISDNisar_irq() 1137 pr_debug("%s: invalid msg his:%x\n", isar->name, isar->cmsb); mISDNisar_irq() 1140 rcv_mbox(isar, NULL); mISDNisar_irq() 1142 isar->name, isar->iis, isar->cmsb, isar->clsb); mISDNisar_irq() 1459 isar_setup(struct isar_hw *isar) isar_setup() argument 1468 send_mbox(isar, (i ? ISAR_HIS_DPS2 : ISAR_HIS_DPS1) | isar_setup() 1470 isar->ch[i].mml = msg; isar_setup() 1471 isar->ch[i].bch.state = 0; isar_setup() 1472 isar->ch[i].dpath = i + 1; isar_setup() 1473 modeisar(&isar->ch[i], ISDN_P_NONE); isar_setup() 1548 pr_debug("%s: isar: new mod\n", ich->is->name); isar_l2l1() 1612 free_isar(struct isar_hw *isar) free_isar() argument 1614 modeisar(&isar->ch[0], ISDN_P_NONE); free_isar() 1615 modeisar(&isar->ch[1], ISDN_P_NONE); free_isar() 1616 del_timer(&isar->ch[0].ftimer); free_isar() 1617 del_timer(&isar->ch[1].ftimer); free_isar() 1618 test_and_clear_bit(FLG_INITIALIZED, &isar->ch[0].bch.Flags); free_isar() 1619 test_and_clear_bit(FLG_INITIALIZED, &isar->ch[1].bch.Flags); free_isar() 1623 init_isar(struct isar_hw *isar) init_isar() argument 1628 isar->version = ISARVersion(isar); init_isar() 1629 if (isar->ch[0].bch.debug & DEBUG_HW) init_isar() 1631 isar->name, isar->version, 3 - cnt); init_isar() 1632 if (isar->version == 1) init_isar() 1634 isar->ctrl(isar->hw, HW_RESET_REQ, 0); init_isar() 1636 if (isar->version != 1) init_isar() 1638 isar->ch[0].ftimer.function = &ftimer_handler; init_isar() 1639 isar->ch[0].ftimer.data = (long)&isar->ch[0]; init_isar() 1640 init_timer(&isar->ch[0].ftimer); init_isar() 1641 test_and_set_bit(FLG_INITIALIZED, &isar->ch[0].bch.Flags); init_isar() 1642 isar->ch[1].ftimer.function = &ftimer_handler; init_isar() 1643 isar->ch[1].ftimer.data = (long)&isar->ch[1]; init_isar() 1644 init_timer(&isar->ch[1].ftimer); init_isar() 1645 test_and_set_bit(FLG_INITIALIZED, &isar->ch[1].bch.Flags); init_isar() 1650 isar_open(struct isar_hw *isar, struct channel_req *rq) isar_open() argument 1658 bch = &isar->ch[rq->adr.channel - 1].bch; isar_open() 1667 mISDNisar_init(struct isar_hw *isar, void *hw) mISDNisar_init() argument 1671 isar->hw = hw; mISDNisar_init() 1673 isar->ch[i].bch.nr = i + 1; mISDNisar_init() 1674 mISDN_initbchannel(&isar->ch[i].bch, MAX_DATA_MEM, 32); mISDNisar_init() 1675 isar->ch[i].bch.ch.nr = i + 1; mISDNisar_init() 1676 isar->ch[i].bch.ch.send = &isar_l2l1; mISDNisar_init() 1677 isar->ch[i].bch.ch.ctrl = isar_bctrl; mISDNisar_init() 1678 isar->ch[i].bch.hw = hw; mISDNisar_init() 1679 isar->ch[i].is = isar; mISDNisar_init() 1682 isar->init = &init_isar; mISDNisar_init() 1683 isar->release = &free_isar; mISDNisar_init() 1684 isar->firmware = &load_firmware; mISDNisar_init() 1685 isar->open = &isar_open; mISDNisar_init()
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