Searched refs:intel_crtc (Results 1 - 27 of 27) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/i915/
H A Dintel_hdmi.c195 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); ibx_write_infoframe() local
196 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); ibx_write_infoframe()
210 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); ibx_write_infoframe()
215 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); ibx_write_infoframe()
230 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); ibx_infoframe_enabled() local
232 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); ibx_infoframe_enabled()
253 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); cpt_write_infoframe() local
254 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); cpt_write_infoframe()
271 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); cpt_write_infoframe()
276 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); cpt_write_infoframe()
291 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); cpt_infoframe_enabled() local
292 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); cpt_infoframe_enabled()
310 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); vlv_write_infoframe() local
311 int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); vlv_write_infoframe()
325 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); vlv_write_infoframe()
330 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); vlv_write_infoframe()
345 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); vlv_infoframe_enabled() local
347 int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); vlv_infoframe_enabled()
368 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); hsw_write_infoframe() local
369 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; hsw_write_infoframe()
403 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); hsw_infoframe_enabled() local
404 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); hsw_infoframe_enabled()
455 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); intel_hdmi_set_avi_infoframe() local
467 if (intel_crtc->config->limited_color_range) intel_hdmi_set_avi_infoframe()
635 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); intel_hdmi_set_gcp_infoframe()
666 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); ibx_set_infoframes() local
669 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); ibx_set_infoframes()
718 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); cpt_set_infoframes() local
720 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); cpt_set_infoframes()
761 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); vlv_set_infoframes() local
763 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); vlv_set_infoframes()
812 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); hsw_set_infoframes() local
814 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); hsw_set_infoframes()
844 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); intel_hdmi_prepare()
956 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); intel_enable_hdmi_audio()
968 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); g4x_enable_hdmi()
989 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); ibx_enable_hdmi()
1038 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); cpt_enable_hdmi()
1096 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); intel_disable_hdmi()
1132 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); g4x_disable_hdmi()
1142 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); pch_disable_hdmi()
1550 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); intel_hdmi_pre_enable() local
1551 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; intel_hdmi_pre_enable()
1556 intel_crtc->config->has_hdmi_sink, intel_hdmi_pre_enable()
1566 struct intel_crtc *intel_crtc = vlv_hdmi_pre_enable() local
1568 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; vlv_hdmi_pre_enable()
1570 int pipe = intel_crtc->pipe; vlv_hdmi_pre_enable()
1600 intel_crtc->config->has_hdmi_sink, vlv_hdmi_pre_enable()
1613 struct intel_crtc *intel_crtc = vlv_hdmi_pre_pll_enable() local
1616 int pipe = intel_crtc->pipe; vlv_hdmi_pre_pll_enable()
1646 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); chv_data_lane_soft_reset()
1690 struct intel_crtc *intel_crtc = chv_hdmi_pre_pll_enable() local
1693 enum pipe pipe = intel_crtc->pipe; chv_hdmi_pre_pll_enable()
1801 struct intel_crtc *intel_crtc = vlv_hdmi_post_disable() local
1804 int pipe = intel_crtc->pipe; vlv_hdmi_post_disable()
1832 struct intel_crtc *intel_crtc = chv_hdmi_pre_enable() local
1834 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; chv_hdmi_pre_enable()
1836 int pipe = intel_crtc->pipe; chv_hdmi_pre_enable()
1860 if (intel_crtc->config->port_clock > 270000) chv_hdmi_pre_enable()
1862 else if (intel_crtc->config->port_clock > 135000) chv_hdmi_pre_enable()
1864 else if (intel_crtc->config->port_clock > 67500) chv_hdmi_pre_enable()
1866 else if (intel_crtc->config->port_clock > 33750) chv_hdmi_pre_enable()
1969 intel_crtc->config->has_hdmi_sink, chv_hdmi_pre_enable()
H A Dintel_display.c88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
105 static void vlv_prepare_pll(struct intel_crtc *crtc,
107 static void chv_prepare_pll(struct intel_crtc *crtc,
111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
510 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) intel_pipe_has_type()
951 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); vlv_find_best_dpll()
1005 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); chv_find_best_dpll()
1068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_crtc_active() local
1079 * FIXME: The intel_crtc->active here should be switched to intel_crtc_active()
1083 return intel_crtc->active && crtc->primary->state->fb && intel_crtc_active()
1084 intel_crtc->config->base.adjusted_mode.crtc_clock; intel_crtc_active()
1091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_pipe_to_cpu_transcoder() local
1093 return intel_crtc->config->cpu_transcoder; intel_pipe_to_cpu_transcoder()
1131 static void intel_wait_for_pipe_off(struct intel_crtc *crtc) intel_wait_for_pipe_off()
1190 intel_crtc_to_shared_dpll(struct intel_crtc *crtc) intel_crtc_to_shared_dpll()
1598 static void vlv_enable_pll(struct intel_crtc *crtc, vlv_enable_pll()
1637 static void chv_enable_pll(struct intel_crtc *crtc, chv_enable_pll()
1678 struct intel_crtc *crtc; intel_num_dvo_pipes()
1688 static void i9xx_enable_pll(struct intel_crtc *crtc) i9xx_enable_pll()
1763 static void i9xx_disable_pll(struct intel_crtc *crtc) i9xx_disable_pll()
1866 static void intel_prepare_shared_dpll(struct intel_crtc *crtc) intel_prepare_shared_dpll()
1893 static void intel_enable_shared_dpll(struct intel_crtc *crtc) intel_enable_shared_dpll()
1923 static void intel_disable_shared_dpll(struct intel_crtc *crtc) intel_disable_shared_dpll()
1965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); ironlake_enable_pch_transcoder() local
1973 intel_crtc_to_shared_dpll(intel_crtc)); ironlake_enable_pch_transcoder()
1999 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) ironlake_enable_pch_transcoder()
2008 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) ironlake_enable_pch_transcoder()
2105 static void intel_enable_pipe(struct intel_crtc *crtc) intel_enable_pipe()
2169 static void intel_disable_pipe(struct intel_crtc *crtc) intel_disable_pipe()
2528 intel_alloc_initial_plane_obj(struct intel_crtc *crtc, intel_alloc_initial_plane_obj()
2601 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, intel_find_initial_plane_obj() argument
2604 struct drm_device *dev = intel_crtc->base.dev; intel_find_initial_plane_obj()
2607 struct intel_crtc *i; intel_find_initial_plane_obj()
2609 struct drm_plane *primary = intel_crtc->base.primary; intel_find_initial_plane_obj()
2611 struct drm_crtc_state *crtc_state = intel_crtc->base.state; intel_find_initial_plane_obj()
2618 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { intel_find_initial_plane_obj()
2632 if (c == &intel_crtc->base) for_each_crtc()
2658 intel_pre_disable_primary(&intel_crtc->base);
2659 intel_plane->disable_plane(primary, &intel_crtc->base);
2680 primary->crtc = primary->state->crtc = &intel_crtc->base;
2681 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); i9xx_update_primary_plane() local
2695 int plane = intel_crtc->plane; i9xx_update_primary_plane()
2722 if (intel_crtc->pipe == PIPE_B) i9xx_update_primary_plane()
2729 ((intel_crtc->config->pipe_src_h - 1) << 16) | i9xx_update_primary_plane()
2730 (intel_crtc->config->pipe_src_w - 1)); i9xx_update_primary_plane()
2734 ((intel_crtc->config->pipe_src_h - 1) << 16) | i9xx_update_primary_plane()
2735 (intel_crtc->config->pipe_src_w - 1)); i9xx_update_primary_plane()
2776 intel_crtc->dspaddr_offset = i9xx_update_primary_plane()
2781 linear_offset -= intel_crtc->dspaddr_offset; i9xx_update_primary_plane()
2783 intel_crtc->dspaddr_offset = linear_offset; i9xx_update_primary_plane()
2789 x += (intel_crtc->config->pipe_src_w - 1); i9xx_update_primary_plane()
2790 y += (intel_crtc->config->pipe_src_h - 1); i9xx_update_primary_plane()
2795 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + i9xx_update_primary_plane()
2796 (intel_crtc->config->pipe_src_w - 1) * pixel_size; i9xx_update_primary_plane()
2799 intel_crtc->adjusted_x = x; i9xx_update_primary_plane()
2800 intel_crtc->adjusted_y = y; i9xx_update_primary_plane()
2807 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); i9xx_update_primary_plane()
2821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); ironlake_update_primary_plane() local
2825 int plane = intel_crtc->plane; ironlake_update_primary_plane()
2881 intel_crtc->dspaddr_offset = ironlake_update_primary_plane()
2886 linear_offset -= intel_crtc->dspaddr_offset; ironlake_update_primary_plane()
2891 x += (intel_crtc->config->pipe_src_w - 1); ironlake_update_primary_plane()
2892 y += (intel_crtc->config->pipe_src_h - 1); ironlake_update_primary_plane()
2897 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + ironlake_update_primary_plane()
2898 (intel_crtc->config->pipe_src_w - 1) * pixel_size; ironlake_update_primary_plane()
2902 intel_crtc->adjusted_x = x; ironlake_update_primary_plane()
2903 intel_crtc->adjusted_y = y; ironlake_update_primary_plane()
2909 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); ironlake_update_primary_plane()
2979 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) skl_detach_scaler() argument
2981 struct drm_device *dev = intel_crtc->base.dev; skl_detach_scaler()
2984 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); skl_detach_scaler()
2985 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); skl_detach_scaler()
2986 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); skl_detach_scaler()
2992 static void skl_detach_scalers(struct intel_crtc *intel_crtc) skl_detach_scalers() argument
2997 scaler_state = &intel_crtc->config->scaler_state; skl_detach_scalers()
3000 for (i = 0; i < intel_crtc->num_scalers; i++) { skl_detach_scalers()
3002 skl_detach_scaler(intel_crtc, i); skl_detach_scalers()
3093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); skylake_update_primary_plane() local
3097 int pipe = intel_crtc->pipe; skylake_update_primary_plane()
3103 struct intel_crtc_state *crtc_state = intel_crtc->config; skylake_update_primary_plane()
3164 intel_crtc->adjusted_x = x_offset; skylake_update_primary_plane()
3165 intel_crtc->adjusted_y = y_offset; skylake_update_primary_plane()
3213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); for_each_crtc() local
3214 enum plane plane = intel_crtc->plane; for_each_crtc()
3339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_crtc_has_pending_flip() local
3343 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) intel_crtc_has_pending_flip()
3353 static void intel_update_pipe_config(struct intel_crtc *crtc, intel_update_pipe_config()
3402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_fdi_normal_train() local
3403 int pipe = intel_crtc->pipe; intel_fdi_normal_train()
3444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); ironlake_fdi_link_train() local
3445 int pipe = intel_crtc->pipe; ironlake_fdi_link_train()
3465 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); ironlake_fdi_link_train()
3544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); gen6_fdi_link_train() local
3545 int pipe = intel_crtc->pipe; gen6_fdi_link_train()
3563 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); gen6_fdi_link_train()
3676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); ivb_manual_fdi_link_train() local
3677 int pipe = intel_crtc->pipe; ivb_manual_fdi_link_train()
3714 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); ivb_manual_fdi_link_train()
3790 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) ironlake_fdi_pll_enable() argument
3792 struct drm_device *dev = intel_crtc->base.dev; ironlake_fdi_pll_enable()
3794 int pipe = intel_crtc->pipe; ironlake_fdi_pll_enable()
3802 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); ironlake_fdi_pll_enable()
3827 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) ironlake_fdi_pll_disable() argument
3829 struct drm_device *dev = intel_crtc->base.dev; ironlake_fdi_pll_disable()
3831 int pipe = intel_crtc->pipe; ironlake_fdi_pll_disable()
3860 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); ironlake_fdi_disable() local
3861 int pipe = intel_crtc->pipe; ironlake_fdi_disable()
3910 struct intel_crtc *crtc; intel_has_pending_fb_unpin()
3932 static void page_flip_completed(struct intel_crtc *intel_crtc) page_flip_completed() argument
3934 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); page_flip_completed()
3935 struct intel_unpin_work *work = intel_crtc->unpin_work; page_flip_completed()
3939 intel_crtc->unpin_work = NULL; page_flip_completed()
3942 drm_send_vblank_event(intel_crtc->base.dev, page_flip_completed()
3943 intel_crtc->pipe, page_flip_completed()
3946 drm_crtc_vblank_put(&intel_crtc->base); page_flip_completed()
3951 trace_i915_flip_complete(intel_crtc->plane, page_flip_completed()
3964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_crtc_wait_for_pending_flips() local
3967 if (intel_crtc->unpin_work) { intel_crtc_wait_for_pending_flips()
3969 page_flip_completed(intel_crtc); intel_crtc_wait_for_pending_flips()
4070 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, ironlake_pch_transcoder_set_timings()
4115 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) ivybridge_update_fdi_bc_bifurcation() argument
4117 struct drm_device *dev = intel_crtc->base.dev; ivybridge_update_fdi_bc_bifurcation()
4119 switch (intel_crtc->pipe) { ivybridge_update_fdi_bc_bifurcation()
4123 if (intel_crtc->config->fdi_lanes > 2) ivybridge_update_fdi_bc_bifurcation()
4150 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); ironlake_pch_enable() local
4151 int pipe = intel_crtc->pipe; ironlake_pch_enable()
4157 ivybridge_update_fdi_bc_bifurcation(intel_crtc); ironlake_pch_enable()
4175 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) ironlake_pch_enable()
4189 intel_enable_shared_dpll(intel_crtc); ironlake_pch_enable()
4193 ironlake_pch_transcoder_set_timings(intel_crtc, pipe); ironlake_pch_enable()
4198 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { ironlake_pch_enable()
4237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); lpt_pch_enable() local
4238 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; lpt_pch_enable()
4245 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); lpt_pch_enable()
4250 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, intel_get_shared_dpll()
4378 struct intel_crtc *intel_crtc = skl_update_scaler() local
4403 intel_crtc->pipe, scaler_user, *scaler_id, skl_update_scaler()
4418 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); skl_update_scaler()
4426 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, skl_update_scaler()
4443 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); skl_update_scaler_crtc() local
4447 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); skl_update_scaler_crtc()
4469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); skl_update_scaler_plane() local
4478 intel_plane->base.base.id, intel_crtc->pipe, skl_update_scaler_plane()
4523 static void skylake_scaler_disable(struct intel_crtc *crtc) skylake_scaler_disable()
4531 static void skylake_pfit_enable(struct intel_crtc *crtc) skylake_pfit_enable()
4559 static void ironlake_pfit_enable(struct intel_crtc *crtc) ironlake_pfit_enable()
4580 void hsw_enable_ips(struct intel_crtc *crtc) hsw_enable_ips()
4613 void hsw_disable_ips(struct intel_crtc *crtc) hsw_disable_ips()
4643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_crtc_load_lut() local
4644 enum pipe pipe = intel_crtc->pipe; intel_crtc_load_lut()
4653 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) intel_crtc_load_lut()
4662 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && intel_crtc_load_lut()
4665 hsw_disable_ips(intel_crtc); intel_crtc_load_lut()
4678 (intel_crtc->lut_r[i] << 16) | intel_crtc_load_lut()
4679 (intel_crtc->lut_g[i] << 8) | intel_crtc_load_lut()
4680 intel_crtc->lut_b[i]); intel_crtc_load_lut()
4684 hsw_enable_ips(intel_crtc); intel_crtc_load_lut()
4687 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) intel_crtc_dpms_overlay_disable() argument
4689 if (intel_crtc->overlay) { intel_crtc_dpms_overlay_disable()
4690 struct drm_device *dev = intel_crtc->base.dev; intel_crtc_dpms_overlay_disable()
4695 (void) intel_overlay_switch_off(intel_crtc->overlay); intel_crtc_dpms_overlay_disable()
4720 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_post_enable_primary() local
4721 int pipe = intel_crtc->pipe; intel_post_enable_primary()
4737 hsw_enable_ips(intel_crtc); intel_post_enable_primary()
4769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_pre_disable_primary() local
4770 int pipe = intel_crtc->pipe; intel_pre_disable_primary()
4802 hsw_disable_ips(intel_crtc); intel_pre_disable_primary()
4805 static void intel_post_plane_update(struct intel_crtc *crtc) intel_post_plane_update()
4836 static void intel_pre_plane_update(struct intel_crtc *crtc) intel_pre_plane_update()
4874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_crtc_disable_planes() local
4876 int pipe = intel_crtc->pipe; intel_crtc_disable_planes()
4878 intel_crtc_dpms_overlay_disable(intel_crtc); intel_crtc_disable_planes()
4895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); ironlake_crtc_enable() local
4897 int pipe = intel_crtc->pipe; ironlake_crtc_enable()
4899 if (WARN_ON(intel_crtc->active)) ironlake_crtc_enable()
4902 if (intel_crtc->config->has_pch_encoder) ironlake_crtc_enable()
4903 intel_prepare_shared_dpll(intel_crtc); ironlake_crtc_enable()
4905 if (intel_crtc->config->has_dp_encoder) ironlake_crtc_enable()
4906 intel_dp_set_m_n(intel_crtc, M1_N1); ironlake_crtc_enable()
4908 intel_set_pipe_timings(intel_crtc); ironlake_crtc_enable()
4910 if (intel_crtc->config->has_pch_encoder) { ironlake_crtc_enable()
4911 intel_cpu_transcoder_set_m_n(intel_crtc, ironlake_crtc_enable()
4912 &intel_crtc->config->fdi_m_n, NULL); ironlake_crtc_enable()
4917 intel_crtc->active = true; ironlake_crtc_enable()
4926 if (intel_crtc->config->has_pch_encoder) { for_each_encoder_on_crtc()
4930 ironlake_fdi_pll_enable(intel_crtc); for_each_encoder_on_crtc()
4936 ironlake_pfit_enable(intel_crtc);
4945 intel_enable_pipe(intel_crtc);
4947 if (intel_crtc->config->has_pch_encoder)
4957 cpt_verify_modeset(dev, intel_crtc->pipe);
4961 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) hsw_crtc_supports_ips()
4970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); haswell_crtc_enable() local
4972 int pipe = intel_crtc->pipe, hsw_workaround_pipe; haswell_crtc_enable()
4975 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); haswell_crtc_enable()
4977 if (WARN_ON(intel_crtc->active)) haswell_crtc_enable()
4980 if (intel_crtc_to_shared_dpll(intel_crtc)) haswell_crtc_enable()
4981 intel_enable_shared_dpll(intel_crtc); haswell_crtc_enable()
4983 if (intel_crtc->config->has_dp_encoder) haswell_crtc_enable()
4984 intel_dp_set_m_n(intel_crtc, M1_N1); haswell_crtc_enable()
4986 intel_set_pipe_timings(intel_crtc); haswell_crtc_enable()
4988 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { haswell_crtc_enable()
4989 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), haswell_crtc_enable()
4990 intel_crtc->config->pixel_multiplier - 1); haswell_crtc_enable()
4993 if (intel_crtc->config->has_pch_encoder) { haswell_crtc_enable()
4994 intel_cpu_transcoder_set_m_n(intel_crtc, haswell_crtc_enable()
4995 &intel_crtc->config->fdi_m_n, NULL); haswell_crtc_enable()
5002 intel_crtc->active = true; haswell_crtc_enable()
5012 if (intel_crtc->config->has_pch_encoder) {
5019 intel_ddi_enable_pipe_clock(intel_crtc);
5022 skylake_pfit_enable(intel_crtc);
5024 ironlake_pfit_enable(intel_crtc);
5037 intel_enable_pipe(intel_crtc);
5039 if (intel_crtc->config->has_pch_encoder)
5042 if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
5062 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) ironlake_pfit_disable()
5081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); ironlake_crtc_disable() local
5083 int pipe = intel_crtc->pipe; ironlake_crtc_disable()
5092 if (intel_crtc->config->has_pch_encoder) ironlake_crtc_disable()
5095 intel_disable_pipe(intel_crtc); ironlake_crtc_disable()
5097 ironlake_pfit_disable(intel_crtc, false); ironlake_crtc_disable()
5099 if (intel_crtc->config->has_pch_encoder) ironlake_crtc_disable()
5106 if (intel_crtc->config->has_pch_encoder) { for_each_encoder_on_crtc()
5124 ironlake_fdi_pll_disable(intel_crtc); for_each_encoder_on_crtc()
5132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); haswell_crtc_disable() local
5134 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; haswell_crtc_disable()
5135 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); haswell_crtc_disable()
5145 if (intel_crtc->config->has_pch_encoder)
5148 intel_disable_pipe(intel_crtc);
5150 if (intel_crtc->config->dp_encoder_is_mst)
5157 skylake_scaler_disable(intel_crtc);
5159 ironlake_pfit_disable(intel_crtc, false);
5162 intel_ddi_disable_pipe_clock(intel_crtc);
5164 if (intel_crtc->config->has_pch_encoder) {
5174 static void i9xx_pfit_enable(struct intel_crtc *crtc) i9xx_pfit_enable()
5302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); get_crtc_power_domains() local
5303 enum pipe pipe = intel_crtc->pipe; get_crtc_power_domains()
5314 if (intel_crtc->config->pch_pfit.enabled || get_crtc_power_domains()
5315 intel_crtc->config->pch_pfit.force_thru) get_crtc_power_domains()
5327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); modeset_get_crtc_power_domains() local
5331 old_domains = intel_crtc->enabled_power_domains; modeset_get_crtc_power_domains()
5332 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc); modeset_get_crtc_power_domains()
6023 struct intel_crtc *intel_crtc; intel_mode_max_pixclk() local
6027 for_each_intel_crtc(dev, intel_crtc) { for_each_intel_crtc()
6028 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); for_each_intel_crtc()
6139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); valleyview_crtc_enable() local
6141 int pipe = intel_crtc->pipe; valleyview_crtc_enable()
6144 if (WARN_ON(intel_crtc->active)) valleyview_crtc_enable()
6147 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI); valleyview_crtc_enable()
6149 if (intel_crtc->config->has_dp_encoder) valleyview_crtc_enable()
6150 intel_dp_set_m_n(intel_crtc, M1_N1); valleyview_crtc_enable()
6152 intel_set_pipe_timings(intel_crtc); valleyview_crtc_enable()
6161 i9xx_set_pipeconf(intel_crtc); valleyview_crtc_enable()
6163 intel_crtc->active = true; valleyview_crtc_enable()
6173 chv_prepare_pll(intel_crtc, intel_crtc->config); for_each_encoder_on_crtc()
6174 chv_enable_pll(intel_crtc, intel_crtc->config); for_each_encoder_on_crtc()
6176 vlv_prepare_pll(intel_crtc, intel_crtc->config); for_each_encoder_on_crtc()
6177 vlv_enable_pll(intel_crtc, intel_crtc->config); for_each_encoder_on_crtc()
6185 i9xx_pfit_enable(intel_crtc);
6189 intel_enable_pipe(intel_crtc);
6198 static void i9xx_set_pll_dividers(struct intel_crtc *crtc) i9xx_set_pll_dividers()
6211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); i9xx_crtc_enable() local
6213 int pipe = intel_crtc->pipe; i9xx_crtc_enable()
6215 if (WARN_ON(intel_crtc->active)) i9xx_crtc_enable()
6218 i9xx_set_pll_dividers(intel_crtc); i9xx_crtc_enable()
6220 if (intel_crtc->config->has_dp_encoder) i9xx_crtc_enable()
6221 intel_dp_set_m_n(intel_crtc, M1_N1); i9xx_crtc_enable()
6223 intel_set_pipe_timings(intel_crtc); i9xx_crtc_enable()
6225 i9xx_set_pipeconf(intel_crtc); i9xx_crtc_enable()
6227 intel_crtc->active = true; i9xx_crtc_enable()
6236 i9xx_enable_pll(intel_crtc); i9xx_crtc_enable()
6238 i9xx_pfit_enable(intel_crtc); i9xx_crtc_enable()
6243 intel_enable_pipe(intel_crtc); i9xx_crtc_enable()
6252 static void i9xx_pfit_disable(struct intel_crtc *crtc) i9xx_pfit_disable()
6271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); i9xx_crtc_disable() local
6273 int pipe = intel_crtc->pipe; i9xx_crtc_disable()
6289 intel_disable_pipe(intel_crtc); i9xx_crtc_disable()
6291 i9xx_pfit_disable(intel_crtc); i9xx_crtc_disable()
6297 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) { for_each_encoder_on_crtc()
6303 i9xx_disable_pll(intel_crtc); for_each_encoder_on_crtc()
6316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_crtc_disable_noatomic() local
6321 if (!intel_crtc->active) intel_crtc_disable_noatomic()
6333 intel_crtc->active = false; intel_crtc_disable_noatomic()
6335 intel_disable_shared_dpll(intel_crtc); intel_crtc_disable_noatomic()
6337 domains = intel_crtc->enabled_power_domains; intel_crtc_disable_noatomic()
6340 intel_crtc->enabled_power_domains = 0; intel_crtc_disable_noatomic()
6499 struct intel_crtc *other_crtc; ironlake_check_fdi_lanes()
6567 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, ironlake_fdi_compute_config() argument
6570 struct drm_device *dev = intel_crtc->base.dev; ironlake_fdi_compute_config()
6595 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, ironlake_fdi_compute_config()
6596 intel_crtc->pipe, pipe_config); ironlake_fdi_compute_config()
6634 static void hsw_compute_ips_config(struct intel_crtc *crtc, hsw_compute_ips_config()
6645 static int intel_crtc_compute_config(struct intel_crtc *crtc, intel_crtc_compute_config()
7172 static void i9xx_update_pll_dividers(struct intel_crtc *crtc, i9xx_update_pll_dividers()
7230 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, intel_pch_transcoder_set_m_n()
7243 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, intel_cpu_transcoder_set_m_n()
7277 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) intel_dp_set_m_n()
7302 static void vlv_compute_dpll(struct intel_crtc *crtc, vlv_compute_dpll()
7325 static void vlv_prepare_pll(struct intel_crtc *crtc, vlv_prepare_pll()
7416 static void chv_compute_dpll(struct intel_crtc *crtc, chv_compute_dpll()
7429 static void chv_prepare_pll(struct intel_crtc *crtc, chv_prepare_pll()
7546 struct intel_crtc *crtc = vlv_force_pll_on()
7581 static void i9xx_compute_dpll(struct intel_crtc *crtc, i9xx_compute_dpll()
7658 static void i8xx_compute_dpll(struct intel_crtc *crtc, i8xx_compute_dpll()
7696 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) intel_set_pipe_timings() argument
7698 struct drm_device *dev = intel_crtc->base.dev; intel_set_pipe_timings()
7700 enum pipe pipe = intel_crtc->pipe; intel_set_pipe_timings()
7701 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; intel_set_pipe_timings()
7702 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; intel_set_pipe_timings()
7716 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) intel_set_pipe_timings()
7760 ((intel_crtc->config->pipe_src_w - 1) << 16) | intel_set_pipe_timings()
7761 (intel_crtc->config->pipe_src_h - 1)); intel_set_pipe_timings()
7764 static void intel_get_pipe_timings(struct intel_crtc *crtc, intel_get_pipe_timings()
7830 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) i9xx_set_pipeconf() argument
7832 struct drm_device *dev = intel_crtc->base.dev; i9xx_set_pipeconf()
7838 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || i9xx_set_pipeconf()
7839 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) i9xx_set_pipeconf()
7840 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; i9xx_set_pipeconf()
7842 if (intel_crtc->config->double_wide) i9xx_set_pipeconf()
7848 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) i9xx_set_pipeconf()
7852 switch (intel_crtc->config->pipe_bpp) { i9xx_set_pipeconf()
7869 if (intel_crtc->lowfreq_avail) { i9xx_set_pipeconf()
7877 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { i9xx_set_pipeconf()
7879 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) i9xx_set_pipeconf()
7886 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range) i9xx_set_pipeconf()
7889 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); i9xx_set_pipeconf()
7890 POSTING_READ(PIPECONF(intel_crtc->pipe)); i9xx_set_pipeconf()
7893 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, i9xx_crtc_compute_clock()
7973 static void i9xx_get_pfit_config(struct intel_crtc *crtc, i9xx_get_pfit_config()
8003 static void vlv_crtc_clock_get(struct intel_crtc *crtc, vlv_crtc_clock_get()
8031 i9xx_get_initial_plane_config(struct intel_crtc *crtc, i9xx_get_initial_plane_config()
8099 static void chv_crtc_clock_get(struct intel_crtc *crtc, chv_crtc_clock_get()
8129 static bool i9xx_get_pipe_config(struct intel_crtc *crtc, i9xx_get_pipe_config()
8614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); ironlake_set_pipeconf() local
8615 int pipe = intel_crtc->pipe; ironlake_set_pipeconf()
8620 switch (intel_crtc->config->pipe_bpp) { ironlake_set_pipeconf()
8638 if (intel_crtc->config->dither) ironlake_set_pipeconf()
8641 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) ironlake_set_pipeconf()
8646 if (intel_crtc->config->limited_color_range) ironlake_set_pipeconf()
8664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_set_pipe_csc() local
8665 int pipe = intel_crtc->pipe; intel_set_pipe_csc()
8675 if (intel_crtc->config->limited_color_range) intel_set_pipe_csc()
8699 if (intel_crtc->config->limited_color_range) intel_set_pipe_csc()
8710 if (intel_crtc->config->limited_color_range) intel_set_pipe_csc()
8721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); haswell_set_pipeconf() local
8722 enum pipe pipe = intel_crtc->pipe; haswell_set_pipeconf()
8723 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; haswell_set_pipeconf()
8728 if (IS_HASWELL(dev) && intel_crtc->config->dither) haswell_set_pipeconf()
8731 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) haswell_set_pipeconf()
8739 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); haswell_set_pipeconf()
8740 POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); haswell_set_pipeconf()
8745 switch (intel_crtc->config->pipe_bpp) { haswell_set_pipeconf()
8763 if (intel_crtc->config->dither) haswell_set_pipeconf()
8815 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, ironlake_compute_dpll() argument
8820 struct drm_crtc *crtc = &intel_crtc->base; ironlake_compute_dpll()
8911 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, ironlake_crtc_compute_clock()
8977 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, intel_pch_transcoder_get_m_n()
8993 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, intel_cpu_transcoder_get_m_n()
9035 void intel_dp_get_m_n(struct intel_crtc *crtc, intel_dp_get_m_n()
9046 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, ironlake_get_fdi_m_n_config()
9053 static void skylake_get_pfit_config(struct intel_crtc *crtc, skylake_get_pfit_config()
9084 skylake_get_initial_plane_config(struct intel_crtc *crtc, skylake_get_initial_plane_config()
9167 static void ironlake_get_pfit_config(struct intel_crtc *crtc, ironlake_get_pfit_config()
9192 ironlake_get_initial_plane_config(struct intel_crtc *crtc, ironlake_get_initial_plane_config()
9260 static bool ironlake_get_pipe_config(struct intel_crtc *crtc, ironlake_get_pipe_config()
9345 struct intel_crtc *crtc; assert_can_disable_lcpll()
9576 struct intel_crtc *intel_crtc; ilk_max_pixel_rate() local
9580 for_each_intel_crtc(state->dev, intel_crtc) { ilk_max_pixel_rate()
9583 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); ilk_max_pixel_rate()
9721 static int haswell_crtc_compute_clock(struct intel_crtc *crtc, haswell_crtc_compute_clock()
9803 static void haswell_get_ddi_port_state(struct intel_crtc *crtc, haswell_get_ddi_port_state()
9847 static bool haswell_get_pipe_config(struct intel_crtc *crtc, haswell_get_pipe_config()
9932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); i845_update_cursor() local
9936 unsigned int width = intel_crtc->base.cursor->state->crtc_w; i845_update_cursor()
9937 unsigned int height = intel_crtc->base.cursor->state->crtc_h; i845_update_cursor()
9961 if (intel_crtc->cursor_cntl != 0 && i845_update_cursor()
9962 (intel_crtc->cursor_base != base || i845_update_cursor()
9963 intel_crtc->cursor_size != size || i845_update_cursor()
9964 intel_crtc->cursor_cntl != cntl)) { i845_update_cursor()
9970 intel_crtc->cursor_cntl = 0; i845_update_cursor()
9973 if (intel_crtc->cursor_base != base) { i845_update_cursor()
9975 intel_crtc->cursor_base = base; i845_update_cursor()
9978 if (intel_crtc->cursor_size != size) { i845_update_cursor()
9980 intel_crtc->cursor_size = size; i845_update_cursor()
9983 if (intel_crtc->cursor_cntl != cntl) { i845_update_cursor()
9986 intel_crtc->cursor_cntl = cntl; i845_update_cursor()
9994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); i9xx_update_cursor() local
9995 int pipe = intel_crtc->pipe; i9xx_update_cursor()
10000 switch (intel_crtc->base.cursor->state->crtc_w) { i9xx_update_cursor()
10011 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); i9xx_update_cursor()
10023 if (intel_crtc->cursor_cntl != cntl) { i9xx_update_cursor()
10026 intel_crtc->cursor_cntl = cntl; i9xx_update_cursor()
10033 intel_crtc->cursor_base = base; i9xx_update_cursor()
10042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_crtc_update_cursor() local
10043 int pipe = intel_crtc->pipe; intel_crtc_update_cursor()
10049 base = intel_crtc->cursor_addr; intel_crtc_update_cursor()
10051 if (x >= intel_crtc->config->pipe_src_w) intel_crtc_update_cursor()
10054 if (y >= intel_crtc->config->pipe_src_h) intel_crtc_update_cursor()
10131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_crtc_gamma_set() local
10134 intel_crtc->lut_r[i] = red[i] >> 8; intel_crtc_gamma_set()
10135 intel_crtc->lut_g[i] = green[i] >> 8; intel_crtc_gamma_set()
10136 intel_crtc->lut_b[i] = blue[i] >> 8; intel_crtc_gamma_set()
10299 struct intel_crtc *intel_crtc; intel_get_load_detect_pipe() local
10380 intel_crtc = to_intel_crtc(crtc);
10400 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10445 intel_wait_for_vblank(dev, intel_crtc->pipe);
10469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_release_load_detect_pipe() local
10490 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); intel_release_load_detect_pipe()
10543 static void i9xx_crtc_clock_get(struct intel_crtc *crtc, i9xx_crtc_clock_get()
10651 static void ironlake_pch_clock_get(struct intel_crtc *crtc, ironlake_pch_clock_get()
10675 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_crtc_mode_get() local
10676 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; intel_crtc_mode_get()
10683 enum pipe pipe = intel_crtc->pipe; intel_crtc_mode_get()
10701 i9xx_crtc_clock_get(intel_crtc, &pipe_config); intel_crtc_mode_get()
10749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_crtc_destroy() local
10754 work = intel_crtc->unpin_work; intel_crtc_destroy()
10755 intel_crtc->unpin_work = NULL; intel_crtc_destroy()
10765 kfree(intel_crtc); intel_crtc_destroy()
10772 struct intel_crtc *crtc = to_intel_crtc(work->crtc); intel_unpin_work_fn()
10796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); do_intel_finish_page_flip() local
10801 if (intel_crtc == NULL) do_intel_finish_page_flip()
10809 work = intel_crtc->unpin_work; do_intel_finish_page_flip()
10819 page_flip_completed(intel_crtc); do_intel_finish_page_flip()
10846 static bool page_flip_finished(struct intel_crtc *crtc) page_flip_finished()
10889 struct intel_crtc *intel_crtc = intel_prepare_page_flip() local
10903 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) intel_prepare_page_flip()
10904 atomic_inc_not_zero(&intel_crtc->unpin_work->pending); intel_prepare_page_flip()
10925 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_gen2_queue_flip() local
10936 if (intel_crtc->plane) intel_gen2_queue_flip()
10943 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); intel_gen2_queue_flip()
10945 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); intel_gen2_queue_flip()
10948 intel_mark_page_flip_active(intel_crtc->unpin_work); intel_gen2_queue_flip()
10960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_gen3_queue_flip() local
10968 if (intel_crtc->plane) intel_gen3_queue_flip()
10975 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); intel_gen3_queue_flip()
10977 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); intel_gen3_queue_flip()
10980 intel_mark_page_flip_active(intel_crtc->unpin_work); intel_gen3_queue_flip()
10993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_gen4_queue_flip() local
11006 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); intel_gen4_queue_flip()
11008 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | intel_gen4_queue_flip()
11016 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; intel_gen4_queue_flip()
11019 intel_mark_page_flip_active(intel_crtc->unpin_work); intel_gen4_queue_flip()
11032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_gen6_queue_flip() local
11041 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); intel_gen6_queue_flip()
11043 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); intel_gen6_queue_flip()
11049 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; intel_gen6_queue_flip()
11052 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; intel_gen6_queue_flip()
11055 intel_mark_page_flip_active(intel_crtc->unpin_work); intel_gen6_queue_flip()
11067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_gen7_queue_flip() local
11071 switch (intel_crtc->plane) { intel_gen7_queue_flip()
11147 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); intel_gen7_queue_flip()
11150 intel_mark_page_flip_active(intel_crtc->unpin_work); intel_gen7_queue_flip()
11181 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, skl_do_mmio_flip() argument
11184 struct drm_device *dev = intel_crtc->base.dev; skl_do_mmio_flip()
11186 struct drm_framebuffer *fb = intel_crtc->base.primary->fb; skl_do_mmio_flip()
11187 const enum pipe pipe = intel_crtc->pipe; skl_do_mmio_flip()
11227 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, ilk_do_mmio_flip() argument
11230 struct drm_device *dev = intel_crtc->base.dev; ilk_do_mmio_flip()
11233 to_intel_framebuffer(intel_crtc->base.primary->fb); ilk_do_mmio_flip()
11238 reg = DSPCNTR(intel_crtc->plane); ilk_do_mmio_flip()
11248 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); ilk_do_mmio_flip()
11249 POSTING_READ(DSPSURF(intel_crtc->plane)); ilk_do_mmio_flip()
11258 struct intel_crtc *crtc = mmio_flip->crtc; intel_do_mmio_flip()
11334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); __intel_pageflip_stall_check() local
11335 struct intel_unpin_work *work = intel_crtc->unpin_work; __intel_pageflip_stall_check()
11361 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); __intel_pageflip_stall_check()
11363 addr = I915_READ(DSPADDR(intel_crtc->plane)); __intel_pageflip_stall_check()
11376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_check_page_flip() local
11385 work = intel_crtc->unpin_work; intel_check_page_flip()
11389 page_flip_completed(intel_crtc); intel_check_page_flip()
11407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_crtc_page_flip() local
11409 enum pipe pipe = intel_crtc->pipe; intel_crtc_page_flip()
11455 if (intel_crtc->unpin_work) { intel_crtc_page_flip()
11461 page_flip_completed(intel_crtc); intel_crtc_page_flip()
11471 intel_crtc->unpin_work = work; intel_crtc_page_flip()
11474 if (atomic_read(&intel_crtc->unpin_work_count) >= 2) intel_crtc_page_flip()
11490 atomic_inc(&intel_crtc->unpin_work_count); intel_crtc_page_flip()
11491 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); intel_crtc_page_flip()
11526 work->gtt_offset += intel_crtc->dspaddr_offset; intel_crtc_page_flip()
11561 intel_fbc_disable_crtc(intel_crtc); intel_crtc_page_flip()
11565 trace_i915_flip_request(intel_crtc->plane, obj); intel_crtc_page_flip()
11574 atomic_dec(&intel_crtc->unpin_work_count); intel_crtc_page_flip()
11584 intel_crtc->unpin_work = NULL; intel_crtc_page_flip()
11660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_plane_atomic_calc_changes() local
11666 int idx = intel_crtc->base.base.id, ret; intel_plane_atomic_calc_changes()
11690 intel_crtc->atomic.disabled_planes |= 1 << i; intel_plane_atomic_calc_changes()
11715 intel_crtc->atomic.update_wm_pre = true; intel_plane_atomic_calc_changes()
11718 intel_crtc->atomic.disable_cxsr = true; intel_plane_atomic_calc_changes()
11720 intel_crtc->atomic.wait_vblank = true; intel_plane_atomic_calc_changes()
11721 intel_crtc->atomic.update_wm_post = true; intel_plane_atomic_calc_changes()
11724 intel_crtc->atomic.update_wm_post = true; intel_plane_atomic_calc_changes()
11728 intel_crtc->atomic.wait_vblank = true; intel_plane_atomic_calc_changes()
11729 intel_crtc->atomic.disable_cxsr = true; intel_plane_atomic_calc_changes()
11732 intel_crtc->atomic.update_wm_pre = true; intel_plane_atomic_calc_changes()
11736 intel_crtc->atomic.fb_bits |= intel_plane_atomic_calc_changes()
11741 intel_crtc->atomic.wait_for_flips = true; intel_plane_atomic_calc_changes()
11742 intel_crtc->atomic.pre_disable_primary = turn_off; intel_plane_atomic_calc_changes()
11743 intel_crtc->atomic.post_enable_primary = turn_on; intel_plane_atomic_calc_changes()
11754 intel_crtc->atomic.disable_ips = true; intel_plane_atomic_calc_changes()
11756 intel_crtc->atomic.disable_fbc = true; intel_plane_atomic_calc_changes()
11772 dev_priv->fbc.crtc == intel_crtc && intel_plane_atomic_calc_changes()
11774 intel_crtc->atomic.disable_fbc = true; intel_plane_atomic_calc_changes()
11782 intel_crtc->atomic.wait_vblank = true; intel_plane_atomic_calc_changes()
11784 intel_crtc->atomic.update_fbc |= visible || mode_changed; intel_plane_atomic_calc_changes()
11790 intel_crtc->atomic.wait_vblank = true; intel_plane_atomic_calc_changes()
11791 intel_crtc->atomic.update_sprite_watermarks |= intel_plane_atomic_calc_changes()
11807 struct intel_crtc *crtc, check_single_encoder_cloning()
11829 struct intel_crtc *crtc) check_encoder_cloning()
11853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_crtc_atomic_check() local
11860 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { intel_crtc_atomic_check()
11866 intel_crtc->atomic.update_wm_post = true; intel_crtc_atomic_check()
11871 ret = dev_priv->display.crtc_compute_clock(intel_crtc, intel_crtc_atomic_check()
11883 ret = intel_atomic_setup_scalers(dev, intel_crtc, intel_crtc_atomic_check()
11952 compute_baseline_pipe_bpp(struct intel_crtc *crtc, compute_baseline_pipe_bpp()
11996 static void intel_dump_pipe_config(struct intel_crtc *crtc, intel_dump_pipe_config()
12356 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12357 list_for_each_entry((intel_crtc), \
12360 if (mask & (1 <<(intel_crtc)->pipe))
12640 struct intel_crtc *intel_crtc; check_wm_state() local
12649 for_each_intel_crtc(dev, intel_crtc) { for_each_intel_crtc()
12651 const enum pipe pipe = intel_crtc->pipe; for_each_intel_crtc()
12653 if (!intel_crtc->active) for_each_intel_crtc()
12757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); for_each_crtc_in_state() local
12774 active = dev_priv->display.get_pipe_config(intel_crtc, for_each_crtc_in_state()
12778 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || for_each_crtc_in_state()
12779 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) for_each_crtc_in_state()
12786 I915_STATE_WARN(intel_crtc->active != crtc->state->active, for_each_crtc_in_state()
12788 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active); for_each_crtc_in_state()
12798 I915_STATE_WARN(active && intel_crtc->pipe != pipe, for_each_encoder_on_crtc()
12813 intel_dump_pipe_config(intel_crtc, pipe_config,
12815 intel_dump_pipe_config(intel_crtc, sw_config,
12825 struct intel_crtc *crtc; check_shared_dpll_state()
12893 static void update_scanline_offset(struct intel_crtc *crtc) update_scanline_offset()
12936 struct intel_crtc *intel_crtc; intel_modeset_clear_plls() local
12948 intel_crtc = to_intel_crtc(crtc); for_each_crtc_in_state()
12960 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe); for_each_crtc_in_state()
12973 struct intel_crtc *intel_crtc; haswell_mode_set_planes_workaround() local
12982 intel_crtc = to_intel_crtc(crtc); for_each_crtc_in_state()
12992 first_pipe = intel_crtc->pipe; for_each_crtc_in_state()
13001 for_each_intel_crtc(state->dev, intel_crtc) {
13004 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13018 enabled_pipe = intel_crtc->pipe;
13218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); for_each_crtc_in_state() local
13224 intel_pre_plane_update(intel_crtc); for_each_crtc_in_state()
13229 intel_crtc->active = false; for_each_crtc_in_state()
13230 intel_disable_shared_dpll(intel_crtc); for_each_crtc_in_state()
13247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); for_each_crtc_in_state() local
13266 intel_pre_plane_update(intel_crtc); for_each_crtc_in_state()
13273 intel_post_plane_update(intel_crtc); for_each_crtc_in_state()
13388 struct intel_crtc *crtc; ibx_pch_dpll_disable()
13510 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) skl_max_scale() argument
13517 if (!intel_crtc || !crtc_state) skl_max_scale()
13520 dev = intel_crtc->base.dev; skl_max_scale()
13574 struct intel_crtc *intel_crtc; intel_commit_primary_plane() local
13578 intel_crtc = to_intel_crtc(crtc); intel_commit_primary_plane()
13606 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_begin_crtc_commit() local
13611 if (intel_crtc->atomic.update_wm_pre) intel_begin_crtc_commit()
13616 intel_pipe_update_start(intel_crtc); intel_begin_crtc_commit()
13622 intel_update_pipe_config(intel_crtc, old_intel_state); intel_begin_crtc_commit()
13624 skl_detach_scalers(intel_crtc); intel_begin_crtc_commit()
13630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_finish_crtc_commit() local
13633 intel_pipe_update_end(intel_crtc); intel_finish_crtc_commit()
13812 struct intel_crtc *intel_crtc; intel_commit_cursor_plane() local
13817 intel_crtc = to_intel_crtc(crtc); intel_commit_cursor_plane()
13826 intel_crtc->cursor_addr = addr; intel_commit_cursor_plane()
13884 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, skl_init_scalers() argument
13891 for (i = 0; i < intel_crtc->num_scalers; i++) { skl_init_scalers()
13903 struct intel_crtc *intel_crtc; intel_crtc_init() local
13909 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); intel_crtc_init()
13910 if (intel_crtc == NULL) intel_crtc_init()
13916 intel_crtc->config = crtc_state; intel_crtc_init()
13917 intel_crtc->base.state = &crtc_state->base; intel_crtc_init()
13918 crtc_state->base.crtc = &intel_crtc->base; intel_crtc_init()
13923 intel_crtc->num_scalers = 1; intel_crtc_init()
13925 intel_crtc->num_scalers = SKL_NUM_SCALERS; intel_crtc_init()
13927 skl_init_scalers(dev, intel_crtc, crtc_state); intel_crtc_init()
13938 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, intel_crtc_init()
13943 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); intel_crtc_init()
13945 intel_crtc->lut_r[i] = i; intel_crtc_init()
13946 intel_crtc->lut_g[i] = i; intel_crtc_init()
13947 intel_crtc->lut_b[i] = i; intel_crtc_init()
13954 intel_crtc->pipe = pipe; intel_crtc_init()
13955 intel_crtc->plane = pipe; intel_crtc_init()
13958 intel_crtc->plane = !pipe; intel_crtc_init()
13961 intel_crtc->cursor_base = ~0; intel_crtc_init()
13962 intel_crtc->cursor_cntl = ~0; intel_crtc_init()
13963 intel_crtc->cursor_size = ~0; intel_crtc_init()
13965 intel_crtc->wm.cxsr_allowed = true; intel_crtc_init()
13968 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); intel_crtc_init()
13969 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; intel_crtc_init()
13970 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; intel_crtc_init()
13972 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); intel_crtc_init()
13974 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); intel_crtc_init()
13983 kfree(intel_crtc); intel_crtc_init()
14004 struct intel_crtc *crtc; intel_get_pipe_from_crtc_id()
14879 struct intel_crtc *crtc; intel_modeset_init()
15024 intel_check_plane_mapping(struct intel_crtc *crtc) intel_check_plane_mapping()
15042 static bool intel_crtc_has_encoders(struct intel_crtc *crtc) intel_crtc_has_encoders()
15053 static void intel_sanitize_crtc(struct intel_crtc *crtc) intel_sanitize_crtc()
15247 static void readout_plane_state(struct intel_crtc *crtc) readout_plane_state()
15264 struct intel_crtc *crtc; intel_modeset_readout_hw_state()
15382 struct intel_crtc *crtc; intel_modeset_setup_hw_state()
15814 struct intel_crtc *crtc; intel_modeset_preclose()
H A Dintel_fbdev.c294 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_crtc_fb_gamma_set() local
296 intel_crtc->lut_r[regno] = red >> 8; intel_crtc_fb_gamma_set()
297 intel_crtc->lut_g[regno] = green >> 8; intel_crtc_fb_gamma_set()
298 intel_crtc->lut_b[regno] = blue >> 8; intel_crtc_fb_gamma_set()
304 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_crtc_fb_gamma_get() local
306 *red = intel_crtc->lut_r[regno] << 8; intel_crtc_fb_gamma_get()
307 *green = intel_crtc->lut_g[regno] << 8; intel_crtc_fb_gamma_get()
308 *blue = intel_crtc->lut_b[regno] << 8; intel_crtc_fb_gamma_get()
547 struct intel_crtc *intel_crtc; intel_fbdev_init_bios() local
554 intel_crtc = to_intel_crtc(crtc); for_each_crtc()
558 pipe_name(intel_crtc->pipe)); for_each_crtc()
564 pipe_name(intel_crtc->pipe)); for_each_crtc()
579 intel_crtc = to_intel_crtc(crtc); for_each_crtc()
583 pipe_name(intel_crtc->pipe)); for_each_crtc()
588 pipe_name(intel_crtc->pipe)); for_each_crtc()
595 cur_size = intel_crtc->config->base.adjusted_mode.crtc_hdisplay; for_each_crtc()
599 pipe_name(intel_crtc->pipe), for_each_crtc()
605 cur_size = intel_crtc->config->base.adjusted_mode.crtc_vdisplay; for_each_crtc()
611 pipe_name(intel_crtc->pipe), for_each_crtc()
612 intel_crtc->config->base.adjusted_mode.crtc_hdisplay, for_each_crtc()
613 intel_crtc->config->base.adjusted_mode.crtc_vdisplay, for_each_crtc()
619 pipe_name(intel_crtc->pipe), for_each_crtc()
626 pipe_name(intel_crtc->pipe), for_each_crtc()
642 intel_crtc = to_intel_crtc(crtc); for_each_crtc()
H A Dintel_fifo_underrun.c54 struct intel_crtc *crtc; ivb_can_enable_err_int()
73 struct intel_crtc *crtc; cpt_can_enable_serr_int()
97 struct intel_crtc *crtc; i9xx_check_fifo_underruns()
235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); __intel_set_cpu_fifo_underrun_reporting() local
240 old = !intel_crtc->cpu_fifo_underrun_disabled; __intel_set_cpu_fifo_underrun_reporting()
241 intel_crtc->cpu_fifo_underrun_disabled = !enable; __intel_set_cpu_fifo_underrun_reporting()
304 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_set_pch_fifo_underrun_reporting() local
319 old = !intel_crtc->pch_fifo_underrun_disabled; intel_set_pch_fifo_underrun_reporting()
320 intel_crtc->pch_fifo_underrun_disabled = !enable; intel_set_pch_fifo_underrun_reporting()
H A Dintel_audio.c152 static bool audio_rate_need_prog(struct intel_crtc *crtc, audio_rate_need_prog()
251 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); hsw_audio_codec_disable() local
252 enum pipe pipe = intel_crtc->pipe; hsw_audio_codec_disable()
265 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) hsw_audio_codec_disable()
283 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); hsw_audio_codec_enable() local
284 enum pipe pipe = intel_crtc->pipe; hsw_audio_codec_enable()
331 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) hsw_audio_codec_enable()
337 if (audio_rate_need_prog(intel_crtc, adjusted_mode)) { hsw_audio_codec_enable()
361 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); ilk_audio_codec_disable() local
365 enum pipe pipe = intel_crtc->pipe; ilk_audio_codec_disable()
393 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) ilk_audio_codec_disable()
410 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); ilk_audio_codec_enable() local
414 enum pipe pipe = intel_crtc->pipe; ilk_audio_codec_enable()
481 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) ilk_audio_codec_enable()
498 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); intel_audio_codec_enable()
638 struct intel_crtc *crtc; i915_audio_component_sync_audio_rate()
H A Dintel_atomic.c133 struct intel_crtc *intel_crtc, intel_atomic_setup_scalers()
160 if (num_scalers_need > intel_crtc->num_scalers){ intel_atomic_setup_scalers()
162 num_scalers_need, intel_crtc->num_scalers); intel_atomic_setup_scalers()
178 idx = intel_crtc->base.base.id; intel_atomic_setup_scalers()
209 intel_crtc->atomic.wait_for_flips = true; intel_atomic_setup_scalers()
217 if (WARN_ON(intel_plane->pipe != intel_crtc->pipe)) { intel_atomic_setup_scalers()
227 for (j = 0; j < intel_crtc->num_scalers; j++) { intel_atomic_setup_scalers()
232 intel_crtc->pipe, *scaler_id, name, idx); intel_atomic_setup_scalers()
244 if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) { intel_atomic_setup_scalers()
132 intel_atomic_setup_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) intel_atomic_setup_scalers() argument
H A Dintel_ddi.c611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); hsw_fdi_link_train() local
628 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); hsw_fdi_link_train()
638 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel); hsw_fdi_link_train()
639 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL); hsw_fdi_link_train()
657 ((intel_crtc->config->fdi_lanes - 1) << 1) | hsw_fdi_link_train()
741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_ddi_get_crtc_encoder() local
752 pipe_name(intel_crtc->pipe));
761 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); intel_ddi_get_crtc_new_encoder()
1267 hsw_ddi_pll_select(struct intel_crtc *intel_crtc, hsw_ddi_pll_select() argument
1289 pll = intel_get_shared_dpll(intel_crtc, crtc_state); hsw_ddi_pll_select()
1292 pipe_name(intel_crtc->pipe)); hsw_ddi_pll_select()
1308 spll->crtc_mask |= 1 << intel_crtc->pipe; hsw_ddi_pll_select()
1561 skl_ddi_pll_select(struct intel_crtc *intel_crtc, skl_ddi_pll_select() argument
1618 pll = intel_get_shared_dpll(intel_crtc, crtc_state); skl_ddi_pll_select()
1621 pipe_name(intel_crtc->pipe)); skl_ddi_pll_select()
1654 bxt_ddi_pll_select(struct intel_crtc *intel_crtc, bxt_ddi_pll_select() argument
1675 clock, pipe_name(intel_crtc->pipe)); bxt_ddi_pll_select()
1765 pll = intel_get_shared_dpll(intel_crtc, crtc_state); bxt_ddi_pll_select()
1768 pipe_name(intel_crtc->pipe)); bxt_ddi_pll_select()
1780 * intel_crtc->ddi_pll_sel.
1785 bool intel_ddi_pll_select(struct intel_crtc *intel_crtc, intel_ddi_pll_select() argument
1788 struct drm_device *dev = intel_crtc->base.dev; intel_ddi_pll_select()
1793 return skl_ddi_pll_select(intel_crtc, crtc_state, intel_ddi_pll_select()
1796 return bxt_ddi_pll_select(intel_crtc, crtc_state, intel_ddi_pll_select()
1799 return hsw_ddi_pll_select(intel_crtc, crtc_state, intel_ddi_pll_select()
1806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_ddi_set_pipe_settings() local
1808 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; intel_ddi_set_pipe_settings()
1814 switch (intel_crtc->config->pipe_bpp) { intel_ddi_set_pipe_settings()
1836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_ddi_set_vc_payload_alloc() local
1839 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; intel_ddi_set_vc_payload_alloc()
1851 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_ddi_enable_transcoder_func() local
1856 enum pipe pipe = intel_crtc->pipe; intel_ddi_enable_transcoder_func()
1857 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; intel_ddi_enable_transcoder_func()
1866 switch (intel_crtc->config->pipe_bpp) { intel_ddi_enable_transcoder_func()
1883 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) intel_ddi_enable_transcoder_func()
1885 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) intel_ddi_enable_transcoder_func()
1896 (intel_crtc->config->pch_pfit.enabled || intel_ddi_enable_transcoder_func()
1897 intel_crtc->config->pch_pfit.force_thru)) intel_ddi_enable_transcoder_func()
1915 if (intel_crtc->config->has_hdmi_sink) intel_ddi_enable_transcoder_func()
1922 temp |= (intel_crtc->config->fdi_lanes - 1) << 1; intel_ddi_enable_transcoder_func()
1933 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); intel_ddi_enable_transcoder_func()
1942 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count); intel_ddi_enable_transcoder_func()
2066 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) intel_ddi_enable_pipe_clock() argument
2068 struct drm_crtc *crtc = &intel_crtc->base; intel_ddi_enable_pipe_clock()
2073 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; intel_ddi_enable_pipe_clock()
2080 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) intel_ddi_disable_pipe_clock() argument
2082 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; intel_ddi_disable_pipe_clock()
2083 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; intel_ddi_disable_pipe_clock()
2288 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); intel_ddi_pre_enable()
2404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_enable_ddi() local
2432 if (intel_crtc->config->has_audio) { intel_enable_ddi()
2442 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_disable_ddi() local
2447 if (intel_crtc->config->has_audio) { intel_disable_ddi()
3114 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); intel_ddi_get_config() local
3164 intel_dp_get_m_n(intel_crtc, pipe_config); intel_ddi_get_config()
3172 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe)) intel_ddi_get_config()
H A Dintel_fbc.c57 static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc) get_crtc_fence_y_offset()
85 static void i8xx_fbc_enable(struct intel_crtc *crtc) i8xx_fbc_enable()
140 static void g4x_fbc_enable(struct intel_crtc *crtc) g4x_fbc_enable()
191 static void ilk_fbc_enable(struct intel_crtc *crtc) ilk_fbc_enable()
260 static void gen7_fbc_enable(struct intel_crtc *crtc) gen7_fbc_enable()
331 static void intel_fbc_enable(struct intel_crtc *crtc, intel_fbc_enable()
391 static void intel_fbc_schedule_enable(struct intel_crtc *crtc) intel_fbc_schedule_enable()
461 void intel_fbc_disable_crtc(struct intel_crtc *crtc) intel_fbc_disable_crtc()
706 static void intel_fbc_get_plane_source_size(struct intel_crtc *crtc, intel_fbc_get_plane_source_size()
727 static int intel_fbc_calculate_cfb_size(struct intel_crtc *crtc) intel_fbc_calculate_cfb_size()
740 static int intel_fbc_setup_cfb(struct intel_crtc *crtc) intel_fbc_setup_cfb()
808 static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc) intel_fbc_hw_tracking_covers_screen()
853 struct intel_crtc *intel_crtc; __intel_fbc_update() local
894 intel_crtc = to_intel_crtc(crtc); __intel_fbc_update()
897 adjusted_mode = &intel_crtc->config->base.adjusted_mode; __intel_fbc_update()
905 if (!intel_fbc_hw_tracking_covers_screen(intel_crtc)) { __intel_fbc_update()
911 intel_crtc->plane != PLANE_A) { __intel_fbc_update()
948 ilk_pipe_pixel_rate(intel_crtc->config) >= __intel_fbc_update()
954 if (intel_fbc_setup_cfb(intel_crtc)) { __intel_fbc_update()
964 if (dev_priv->fbc.crtc == intel_crtc && __intel_fbc_update()
997 intel_fbc_schedule_enable(intel_crtc); __intel_fbc_update()
H A Dintel_pm.c819 static void vlv_write_wm_values(struct intel_crtc *crtc, vlv_write_wm_values()
929 struct intel_crtc *crtc, vlv_compute_wm_level()
965 static void vlv_compute_fifo(struct intel_crtc *crtc) vlv_compute_fifo()
1032 static void vlv_invert_wms(struct intel_crtc *crtc) vlv_invert_wms()
1066 static void vlv_compute_wm(struct intel_crtc *crtc) vlv_compute_wm()
1168 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc) vlv_pipe_set_fifo_size()
1258 struct intel_crtc *crtc; vlv_merge_wm()
1305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); vlv_update_wm() local
1306 enum pipe pipe = intel_crtc->pipe; vlv_update_wm()
1309 vlv_compute_wm(intel_crtc); vlv_update_wm()
1314 vlv_pipe_set_fifo_size(intel_crtc); vlv_update_wm()
1330 vlv_pipe_set_fifo_size(intel_crtc); vlv_update_wm()
1332 vlv_write_wm_values(intel_crtc, &wm); vlv_update_wm()
1979 const struct intel_crtc *intel_crtc, ilk_compute_wm_level()
1996 for_each_intel_plane_on_crtc(dev_priv->dev, intel_crtc, intel_plane) { ilk_compute_wm_level()
2026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); hsw_compute_linetime_wm() local
2027 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; hsw_compute_linetime_wm()
2030 if (!intel_crtc->active) hsw_compute_linetime_wm()
2280 struct intel_crtc *intel_crtc; ilk_compute_wm_config() local
2283 for_each_intel_crtc(dev, intel_crtc) { for_each_intel_crtc()
2284 const struct intel_pipe_wm *wm = &intel_crtc->wm.active; for_each_intel_crtc()
2302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_compute_pipe_wm() local
2312 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { for_each_intel_plane_on_crtc()
2336 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, &pipe_wm->wm[0]);
2353 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, &wm);
2376 const struct intel_crtc *intel_crtc; ilk_merge_wm_level() local
2380 for_each_intel_crtc(dev, intel_crtc) { for_each_intel_crtc()
2381 const struct intel_pipe_wm *active = &intel_crtc->wm.active; for_each_intel_crtc()
2483 struct intel_crtc *intel_crtc; ilk_compute_wm_results() local
2528 for_each_intel_crtc(dev, intel_crtc) { for_each_intel_crtc()
2529 enum pipe pipe = intel_crtc->pipe; for_each_intel_crtc()
2531 &intel_crtc->wm.active.wm[0]; for_each_intel_crtc()
2536 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime; for_each_intel_crtc()
2861 skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc, skl_get_total_relative_data_rate() argument
2867 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { skl_get_total_relative_data_rate()
2891 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); skl_allocate_pipe_ddb() local
2892 enum pipe pipe = intel_crtc->pipe; skl_allocate_pipe_ddb()
2936 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
2939 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
3039 const struct intel_crtc *intel_crtc) skl_ddb_allocation_changed()
3041 struct drm_device *dev = intel_crtc->base.dev; skl_ddb_allocation_changed()
3044 enum pipe pipe = intel_crtc->pipe; skl_ddb_allocation_changed()
3079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); skl_compute_wm_pipe_parameters() local
3080 enum pipe pipe = intel_crtc->pipe; skl_compute_wm_pipe_parameters()
3085 p->active = intel_crtc->active; skl_compute_wm_pipe_parameters()
3087 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal; skl_compute_wm_pipe_parameters()
3088 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config); skl_compute_wm_pipe_parameters()
3106 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w; skl_compute_wm_pipe_parameters()
3107 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h; skl_compute_wm_pipe_parameters()
3259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); skl_compute_transition_wm() local
3266 for (i = 0; i < intel_num_planes(intel_crtc); i++) skl_compute_transition_wm()
3278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); skl_compute_pipe_wm() local
3282 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe, skl_compute_pipe_wm()
3283 level, intel_num_planes(intel_crtc), skl_compute_pipe_wm()
3295 struct intel_crtc *intel_crtc) skl_compute_wm_results()
3298 enum pipe pipe = intel_crtc->pipe; skl_compute_wm_results()
3303 for (i = 0; i < intel_num_planes(intel_crtc); i++) { skl_compute_wm_results()
3328 for (i = 0; i < intel_num_planes(intel_crtc); i++) { skl_compute_wm_results()
3362 struct intel_crtc *crtc; skl_write_wm_values()
3459 struct intel_crtc *crtc; skl_flush_wm_values()
3541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); skl_update_pipe_wm() local
3547 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm))) skl_update_pipe_wm()
3550 intel_crtc->wm.skl_active = *pipe_wm; skl_update_pipe_wm()
3560 struct intel_crtc *intel_crtc; skl_update_other_pipe_wm() local
3561 struct intel_crtc *this_crtc = to_intel_crtc(crtc); skl_update_other_pipe_wm()
3576 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, skl_update_other_pipe_wm()
3582 if (this_crtc->pipe == intel_crtc->pipe) skl_update_other_pipe_wm()
3585 if (!intel_crtc->active) skl_update_other_pipe_wm()
3588 wm_changed = skl_update_pipe_wm(&intel_crtc->base, skl_update_other_pipe_wm()
3599 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc); skl_update_other_pipe_wm()
3600 r->dirty[intel_crtc->pipe] = true; skl_update_other_pipe_wm()
3626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); skl_update_wm() local
3638 skl_clear_wm(results, intel_crtc->pipe); skl_update_wm()
3646 skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc); skl_update_wm()
3647 results->dirty[intel_crtc->pipe] = true; skl_update_wm()
3692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); ilk_update_wm() local
3703 WARN_ON(cstate->base.active != intel_crtc->active); ilk_update_wm()
3707 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm))) ilk_update_wm()
3710 intel_crtc->wm.active = pipe_wm; ilk_update_wm()
3807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); skl_pipe_wm_get_hw_state() local
3808 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active; skl_pipe_wm_get_hw_state()
3809 enum pipe pipe = intel_crtc->pipe; skl_pipe_wm_get_hw_state()
3818 for (i = 0; i < intel_num_planes(intel_crtc); i++) skl_pipe_wm_get_hw_state()
3824 for (i = 0; i < intel_num_planes(intel_crtc); i++) skl_pipe_wm_get_hw_state()
3828 if (!intel_crtc->active) skl_pipe_wm_get_hw_state()
3836 for (i = 0; i < intel_num_planes(intel_crtc); i++) { skl_pipe_wm_get_hw_state()
3845 for (i = 0; i < intel_num_planes(intel_crtc); i++) { skl_pipe_wm_get_hw_state()
3870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); ilk_pipe_wm_get_hw_state() local
3871 struct intel_pipe_wm *active = &intel_crtc->wm.active; ilk_pipe_wm_get_hw_state()
3872 enum pipe pipe = intel_crtc->pipe; ilk_pipe_wm_get_hw_state()
3885 active->pipe_enabled = intel_crtc->active; ilk_pipe_wm_get_hw_state()
1978 ilk_compute_wm_level(const struct drm_i915_private *dev_priv, const struct intel_crtc *intel_crtc, int level, struct intel_crtc_state *cstate, struct intel_wm_level *result) ilk_compute_wm_level() argument
3038 skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb, const struct intel_crtc *intel_crtc) skl_ddb_allocation_changed() argument
3291 skl_compute_wm_results(struct drm_device *dev, struct skl_pipe_wm_parameters *p, struct skl_pipe_wm *p_wm, struct skl_wm_values *r, struct intel_crtc *intel_crtc) skl_compute_wm_results() argument
H A Dintel_drv.h495 struct intel_crtc *crtc;
528 struct intel_crtc { struct
670 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
930 static inline unsigned int intel_num_planes(struct intel_crtc *crtc) intel_num_planes()
967 int intel_get_crtc_scanline(struct intel_crtc *crtc);
985 void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
986 void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
987 bool intel_ddi_pll_select(struct intel_crtc *crtc,
1052 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type);
1111 struct intel_shared_dpll *intel_crtc_to_shared_dpll(struct intel_crtc *crtc);
1117 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
1155 void intel_dp_get_m_n(struct intel_crtc *crtc,
1157 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1167 void hsw_enable_ips(struct intel_crtc *crtc);
1168 void hsw_disable_ips(struct intel_crtc *crtc);
1179 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1286 void intel_fbc_disable_crtc(struct intel_crtc *crtc);
1336 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1339 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1440 void intel_pipe_update_start(struct intel_crtc *crtc);
1441 void intel_pipe_update_end(struct intel_crtc *crtc);
1461 struct intel_crtc *crtc) intel_atomic_get_crtc_state()
1471 struct intel_crtc *intel_crtc,
H A Dintel_dp_mst.c153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_mst_pre_enable_dp() local
178 intel_dp_set_link_params(intel_dp, intel_crtc->config);
183 intel_crtc->config->ddi_pll_sel);
196 intel_crtc->config->pbn, &slots);
246 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); intel_dp_mst_enc_get_config()
371 struct intel_crtc *crtc = to_intel_crtc(state->crtc); intel_mst_atomic_best_encoder()
H A Dintel_dsi.c377 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); intel_dsi_port_enable() local
403 temp |= intel_crtc->pipe ? intel_dsi_port_enable()
466 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); intel_dsi_pre_enable() local
467 enum pipe pipe = intel_crtc->pipe; intel_dsi_pre_enable()
489 intel_crtc->config->dpll_hw_state.dpll = intel_dsi_pre_enable()
773 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); set_dsi_timings() local
776 unsigned int bpp = intel_crtc->config->pipe_bpp; set_dsi_timings()
843 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); intel_dsi_prepare() local
845 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; intel_dsi_prepare()
847 unsigned int bpp = intel_crtc->config->pipe_bpp; intel_dsi_prepare()
851 DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); intel_dsi_prepare()
H A Dintel_dp.c1387 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); intel_dp_compute_config() local
1427 intel_gmch_panel_fitting(intel_crtc, pipe_config, intel_dp_compute_config()
1430 intel_pch_panel_fitting(intel_crtc, pipe_config, intel_dp_compute_config()
1545 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); ironlake_set_pll_cpu_edp()
1586 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); intel_dp_prepare()
2279 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); intel_dp_get_config()
2363 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); intel_disable_dp()
2405 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); chv_data_lane_soft_reset()
2573 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); intel_enable_dp()
2712 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); vlv_init_panel_power_sequencer()
2753 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); vlv_pre_enable_dp() local
2755 int pipe = intel_crtc->pipe; vlv_pre_enable_dp()
2781 struct intel_crtc *intel_crtc = vlv_dp_pre_pll_enable() local
2784 int pipe = intel_crtc->pipe; vlv_dp_pre_pll_enable()
2812 struct intel_crtc *intel_crtc = chv_pre_enable_dp() local
2815 int pipe = intel_crtc->pipe; chv_pre_enable_dp()
2826 if (intel_crtc->config->lane_count > 2) { chv_pre_enable_dp()
2833 for (i = 0; i < intel_crtc->config->lane_count; i++) { chv_pre_enable_dp()
2835 if (intel_crtc->config->lane_count == 1) chv_pre_enable_dp()
2844 if (intel_crtc->config->port_clock > 270000) chv_pre_enable_dp()
2846 else if (intel_crtc->config->port_clock > 135000) chv_pre_enable_dp()
2848 else if (intel_crtc->config->port_clock > 67500) chv_pre_enable_dp()
2850 else if (intel_crtc->config->port_clock > 33750) chv_pre_enable_dp()
2859 if (intel_crtc->config->lane_count > 2) { chv_pre_enable_dp()
2872 if (intel_crtc->config->lane_count > 2) { chv_pre_enable_dp()
2900 struct intel_crtc *intel_crtc = chv_dp_pre_pll_enable() local
2903 enum pipe pipe = intel_crtc->pipe; chv_dp_pre_pll_enable()
2905 intel_dp_unused_lane_mask(intel_crtc->config->lane_count); chv_dp_pre_pll_enable()
2953 if (intel_crtc->config->lane_count > 2) { chv_dp_pre_pll_enable()
3152 struct intel_crtc *intel_crtc = vlv_signal_levels() local
3158 int pipe = intel_crtc->pipe; vlv_signal_levels()
3258 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); chv_signal_levels() local
3262 enum pipe pipe = intel_crtc->pipe; chv_signal_levels()
3344 if (intel_crtc->config->lane_count > 2) { chv_signal_levels()
3357 if (intel_crtc->config->lane_count > 2) { chv_signal_levels()
3365 for (i = 0; i < intel_crtc->config->lane_count; i++) { chv_signal_levels()
3373 for (i = 0; i < intel_crtc->config->lane_count; i++) { chv_signal_levels()
3396 for (i = 0; i < intel_crtc->config->lane_count; i++) { chv_signal_levels()
3410 if (intel_crtc->config->lane_count > 2) { chv_signal_levels()
3919 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); intel_dp_link_down()
4106 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); intel_dp_sink_crc_stop() local
4125 hsw_enable_ips(intel_crtc); intel_dp_sink_crc_stop()
4132 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); intel_dp_sink_crc_start() local
4153 hsw_disable_ips(intel_crtc); intel_dp_sink_crc_start()
4157 hsw_enable_ips(intel_crtc); intel_dp_sink_crc_start()
4169 struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc); intel_dp_sink_crc() local
4180 intel_wait_for_vblank(dev, intel_crtc->pipe); intel_dp_sink_crc()
5519 struct intel_crtc *intel_crtc = NULL; intel_dp_set_drrs_state() local
5539 intel_crtc = to_intel_crtc(encoder->base.crtc); intel_dp_set_drrs_state()
5541 if (!intel_crtc) { intel_dp_set_drrs_state()
5542 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); intel_dp_set_drrs_state()
5546 config = intel_crtc->config; intel_dp_set_drrs_state()
5563 if (!intel_crtc->active) { intel_dp_set_drrs_state()
5571 intel_dp_set_m_n(intel_crtc, M1_N1); intel_dp_set_drrs_state()
5574 intel_dp_set_m_n(intel_crtc, M2_N2); intel_dp_set_drrs_state()
5581 u32 reg = PIPECONF(intel_crtc->config->cpu_transcoder); intel_dp_set_drrs_state()
5616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_edp_drrs_enable() local
5618 if (!intel_crtc->config->has_drrs) { intel_edp_drrs_enable()
5648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_edp_drrs_disable() local
5650 if (!intel_crtc->config->has_drrs) intel_edp_drrs_disable()
H A Dintel_atomic_plane.c110 struct intel_crtc *intel_crtc; intel_plane_atomic_check() local
118 intel_crtc = to_intel_crtc(crtc); intel_plane_atomic_check()
H A Dintel_psr.c81 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); intel_psr_write_vsc()
296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_psr_match_conditions() local
315 I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) & intel_psr_match_conditions()
322 intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { intel_psr_match_conditions()
371 struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc); intel_psr_enable()
440 struct intel_crtc *intel_crtc = vlv_psr_disable() local
446 if (wait_for((I915_READ(VLV_PSRSTAT(intel_crtc->pipe)) & vlv_psr_disable()
450 val = I915_READ(VLV_PSRCTL(intel_crtc->pipe)); vlv_psr_disable()
454 I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val); vlv_psr_disable()
458 WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe)); vlv_psr_disable()
H A Di915_debugfs.c568 struct intel_crtc *crtc; i915_gem_pageflip_info()
2801 struct intel_crtc *intel_crtc, intel_encoder_info()
2806 struct drm_crtc *crtc = &intel_crtc->base; intel_encoder_info()
2829 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc) intel_crtc_info() argument
2833 struct drm_crtc *crtc = &intel_crtc->base; intel_crtc_info()
2845 intel_encoder_info(m, intel_crtc, intel_encoder); intel_crtc_info()
2954 struct intel_crtc *crtc; i915_display_info()
3173 struct drm_device *dev, struct intel_crtc *intel_crtc) drrs_status_per_crtc()
3180 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) { drrs_status_per_crtc()
3213 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) { drrs_status_per_crtc()
3259 struct intel_crtc *intel_crtc; i915_drrs_status() local
3262 for_each_intel_crtc(dev, intel_crtc) { for_each_intel_crtc()
3263 drm_modeset_lock(&intel_crtc->base.mutex, NULL); for_each_intel_crtc()
3265 if (intel_crtc->base.state->active) { for_each_intel_crtc()
3269 drrs_status_per_crtc(m, dev, intel_crtc); for_each_intel_crtc()
3272 drm_modeset_unlock(&intel_crtc->base.mutex); for_each_intel_crtc()
3538 struct intel_crtc *crtc; i9xx_pipe_crc_auto_source()
3805 struct intel_crtc *crtc = hsw_trans_edp_pipe_A_crc_wa()
3874 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe_crc_set_source()
3942 struct intel_crtc *crtc = pipe_crc_set_source()
2800 intel_encoder_info(struct seq_file *m, struct intel_crtc *intel_crtc, struct intel_encoder *intel_encoder) intel_encoder_info() argument
3172 drrs_status_per_crtc(struct seq_file *m, struct drm_device *dev, struct intel_crtc *intel_crtc) drrs_status_per_crtc() argument
H A Dintel_lvds.c137 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); intel_pre_enable_lvds()
308 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); intel_lvds_compute_config() local
312 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { intel_lvds_compute_config()
340 intel_pch_panel_fitting(intel_crtc, pipe_config, intel_lvds_compute_config()
343 intel_gmch_panel_fitting(intel_crtc, pipe_config, intel_lvds_compute_config()
H A Dintel_sprite.c81 void intel_pipe_update_start(struct intel_crtc *crtc) intel_pipe_update_start()
157 void intel_pipe_update_end(struct intel_crtc *crtc) intel_pipe_update_end()
760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_check_sprite_plane() local
780 if (intel_plane->pipe != intel_crtc->pipe) { intel_check_sprite_plane()
797 max_scale = skl_max_scale(intel_crtc, crtc_state); intel_check_sprite_plane()
H A Dintel_tv.c1025 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); intel_tv_pre_enable() local
1069 if (intel_crtc->pipe == 1) intel_tv_pre_enable()
1120 assert_pipe_disabled(dev_priv, intel_crtc->pipe); intel_tv_pre_enable()
1183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_tv_detect_type() local
1205 if (intel_crtc->pipe == 1) intel_tv_detect_type()
H A Di915_trace.h20 TP_PROTO(struct intel_crtc *crtc),
46 TP_PROTO(struct intel_crtc *crtc),
71 TP_PROTO(struct intel_crtc *crtc, u32 frame, int scanline_end),
H A Dintel_panel.c104 intel_pch_panel_fitting(struct intel_crtc *intel_crtc, intel_pch_panel_fitting() argument
303 void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, intel_gmch_panel_fitting() argument
307 struct drm_device *dev = intel_crtc->base.dev; intel_gmch_panel_fitting()
359 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | intel_gmch_panel_fitting()
H A Dintel_dvo.c186 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); intel_enable_dvo()
253 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); intel_dvo_pre_enable()
H A Dintel_sdvo.c1011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); intel_sdvo_set_avi_infoframe() local
1024 if (intel_crtc->config->limited_color_range) intel_sdvo_set_avi_infoframe()
1200 struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc); intel_sdvo_pre_enable()
1448 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); intel_disable_sdvo()
1490 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); intel_enable_sdvo() local
1501 intel_wait_for_vblank(dev, intel_crtc->pipe); intel_enable_sdvo()
H A Dintel_overlay.c172 struct intel_crtc *crtc;
883 struct intel_crtc *crtc) check_overlay_possible_on_crtc()
1093 struct intel_crtc *crtc; intel_overlay_put_image()
H A Di915_drv.h288 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
292 if ((intel_plane)->pipe == (intel_crtc)->pipe)
294 #define for_each_intel_crtc(dev, intel_crtc) \
295 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
609 struct intel_crtc;
643 bool (*get_pipe_config)(struct intel_crtc *,
645 void (*get_initial_plane_config)(struct intel_crtc *,
647 int (*crtc_compute_clock)(struct intel_crtc *crtc,
914 struct intel_crtc *crtc;
928 struct intel_crtc *crtc;
952 void (*enable_fbc)(struct intel_crtc *crtc);
H A Di915_irq.c671 struct intel_crtc *intel_crtc = i915_get_vblank_counter() local
673 const struct drm_display_mode *mode = &intel_crtc->base.hwmode; i915_get_vblank_counter()
723 static int __intel_get_crtc_scanline(struct intel_crtc *crtc) __intel_get_crtc_scanline()
780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); i915_get_crtc_scanoutpos() local
824 position = __intel_get_crtc_scanline(intel_crtc); i915_get_crtc_scanoutpos()
897 int intel_get_crtc_scanline(struct intel_crtc *crtc) intel_get_crtc_scanline()
H A Dintel_crt.c148 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); intel_crt_set_dpms()

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