Searched refs:h_sync_width (Results 1 – 8 of 8) sorted by relevance
62 u_int h_sync_width; member
126 vidc.h_sync_width = var->hsync_len - 8; in acornfb_set_timing()127 vidc.h_border_start = vidc.h_sync_width + var->left_margin + 8 - 12; in acornfb_set_timing()168 vidc_writel(0x81000000 | vidc.h_sync_width); in acornfb_set_timing()230 printk(KERN_DEBUG " H-sync-width : %d\n", vidc.h_sync_width); in acornfb_set_timing()
512 uint16_t h_start_width, uint16_t h_sync_width, in sdc_init_panel() argument526 if (v_sync_width == 0 || h_sync_width == 0) in sdc_init_panel()530 reg = ((uint32_t) (h_sync_width - 1) << 26) | in sdc_init_panel()
837 unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey; in tegra_hdmi_encoder_enable() local850 h_sync_width = mode->hsync_end - mode->hsync_start; in tegra_hdmi_encoder_enable()879 pulse_start = 1 + h_sync_width + h_back_porch - 10; in tegra_hdmi_encoder_enable()927 value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch + in tegra_hdmi_encoder_enable()
83 u8 h_sync_width; /**< lower 8 bits (pixels) */ member
853 dtd->part2.h_sync_width = h_sync_len & 0xff; in intel_sdvo_get_dtd_from_mode()880 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; in intel_sdvo_get_mode_from_dtd()
78 u8 h_sync_width; /**< lower 8 bits (pixels) */ member
752 dtd->part2.h_sync_width = h_sync_len & 0xff; in psb_intel_sdvo_get_dtd_from_mode()777 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width; in psb_intel_sdvo_get_mode_from_dtd()