Searched refs:gfx (Results 1 - 87 of 87) sorted by relevance

/linux-4.4.14/sound/hda/
H A DMakefile7 # for sync with i915 gfx driver
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_gfx.c44 for (i = 0; i < adev->gfx.scratch.num_reg; i++) { amdgpu_gfx_scratch_get()
45 if (adev->gfx.scratch.free[i]) { amdgpu_gfx_scratch_get()
46 adev->gfx.scratch.free[i] = false; amdgpu_gfx_scratch_get()
47 *reg = adev->gfx.scratch.reg[i]; amdgpu_gfx_scratch_get()
66 for (i = 0; i < adev->gfx.scratch.num_reg; i++) { amdgpu_gfx_scratch_free()
67 if (adev->gfx.scratch.reg[i] == reg) { amdgpu_gfx_scratch_free()
68 adev->gfx.scratch.free[i] = true; amdgpu_gfx_scratch_free()
H A Dgfx_v7_0.c928 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); gfx_v7_0_init_microcode()
931 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); gfx_v7_0_init_microcode()
936 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); gfx_v7_0_init_microcode()
939 err = amdgpu_ucode_validate(adev->gfx.me_fw); gfx_v7_0_init_microcode()
944 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); gfx_v7_0_init_microcode()
947 err = amdgpu_ucode_validate(adev->gfx.ce_fw); gfx_v7_0_init_microcode()
952 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); gfx_v7_0_init_microcode()
955 err = amdgpu_ucode_validate(adev->gfx.mec_fw); gfx_v7_0_init_microcode()
961 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); gfx_v7_0_init_microcode()
964 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); gfx_v7_0_init_microcode()
970 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); gfx_v7_0_init_microcode()
973 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); gfx_v7_0_init_microcode()
980 release_firmware(adev->gfx.pfp_fw); gfx_v7_0_init_microcode()
981 adev->gfx.pfp_fw = NULL; gfx_v7_0_init_microcode()
982 release_firmware(adev->gfx.me_fw); gfx_v7_0_init_microcode()
983 adev->gfx.me_fw = NULL; gfx_v7_0_init_microcode()
984 release_firmware(adev->gfx.ce_fw); gfx_v7_0_init_microcode()
985 adev->gfx.ce_fw = NULL; gfx_v7_0_init_microcode()
986 release_firmware(adev->gfx.mec_fw); gfx_v7_0_init_microcode()
987 adev->gfx.mec_fw = NULL; gfx_v7_0_init_microcode()
988 release_firmware(adev->gfx.mec2_fw); gfx_v7_0_init_microcode()
989 adev->gfx.mec2_fw = NULL; gfx_v7_0_init_microcode()
990 release_firmware(adev->gfx.rlc_fw); gfx_v7_0_init_microcode()
991 adev->gfx.rlc_fw = NULL; gfx_v7_0_init_microcode()
1013 switch (adev->gfx.config.mem_row_size_in_kb) { gfx_v7_0_tiling_mode_table_init()
1199 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; gfx_v7_0_tiling_mode_table_init()
1292 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; gfx_v7_0_tiling_mode_table_init()
1484 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; gfx_v7_0_tiling_mode_table_init()
1577 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; gfx_v7_0_tiling_mode_table_init()
1756 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; gfx_v7_0_tiling_mode_table_init()
1849 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; gfx_v7_0_tiling_mode_table_init()
1977 adev->gfx.config.backend_enable_mask = enabled_rbs; gfx_v7_0_setup_rb()
2071 adev->gfx.config.max_shader_engines = 2; gfx_v7_0_gpu_init()
2072 adev->gfx.config.max_tile_pipes = 4; gfx_v7_0_gpu_init()
2073 adev->gfx.config.max_cu_per_sh = 7; gfx_v7_0_gpu_init()
2074 adev->gfx.config.max_sh_per_se = 1; gfx_v7_0_gpu_init()
2075 adev->gfx.config.max_backends_per_se = 2; gfx_v7_0_gpu_init()
2076 adev->gfx.config.max_texture_channel_caches = 4; gfx_v7_0_gpu_init()
2077 adev->gfx.config.max_gprs = 256; gfx_v7_0_gpu_init()
2078 adev->gfx.config.max_gs_threads = 32; gfx_v7_0_gpu_init()
2079 adev->gfx.config.max_hw_contexts = 8; gfx_v7_0_gpu_init()
2081 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; gfx_v7_0_gpu_init()
2082 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; gfx_v7_0_gpu_init()
2083 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; gfx_v7_0_gpu_init()
2084 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; gfx_v7_0_gpu_init()
2088 adev->gfx.config.max_shader_engines = 4; gfx_v7_0_gpu_init()
2089 adev->gfx.config.max_tile_pipes = 16; gfx_v7_0_gpu_init()
2090 adev->gfx.config.max_cu_per_sh = 11; gfx_v7_0_gpu_init()
2091 adev->gfx.config.max_sh_per_se = 1; gfx_v7_0_gpu_init()
2092 adev->gfx.config.max_backends_per_se = 4; gfx_v7_0_gpu_init()
2093 adev->gfx.config.max_texture_channel_caches = 16; gfx_v7_0_gpu_init()
2094 adev->gfx.config.max_gprs = 256; gfx_v7_0_gpu_init()
2095 adev->gfx.config.max_gs_threads = 32; gfx_v7_0_gpu_init()
2096 adev->gfx.config.max_hw_contexts = 8; gfx_v7_0_gpu_init()
2098 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; gfx_v7_0_gpu_init()
2099 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; gfx_v7_0_gpu_init()
2100 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; gfx_v7_0_gpu_init()
2101 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; gfx_v7_0_gpu_init()
2105 adev->gfx.config.max_shader_engines = 1; gfx_v7_0_gpu_init()
2106 adev->gfx.config.max_tile_pipes = 4; gfx_v7_0_gpu_init()
2114 adev->gfx.config.max_cu_per_sh = 8; gfx_v7_0_gpu_init()
2115 adev->gfx.config.max_backends_per_se = 2; gfx_v7_0_gpu_init()
2121 adev->gfx.config.max_cu_per_sh = 6; gfx_v7_0_gpu_init()
2122 adev->gfx.config.max_backends_per_se = 2; gfx_v7_0_gpu_init()
2129 adev->gfx.config.max_cu_per_sh = 4; gfx_v7_0_gpu_init()
2130 adev->gfx.config.max_backends_per_se = 1; gfx_v7_0_gpu_init()
2132 adev->gfx.config.max_cu_per_sh = 3; gfx_v7_0_gpu_init()
2133 adev->gfx.config.max_backends_per_se = 1; gfx_v7_0_gpu_init()
2135 adev->gfx.config.max_sh_per_se = 1; gfx_v7_0_gpu_init()
2136 adev->gfx.config.max_texture_channel_caches = 4; gfx_v7_0_gpu_init()
2137 adev->gfx.config.max_gprs = 256; gfx_v7_0_gpu_init()
2138 adev->gfx.config.max_gs_threads = 16; gfx_v7_0_gpu_init()
2139 adev->gfx.config.max_hw_contexts = 8; gfx_v7_0_gpu_init()
2141 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; gfx_v7_0_gpu_init()
2142 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; gfx_v7_0_gpu_init()
2143 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; gfx_v7_0_gpu_init()
2144 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; gfx_v7_0_gpu_init()
2150 adev->gfx.config.max_shader_engines = 1; gfx_v7_0_gpu_init()
2151 adev->gfx.config.max_tile_pipes = 2; gfx_v7_0_gpu_init()
2152 adev->gfx.config.max_cu_per_sh = 2; gfx_v7_0_gpu_init()
2153 adev->gfx.config.max_sh_per_se = 1; gfx_v7_0_gpu_init()
2154 adev->gfx.config.max_backends_per_se = 1; gfx_v7_0_gpu_init()
2155 adev->gfx.config.max_texture_channel_caches = 2; gfx_v7_0_gpu_init()
2156 adev->gfx.config.max_gprs = 256; gfx_v7_0_gpu_init()
2157 adev->gfx.config.max_gs_threads = 16; gfx_v7_0_gpu_init()
2158 adev->gfx.config.max_hw_contexts = 8; gfx_v7_0_gpu_init()
2160 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; gfx_v7_0_gpu_init()
2161 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; gfx_v7_0_gpu_init()
2162 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; gfx_v7_0_gpu_init()
2163 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; gfx_v7_0_gpu_init()
2171 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); gfx_v7_0_gpu_init()
2172 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; gfx_v7_0_gpu_init()
2174 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; gfx_v7_0_gpu_init()
2175 adev->gfx.config.mem_max_burst_length_bytes = 256; gfx_v7_0_gpu_init()
2199 adev->gfx.config.mem_row_size_in_kb = 2; gfx_v7_0_gpu_init()
2201 adev->gfx.config.mem_row_size_in_kb = 1; gfx_v7_0_gpu_init()
2204 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; gfx_v7_0_gpu_init()
2205 if (adev->gfx.config.mem_row_size_in_kb > 4) gfx_v7_0_gpu_init()
2206 adev->gfx.config.mem_row_size_in_kb = 4; gfx_v7_0_gpu_init()
2209 adev->gfx.config.shader_engine_tile_size = 32; gfx_v7_0_gpu_init()
2210 adev->gfx.config.num_gpus = 1; gfx_v7_0_gpu_init()
2211 adev->gfx.config.multi_gpu_tile_size = 64; gfx_v7_0_gpu_init()
2215 switch (adev->gfx.config.mem_row_size_in_kb) { gfx_v7_0_gpu_init()
2227 adev->gfx.config.gb_addr_config = gb_addr_config; gfx_v7_0_gpu_init()
2240 gfx_v7_0_setup_rb(adev, adev->gfx.config.max_shader_engines, gfx_v7_0_gpu_init()
2241 adev->gfx.config.max_sh_per_se, gfx_v7_0_gpu_init()
2242 adev->gfx.config.max_backends_per_se); gfx_v7_0_gpu_init()
2302 ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | gfx_v7_0_gpu_init()
2303 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | gfx_v7_0_gpu_init()
2304 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | gfx_v7_0_gpu_init()
2305 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT))); gfx_v7_0_gpu_init()
2349 adev->gfx.scratch.num_reg = 7; gfx_v7_0_scratch_init()
2350 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; gfx_v7_0_scratch_init()
2351 for (i = 0; i < adev->gfx.scratch.num_reg; i++) { gfx_v7_0_scratch_init()
2352 adev->gfx.scratch.free[i] = true; gfx_v7_0_scratch_init()
2353 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i; gfx_v7_0_scratch_init()
2358 * gfx_v7_0_ring_test_ring - basic gfx ring test
2363 * Allocate a scratch register and write to it using the gfx ring (CIK).
2364 * Provides a basic gfx ring test to verify that the ring is working.
2450 * gfx_v7_0_ring_emit_fence_gfx - emit a fence on the gfx ring
2455 * Emits a fence sequnce number on the gfx ring and flushes
2559 * on the gfx ring. IBs are usually generated by userspace
2562 * on the gfx ring for execution by the GPU.
2643 * Allocate an IB and execute it on the gfx ring (CIK).
2644 * Provides a basic gfx ring test to verify that IBs are working.
2711 * On CIK, gfx and compute now have independant command processors.
2714 * Gfx consists of a single ring and can process both gfx jobs and
2715 * compute jobs. The gfx CP consists of three microengines (ME):
2733 * gfx_v7_0_cp_gfx_enable - enable/disable the gfx CP MEs
2738 * Halts or unhalts the gfx MEs.
2748 for (i = 0; i < adev->gfx.num_gfx_rings; i++) gfx_v7_0_cp_gfx_enable()
2749 adev->gfx.gfx_ring[i].ready = false; gfx_v7_0_cp_gfx_enable()
2755 * gfx_v7_0_cp_gfx_load_microcode - load the gfx CP ME ucode
2759 * Loads the gfx PFP, ME, and CE ucode.
2770 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) gfx_v7_0_cp_gfx_load_microcode()
2773 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; gfx_v7_0_cp_gfx_load_microcode()
2774 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; gfx_v7_0_cp_gfx_load_microcode()
2775 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; gfx_v7_0_cp_gfx_load_microcode()
2780 adev->gfx.pfp_fw_version = le32_to_cpu(pfp_hdr->header.ucode_version); gfx_v7_0_cp_gfx_load_microcode()
2781 adev->gfx.ce_fw_version = le32_to_cpu(ce_hdr->header.ucode_version); gfx_v7_0_cp_gfx_load_microcode()
2782 adev->gfx.me_fw_version = le32_to_cpu(me_hdr->header.ucode_version); gfx_v7_0_cp_gfx_load_microcode()
2783 adev->gfx.me_feature_version = le32_to_cpu(me_hdr->ucode_feature_version); gfx_v7_0_cp_gfx_load_microcode()
2784 adev->gfx.ce_feature_version = le32_to_cpu(ce_hdr->ucode_feature_version); gfx_v7_0_cp_gfx_load_microcode()
2785 adev->gfx.pfp_feature_version = le32_to_cpu(pfp_hdr->ucode_feature_version); gfx_v7_0_cp_gfx_load_microcode()
2791 (adev->gfx.pfp_fw->data + gfx_v7_0_cp_gfx_load_microcode()
2797 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); gfx_v7_0_cp_gfx_load_microcode()
2801 (adev->gfx.ce_fw->data + gfx_v7_0_cp_gfx_load_microcode()
2807 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); gfx_v7_0_cp_gfx_load_microcode()
2811 (adev->gfx.me_fw->data + gfx_v7_0_cp_gfx_load_microcode()
2817 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); gfx_v7_0_cp_gfx_load_microcode()
2823 * gfx_v7_0_cp_gfx_start - start the gfx ring
2833 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; gfx_v7_0_cp_gfx_start()
2839 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); gfx_v7_0_cp_gfx_start()
2851 /* init the CE partitions. CE only used for gfx on CIK */ gfx_v7_0_cp_gfx_start()
2865 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { gfx_v7_0_cp_gfx_start()
2920 * gfx_v7_0_cp_gfx_resume - setup the gfx ring buffer registers
2924 * Program the location and size of the gfx ring buffer
2948 /* ring 0 - compute and gfx */ gfx_v7_0_cp_gfx_resume()
2950 ring = &adev->gfx.gfx_ring[0]; gfx_v7_0_cp_gfx_resume()
3061 for (i = 0; i < adev->gfx.num_compute_rings; i++) gfx_v7_0_cp_compute_enable()
3062 adev->gfx.compute_ring[i].ready = false; gfx_v7_0_cp_compute_enable()
3081 if (!adev->gfx.mec_fw) gfx_v7_0_cp_compute_load_microcode()
3084 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; gfx_v7_0_cp_compute_load_microcode()
3086 adev->gfx.mec_fw_version = le32_to_cpu(mec_hdr->header.ucode_version); gfx_v7_0_cp_compute_load_microcode()
3087 adev->gfx.mec_feature_version = le32_to_cpu( gfx_v7_0_cp_compute_load_microcode()
3094 (adev->gfx.mec_fw->data + gfx_v7_0_cp_compute_load_microcode()
3105 if (!adev->gfx.mec2_fw) gfx_v7_0_cp_compute_load_microcode()
3108 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; gfx_v7_0_cp_compute_load_microcode()
3110 adev->gfx.mec2_fw_version = le32_to_cpu(mec2_hdr->header.ucode_version); gfx_v7_0_cp_compute_load_microcode()
3111 adev->gfx.mec2_feature_version = le32_to_cpu( gfx_v7_0_cp_compute_load_microcode()
3116 (adev->gfx.mec2_fw->data + gfx_v7_0_cp_compute_load_microcode()
3155 for (i = 0; i < adev->gfx.num_compute_rings; i++) { gfx_v7_0_cp_compute_fini()
3156 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; gfx_v7_0_cp_compute_fini()
3176 if (adev->gfx.mec.hpd_eop_obj) { gfx_v7_0_mec_fini()
3177 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); gfx_v7_0_mec_fini()
3180 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj); gfx_v7_0_mec_fini()
3181 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); gfx_v7_0_mec_fini()
3183 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj); gfx_v7_0_mec_fini()
3184 adev->gfx.mec.hpd_eop_obj = NULL; gfx_v7_0_mec_fini()
3201 adev->gfx.mec.num_mec = 1; gfx_v7_0_mec_init()
3202 adev->gfx.mec.num_pipe = 1; gfx_v7_0_mec_init()
3203 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8; gfx_v7_0_mec_init()
3205 if (adev->gfx.mec.hpd_eop_obj == NULL) { gfx_v7_0_mec_init()
3207 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2, gfx_v7_0_mec_init()
3210 &adev->gfx.mec.hpd_eop_obj); gfx_v7_0_mec_init()
3217 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); gfx_v7_0_mec_init()
3222 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT, gfx_v7_0_mec_init()
3223 &adev->gfx.mec.hpd_eop_gpu_addr); gfx_v7_0_mec_init()
3229 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd); gfx_v7_0_mec_init()
3237 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2); gfx_v7_0_mec_init()
3239 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); gfx_v7_0_mec_init()
3240 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); gfx_v7_0_mec_init()
3344 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) { gfx_v7_0_cp_compute_resume()
3348 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2); gfx_v7_0_cp_compute_resume()
3369 for (i = 0; i < adev->gfx.num_compute_rings; i++) { gfx_v7_0_cp_compute_resume()
3370 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; gfx_v7_0_cp_compute_resume()
3708 if (adev->gfx.rlc.save_restore_obj) { gfx_v7_0_rlc_fini()
3709 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false); gfx_v7_0_rlc_fini()
3712 amdgpu_bo_unpin(adev->gfx.rlc.save_restore_obj); gfx_v7_0_rlc_fini()
3713 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); gfx_v7_0_rlc_fini()
3715 amdgpu_bo_unref(&adev->gfx.rlc.save_restore_obj); gfx_v7_0_rlc_fini()
3716 adev->gfx.rlc.save_restore_obj = NULL; gfx_v7_0_rlc_fini()
3720 if (adev->gfx.rlc.clear_state_obj) { gfx_v7_0_rlc_fini()
3721 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); gfx_v7_0_rlc_fini()
3724 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); gfx_v7_0_rlc_fini()
3725 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); gfx_v7_0_rlc_fini()
3727 amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); gfx_v7_0_rlc_fini()
3728 adev->gfx.rlc.clear_state_obj = NULL; gfx_v7_0_rlc_fini()
3732 if (adev->gfx.rlc.cp_table_obj) { gfx_v7_0_rlc_fini()
3733 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false); gfx_v7_0_rlc_fini()
3736 amdgpu_bo_unpin(adev->gfx.rlc.cp_table_obj); gfx_v7_0_rlc_fini()
3737 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); gfx_v7_0_rlc_fini()
3739 amdgpu_bo_unref(&adev->gfx.rlc.cp_table_obj); gfx_v7_0_rlc_fini()
3740 adev->gfx.rlc.cp_table_obj = NULL; gfx_v7_0_rlc_fini()
3755 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list; gfx_v7_0_rlc_init()
3756 adev->gfx.rlc.reg_list_size = gfx_v7_0_rlc_init()
3759 adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list; gfx_v7_0_rlc_init()
3760 adev->gfx.rlc.reg_list_size = gfx_v7_0_rlc_init()
3764 adev->gfx.rlc.cs_data = ci_cs_data; gfx_v7_0_rlc_init()
3765 adev->gfx.rlc.cp_table_size = CP_ME_TABLE_SIZE * 5 * 4; gfx_v7_0_rlc_init()
3767 src_ptr = adev->gfx.rlc.reg_list; gfx_v7_0_rlc_init()
3768 dws = adev->gfx.rlc.reg_list_size; gfx_v7_0_rlc_init()
3771 cs_data = adev->gfx.rlc.cs_data; gfx_v7_0_rlc_init()
3775 if (adev->gfx.rlc.save_restore_obj == NULL) { gfx_v7_0_rlc_init()
3780 &adev->gfx.rlc.save_restore_obj); gfx_v7_0_rlc_init()
3787 r = amdgpu_bo_reserve(adev->gfx.rlc.save_restore_obj, false); gfx_v7_0_rlc_init()
3792 r = amdgpu_bo_pin(adev->gfx.rlc.save_restore_obj, AMDGPU_GEM_DOMAIN_VRAM, gfx_v7_0_rlc_init()
3793 &adev->gfx.rlc.save_restore_gpu_addr); gfx_v7_0_rlc_init()
3795 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); gfx_v7_0_rlc_init()
3801 r = amdgpu_bo_kmap(adev->gfx.rlc.save_restore_obj, (void **)&adev->gfx.rlc.sr_ptr); gfx_v7_0_rlc_init()
3808 dst_ptr = adev->gfx.rlc.sr_ptr; gfx_v7_0_rlc_init()
3809 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) gfx_v7_0_rlc_init()
3811 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj); gfx_v7_0_rlc_init()
3812 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj); gfx_v7_0_rlc_init()
3817 adev->gfx.rlc.clear_state_size = dws = gfx_v7_0_get_csb_size(adev); gfx_v7_0_rlc_init()
3819 if (adev->gfx.rlc.clear_state_obj == NULL) { gfx_v7_0_rlc_init()
3824 &adev->gfx.rlc.clear_state_obj); gfx_v7_0_rlc_init()
3831 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); gfx_v7_0_rlc_init()
3836 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, AMDGPU_GEM_DOMAIN_VRAM, gfx_v7_0_rlc_init()
3837 &adev->gfx.rlc.clear_state_gpu_addr); gfx_v7_0_rlc_init()
3839 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); gfx_v7_0_rlc_init()
3845 r = amdgpu_bo_kmap(adev->gfx.rlc.clear_state_obj, (void **)&adev->gfx.rlc.cs_ptr); gfx_v7_0_rlc_init()
3852 dst_ptr = adev->gfx.rlc.cs_ptr; gfx_v7_0_rlc_init()
3854 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj); gfx_v7_0_rlc_init()
3855 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); gfx_v7_0_rlc_init()
3858 if (adev->gfx.rlc.cp_table_size) { gfx_v7_0_rlc_init()
3859 if (adev->gfx.rlc.cp_table_obj == NULL) { gfx_v7_0_rlc_init()
3860 r = amdgpu_bo_create(adev, adev->gfx.rlc.cp_table_size, PAGE_SIZE, true, gfx_v7_0_rlc_init()
3864 &adev->gfx.rlc.cp_table_obj); gfx_v7_0_rlc_init()
3872 r = amdgpu_bo_reserve(adev->gfx.rlc.cp_table_obj, false); gfx_v7_0_rlc_init()
3878 r = amdgpu_bo_pin(adev->gfx.rlc.cp_table_obj, AMDGPU_GEM_DOMAIN_VRAM, gfx_v7_0_rlc_init()
3879 &adev->gfx.rlc.cp_table_gpu_addr); gfx_v7_0_rlc_init()
3881 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); gfx_v7_0_rlc_init()
3886 r = amdgpu_bo_kmap(adev->gfx.rlc.cp_table_obj, (void **)&adev->gfx.rlc.cp_table_ptr); gfx_v7_0_rlc_init()
3895 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj); gfx_v7_0_rlc_init()
3896 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj); gfx_v7_0_rlc_init()
3921 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { gfx_v7_0_wait_for_rlc_serdes()
3922 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { gfx_v7_0_wait_for_rlc_serdes()
4068 if (!adev->gfx.rlc_fw) gfx_v7_0_rlc_resume()
4071 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; gfx_v7_0_rlc_resume()
4073 adev->gfx.rlc_fw_version = le32_to_cpu(hdr->header.ucode_version); gfx_v7_0_rlc_resume()
4074 adev->gfx.rlc_feature_version = le32_to_cpu( gfx_v7_0_rlc_resume()
4101 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); gfx_v7_0_rlc_resume()
4106 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); gfx_v7_0_rlc_resume()
4324 if (adev->gfx.rlc.cp_table_ptr == NULL) gfx_v7_0_init_cp_pg_table()
4328 dst_ptr = adev->gfx.rlc.cp_table_ptr; gfx_v7_0_init_cp_pg_table()
4332 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; gfx_v7_0_init_cp_pg_table()
4334 (adev->gfx.ce_fw->data + gfx_v7_0_init_cp_pg_table()
4340 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; gfx_v7_0_init_cp_pg_table()
4342 (adev->gfx.pfp_fw->data + gfx_v7_0_init_cp_pg_table()
4348 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; gfx_v7_0_init_cp_pg_table()
4350 (adev->gfx.me_fw->data + gfx_v7_0_init_cp_pg_table()
4356 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; gfx_v7_0_init_cp_pg_table()
4358 (adev->gfx.mec_fw->data + gfx_v7_0_init_cp_pg_table()
4364 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; gfx_v7_0_init_cp_pg_table()
4366 (adev->gfx.mec2_fw->data + gfx_v7_0_init_cp_pg_table()
4427 for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) { gfx_v7_0_get_cu_active_bitmap()
4488 if (adev->gfx.rlc.cs_data) { gfx_v7_0_init_gfx_cgpg()
4490 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); gfx_v7_0_init_gfx_cgpg()
4491 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr)); gfx_v7_0_init_gfx_cgpg()
4492 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size); gfx_v7_0_init_gfx_cgpg()
4498 if (adev->gfx.rlc.reg_list) { gfx_v7_0_init_gfx_cgpg()
4500 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++) gfx_v7_0_init_gfx_cgpg()
4501 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]); gfx_v7_0_init_gfx_cgpg()
4509 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8); gfx_v7_0_init_gfx_cgpg()
4510 WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8); gfx_v7_0_init_gfx_cgpg()
4545 if (adev->gfx.rlc.cs_data == NULL) gfx_v7_0_get_csb_size()
4553 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { gfx_v7_0_get_csb_size()
4578 if (adev->gfx.rlc.cs_data == NULL) gfx_v7_0_get_csb_buffer()
4590 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { gfx_v7_0_get_csb_buffer()
4685 mutex_lock(&adev->gfx.gpu_clock_mutex); gfx_v7_0_get_gpu_clock_counter()
4689 mutex_unlock(&adev->gfx.gpu_clock_mutex); gfx_v7_0_get_gpu_clock_counter()
4745 adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS; gfx_v7_0_early_init()
4746 adev->gfx.num_compute_rings = GFX7_NUM_COMPUTE_RINGS; gfx_v7_0_early_init()
4761 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq); gfx_v7_0_sw_init()
4766 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq); gfx_v7_0_sw_init()
4771 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq); gfx_v7_0_sw_init()
4779 DRM_ERROR("Failed to load gfx firmware!\n"); gfx_v7_0_sw_init()
4796 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { gfx_v7_0_sw_init()
4797 ring = &adev->gfx.gfx_ring[i]; gfx_v7_0_sw_init()
4799 sprintf(ring->name, "gfx"); gfx_v7_0_sw_init()
4802 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP, gfx_v7_0_sw_init()
4809 for (i = 0; i < adev->gfx.num_compute_rings; i++) { gfx_v7_0_sw_init()
4817 ring = &adev->gfx.compute_ring[i]; gfx_v7_0_sw_init()
4829 &adev->gfx.eop_irq, irq_type, gfx_v7_0_sw_init()
4835 /* reserve GDS, GWS and OA resource for gfx */ gfx_v7_0_sw_init()
4869 for (i = 0; i < adev->gfx.num_gfx_rings; i++) gfx_v7_0_sw_fini()
4870 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); gfx_v7_0_sw_fini()
4871 for (i = 0; i < adev->gfx.num_compute_rings; i++) gfx_v7_0_sw_fini()
4872 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); gfx_v7_0_sw_fini()
4897 adev->gfx.ce_ram_size = 0x8000; gfx_v7_0_hw_init()
4997 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { gfx_v7_0_print_status()
5108 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) { gfx_v7_0_print_status()
5460 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); gfx_v7_0_eop_irq()
5464 for (i = 0; i < adev->gfx.num_compute_rings; i++) { gfx_v7_0_eop_irq()
5465 ring = &adev->gfx.compute_ring[i]; gfx_v7_0_eop_irq()
5488 // XXX soft reset the gfx block only gfx_v7_0_priv_inst_irq()
5594 for (i = 0; i < adev->gfx.num_gfx_rings; i++) gfx_v7_0_set_ring_funcs()
5595 adev->gfx.gfx_ring[i].funcs = &gfx_v7_0_ring_funcs_gfx; gfx_v7_0_set_ring_funcs()
5596 for (i = 0; i < adev->gfx.num_compute_rings; i++) gfx_v7_0_set_ring_funcs()
5597 adev->gfx.compute_ring[i].funcs = &gfx_v7_0_ring_funcs_compute; gfx_v7_0_set_ring_funcs()
5617 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; gfx_v7_0_set_irq_funcs()
5618 adev->gfx.eop_irq.funcs = &gfx_v7_0_eop_irq_funcs; gfx_v7_0_set_irq_funcs()
5620 adev->gfx.priv_reg_irq.num_types = 1; gfx_v7_0_set_irq_funcs()
5621 adev->gfx.priv_reg_irq.funcs = &gfx_v7_0_priv_reg_irq_funcs; gfx_v7_0_set_irq_funcs()
5623 adev->gfx.priv_inst_irq.num_types = 1; gfx_v7_0_set_irq_funcs()
5624 adev->gfx.priv_inst_irq.funcs = &gfx_v7_0_priv_inst_irq_funcs; gfx_v7_0_set_irq_funcs()
5666 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { gfx_v7_0_get_cu_info()
5667 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { gfx_v7_0_get_cu_info()
5674 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { gfx_v7_0_get_cu_info()
H A Dgfx_v8_0.c612 adev->gfx.scratch.num_reg = 7; gfx_v8_0_scratch_init()
613 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; gfx_v8_0_scratch_init()
614 for (i = 0; i < adev->gfx.scratch.num_reg; i++) { gfx_v8_0_scratch_init()
615 adev->gfx.scratch.free[i] = true; gfx_v8_0_scratch_init()
616 adev->gfx.scratch.reg[i] = adev->gfx.scratch.reg_base + i; gfx_v8_0_scratch_init()
757 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); gfx_v8_0_init_microcode()
760 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); gfx_v8_0_init_microcode()
763 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; gfx_v8_0_init_microcode()
764 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); gfx_v8_0_init_microcode()
765 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); gfx_v8_0_init_microcode()
768 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); gfx_v8_0_init_microcode()
771 err = amdgpu_ucode_validate(adev->gfx.me_fw); gfx_v8_0_init_microcode()
774 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; gfx_v8_0_init_microcode()
775 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); gfx_v8_0_init_microcode()
776 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); gfx_v8_0_init_microcode()
779 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); gfx_v8_0_init_microcode()
782 err = amdgpu_ucode_validate(adev->gfx.ce_fw); gfx_v8_0_init_microcode()
785 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; gfx_v8_0_init_microcode()
786 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); gfx_v8_0_init_microcode()
787 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); gfx_v8_0_init_microcode()
790 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); gfx_v8_0_init_microcode()
793 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); gfx_v8_0_init_microcode()
794 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.rlc_fw->data; gfx_v8_0_init_microcode()
795 adev->gfx.rlc_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); gfx_v8_0_init_microcode()
796 adev->gfx.rlc_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); gfx_v8_0_init_microcode()
799 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); gfx_v8_0_init_microcode()
802 err = amdgpu_ucode_validate(adev->gfx.mec_fw); gfx_v8_0_init_microcode()
805 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; gfx_v8_0_init_microcode()
806 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); gfx_v8_0_init_microcode()
807 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); gfx_v8_0_init_microcode()
812 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); gfx_v8_0_init_microcode()
814 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); gfx_v8_0_init_microcode()
818 adev->gfx.mec2_fw->data; gfx_v8_0_init_microcode()
819 adev->gfx.mec2_fw_version = gfx_v8_0_init_microcode()
821 adev->gfx.mec2_feature_version = gfx_v8_0_init_microcode()
825 adev->gfx.mec2_fw = NULL; gfx_v8_0_init_microcode()
832 info->fw = adev->gfx.pfp_fw; gfx_v8_0_init_microcode()
839 info->fw = adev->gfx.me_fw; gfx_v8_0_init_microcode()
846 info->fw = adev->gfx.ce_fw; gfx_v8_0_init_microcode()
853 info->fw = adev->gfx.rlc_fw; gfx_v8_0_init_microcode()
860 info->fw = adev->gfx.mec_fw; gfx_v8_0_init_microcode()
865 if (adev->gfx.mec2_fw) { gfx_v8_0_init_microcode()
868 info->fw = adev->gfx.mec2_fw; gfx_v8_0_init_microcode()
881 release_firmware(adev->gfx.pfp_fw); gfx_v8_0_init_microcode()
882 adev->gfx.pfp_fw = NULL; gfx_v8_0_init_microcode()
883 release_firmware(adev->gfx.me_fw); gfx_v8_0_init_microcode()
884 adev->gfx.me_fw = NULL; gfx_v8_0_init_microcode()
885 release_firmware(adev->gfx.ce_fw); gfx_v8_0_init_microcode()
886 adev->gfx.ce_fw = NULL; gfx_v8_0_init_microcode()
887 release_firmware(adev->gfx.rlc_fw); gfx_v8_0_init_microcode()
888 adev->gfx.rlc_fw = NULL; gfx_v8_0_init_microcode()
889 release_firmware(adev->gfx.mec_fw); gfx_v8_0_init_microcode()
890 adev->gfx.mec_fw = NULL; gfx_v8_0_init_microcode()
891 release_firmware(adev->gfx.mec2_fw); gfx_v8_0_init_microcode()
892 adev->gfx.mec2_fw = NULL; gfx_v8_0_init_microcode()
901 if (adev->gfx.mec.hpd_eop_obj) { gfx_v8_0_mec_fini()
902 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); gfx_v8_0_mec_fini()
905 amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj); gfx_v8_0_mec_fini()
906 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); gfx_v8_0_mec_fini()
908 amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj); gfx_v8_0_mec_fini()
909 adev->gfx.mec.hpd_eop_obj = NULL; gfx_v8_0_mec_fini()
924 adev->gfx.mec.num_mec = 1; gfx_v8_0_mec_init()
925 adev->gfx.mec.num_pipe = 1; gfx_v8_0_mec_init()
926 adev->gfx.mec.num_queue = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe * 8; gfx_v8_0_mec_init()
928 if (adev->gfx.mec.hpd_eop_obj == NULL) { gfx_v8_0_mec_init()
930 adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2, gfx_v8_0_mec_init()
933 &adev->gfx.mec.hpd_eop_obj); gfx_v8_0_mec_init()
940 r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false); gfx_v8_0_mec_init()
945 r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT, gfx_v8_0_mec_init()
946 &adev->gfx.mec.hpd_eop_gpu_addr); gfx_v8_0_mec_init()
952 r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd); gfx_v8_0_mec_init()
959 memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2); gfx_v8_0_mec_init()
961 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); gfx_v8_0_mec_init()
962 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); gfx_v8_0_mec_init()
976 adev->gfx.config.max_shader_engines = 1; gfx_v8_0_gpu_early_init()
977 adev->gfx.config.max_tile_pipes = 2; gfx_v8_0_gpu_early_init()
978 adev->gfx.config.max_cu_per_sh = 6; gfx_v8_0_gpu_early_init()
979 adev->gfx.config.max_sh_per_se = 1; gfx_v8_0_gpu_early_init()
980 adev->gfx.config.max_backends_per_se = 2; gfx_v8_0_gpu_early_init()
981 adev->gfx.config.max_texture_channel_caches = 2; gfx_v8_0_gpu_early_init()
982 adev->gfx.config.max_gprs = 256; gfx_v8_0_gpu_early_init()
983 adev->gfx.config.max_gs_threads = 32; gfx_v8_0_gpu_early_init()
984 adev->gfx.config.max_hw_contexts = 8; gfx_v8_0_gpu_early_init()
986 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; gfx_v8_0_gpu_early_init()
987 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; gfx_v8_0_gpu_early_init()
988 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; gfx_v8_0_gpu_early_init()
989 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; gfx_v8_0_gpu_early_init()
993 adev->gfx.config.max_shader_engines = 4; gfx_v8_0_gpu_early_init()
994 adev->gfx.config.max_tile_pipes = 16; gfx_v8_0_gpu_early_init()
995 adev->gfx.config.max_cu_per_sh = 16; gfx_v8_0_gpu_early_init()
996 adev->gfx.config.max_sh_per_se = 1; gfx_v8_0_gpu_early_init()
997 adev->gfx.config.max_backends_per_se = 4; gfx_v8_0_gpu_early_init()
998 adev->gfx.config.max_texture_channel_caches = 16; gfx_v8_0_gpu_early_init()
999 adev->gfx.config.max_gprs = 256; gfx_v8_0_gpu_early_init()
1000 adev->gfx.config.max_gs_threads = 32; gfx_v8_0_gpu_early_init()
1001 adev->gfx.config.max_hw_contexts = 8; gfx_v8_0_gpu_early_init()
1003 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; gfx_v8_0_gpu_early_init()
1004 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; gfx_v8_0_gpu_early_init()
1005 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; gfx_v8_0_gpu_early_init()
1006 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; gfx_v8_0_gpu_early_init()
1010 adev->gfx.config.max_shader_engines = 4; gfx_v8_0_gpu_early_init()
1011 adev->gfx.config.max_tile_pipes = 8; gfx_v8_0_gpu_early_init()
1012 adev->gfx.config.max_cu_per_sh = 8; gfx_v8_0_gpu_early_init()
1013 adev->gfx.config.max_sh_per_se = 1; gfx_v8_0_gpu_early_init()
1014 adev->gfx.config.max_backends_per_se = 2; gfx_v8_0_gpu_early_init()
1015 adev->gfx.config.max_texture_channel_caches = 8; gfx_v8_0_gpu_early_init()
1016 adev->gfx.config.max_gprs = 256; gfx_v8_0_gpu_early_init()
1017 adev->gfx.config.max_gs_threads = 32; gfx_v8_0_gpu_early_init()
1018 adev->gfx.config.max_hw_contexts = 8; gfx_v8_0_gpu_early_init()
1020 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; gfx_v8_0_gpu_early_init()
1021 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; gfx_v8_0_gpu_early_init()
1022 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; gfx_v8_0_gpu_early_init()
1023 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; gfx_v8_0_gpu_early_init()
1027 adev->gfx.config.max_shader_engines = 1; gfx_v8_0_gpu_early_init()
1028 adev->gfx.config.max_tile_pipes = 2; gfx_v8_0_gpu_early_init()
1029 adev->gfx.config.max_sh_per_se = 1; gfx_v8_0_gpu_early_init()
1030 adev->gfx.config.max_backends_per_se = 2; gfx_v8_0_gpu_early_init()
1040 adev->gfx.config.max_cu_per_sh = 8; gfx_v8_0_gpu_early_init()
1050 adev->gfx.config.max_cu_per_sh = 6; gfx_v8_0_gpu_early_init()
1057 adev->gfx.config.max_cu_per_sh = 6; gfx_v8_0_gpu_early_init()
1066 adev->gfx.config.max_cu_per_sh = 4; gfx_v8_0_gpu_early_init()
1070 adev->gfx.config.max_texture_channel_caches = 2; gfx_v8_0_gpu_early_init()
1071 adev->gfx.config.max_gprs = 256; gfx_v8_0_gpu_early_init()
1072 adev->gfx.config.max_gs_threads = 32; gfx_v8_0_gpu_early_init()
1073 adev->gfx.config.max_hw_contexts = 8; gfx_v8_0_gpu_early_init()
1075 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; gfx_v8_0_gpu_early_init()
1076 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; gfx_v8_0_gpu_early_init()
1077 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; gfx_v8_0_gpu_early_init()
1078 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; gfx_v8_0_gpu_early_init()
1082 adev->gfx.config.max_shader_engines = 1; gfx_v8_0_gpu_early_init()
1083 adev->gfx.config.max_tile_pipes = 2; gfx_v8_0_gpu_early_init()
1084 adev->gfx.config.max_sh_per_se = 1; gfx_v8_0_gpu_early_init()
1085 adev->gfx.config.max_backends_per_se = 1; gfx_v8_0_gpu_early_init()
1094 adev->gfx.config.max_cu_per_sh = 3; gfx_v8_0_gpu_early_init()
1100 adev->gfx.config.max_cu_per_sh = 2; gfx_v8_0_gpu_early_init()
1104 adev->gfx.config.max_texture_channel_caches = 2; gfx_v8_0_gpu_early_init()
1105 adev->gfx.config.max_gprs = 256; gfx_v8_0_gpu_early_init()
1106 adev->gfx.config.max_gs_threads = 16; gfx_v8_0_gpu_early_init()
1107 adev->gfx.config.max_hw_contexts = 8; gfx_v8_0_gpu_early_init()
1109 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; gfx_v8_0_gpu_early_init()
1110 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; gfx_v8_0_gpu_early_init()
1111 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; gfx_v8_0_gpu_early_init()
1112 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; gfx_v8_0_gpu_early_init()
1116 adev->gfx.config.max_shader_engines = 2; gfx_v8_0_gpu_early_init()
1117 adev->gfx.config.max_tile_pipes = 4; gfx_v8_0_gpu_early_init()
1118 adev->gfx.config.max_cu_per_sh = 2; gfx_v8_0_gpu_early_init()
1119 adev->gfx.config.max_sh_per_se = 1; gfx_v8_0_gpu_early_init()
1120 adev->gfx.config.max_backends_per_se = 2; gfx_v8_0_gpu_early_init()
1121 adev->gfx.config.max_texture_channel_caches = 4; gfx_v8_0_gpu_early_init()
1122 adev->gfx.config.max_gprs = 256; gfx_v8_0_gpu_early_init()
1123 adev->gfx.config.max_gs_threads = 32; gfx_v8_0_gpu_early_init()
1124 adev->gfx.config.max_hw_contexts = 8; gfx_v8_0_gpu_early_init()
1126 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; gfx_v8_0_gpu_early_init()
1127 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; gfx_v8_0_gpu_early_init()
1128 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; gfx_v8_0_gpu_early_init()
1129 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; gfx_v8_0_gpu_early_init()
1135 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); gfx_v8_0_gpu_early_init()
1136 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; gfx_v8_0_gpu_early_init()
1138 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; gfx_v8_0_gpu_early_init()
1139 adev->gfx.config.mem_max_burst_length_bytes = 256; gfx_v8_0_gpu_early_init()
1163 adev->gfx.config.mem_row_size_in_kb = 2; gfx_v8_0_gpu_early_init()
1165 adev->gfx.config.mem_row_size_in_kb = 1; gfx_v8_0_gpu_early_init()
1168 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; gfx_v8_0_gpu_early_init()
1169 if (adev->gfx.config.mem_row_size_in_kb > 4) gfx_v8_0_gpu_early_init()
1170 adev->gfx.config.mem_row_size_in_kb = 4; gfx_v8_0_gpu_early_init()
1173 adev->gfx.config.shader_engine_tile_size = 32; gfx_v8_0_gpu_early_init()
1174 adev->gfx.config.num_gpus = 1; gfx_v8_0_gpu_early_init()
1175 adev->gfx.config.multi_gpu_tile_size = 64; gfx_v8_0_gpu_early_init()
1178 switch (adev->gfx.config.mem_row_size_in_kb) { gfx_v8_0_gpu_early_init()
1190 adev->gfx.config.gb_addr_config = gb_addr_config; gfx_v8_0_gpu_early_init()
1200 r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq); gfx_v8_0_sw_init()
1205 r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq); gfx_v8_0_sw_init()
1210 r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq); gfx_v8_0_sw_init()
1214 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; gfx_v8_0_sw_init()
1220 DRM_ERROR("Failed to load gfx firmware!\n"); gfx_v8_0_sw_init()
1230 /* set up the gfx ring */ gfx_v8_0_sw_init()
1231 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { gfx_v8_0_sw_init()
1232 ring = &adev->gfx.gfx_ring[i]; gfx_v8_0_sw_init()
1234 sprintf(ring->name, "gfx"); gfx_v8_0_sw_init()
1235 /* no gfx doorbells on iceland */ gfx_v8_0_sw_init()
1243 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP, gfx_v8_0_sw_init()
1250 for (i = 0; i < adev->gfx.num_compute_rings; i++) { gfx_v8_0_sw_init()
1258 ring = &adev->gfx.compute_ring[i]; gfx_v8_0_sw_init()
1270 &adev->gfx.eop_irq, irq_type, gfx_v8_0_sw_init()
1276 /* reserve GDS, GWS and OA resource for gfx */ gfx_v8_0_sw_init()
1298 adev->gfx.ce_ram_size = 0x8000; gfx_v8_0_sw_init()
1314 for (i = 0; i < adev->gfx.num_gfx_rings; i++) gfx_v8_0_sw_fini()
1315 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); gfx_v8_0_sw_fini()
1316 for (i = 0; i < adev->gfx.num_compute_rings; i++) gfx_v8_0_sw_fini()
1317 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); gfx_v8_0_sw_fini()
1330 switch (adev->gfx.config.mem_row_size_in_kb) { gfx_v8_0_tiling_mode_table_init()
1511 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; gfx_v8_0_tiling_mode_table_init()
1607 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; gfx_v8_0_tiling_mode_table_init()
1801 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; gfx_v8_0_tiling_mode_table_init()
1897 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; gfx_v8_0_tiling_mode_table_init()
2092 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; gfx_v8_0_tiling_mode_table_init()
2188 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; gfx_v8_0_tiling_mode_table_init()
2359 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; gfx_v8_0_tiling_mode_table_init()
2455 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; gfx_v8_0_tiling_mode_table_init()
2627 adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; gfx_v8_0_tiling_mode_table_init()
2723 adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; gfx_v8_0_tiling_mode_table_init()
2807 adev->gfx.config.backend_enable_mask = enabled_rbs; gfx_v8_0_setup_rb()
2899 WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); gfx_v8_0_gpu_init()
2900 WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); gfx_v8_0_gpu_init()
2901 WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); gfx_v8_0_gpu_init()
2903 adev->gfx.config.gb_addr_config & 0x70); gfx_v8_0_gpu_init()
2905 adev->gfx.config.gb_addr_config & 0x70); gfx_v8_0_gpu_init()
2906 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); gfx_v8_0_gpu_init()
2907 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); gfx_v8_0_gpu_init()
2908 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); gfx_v8_0_gpu_init()
2912 gfx_v8_0_setup_rb(adev, adev->gfx.config.max_shader_engines, gfx_v8_0_gpu_init()
2913 adev->gfx.config.max_sh_per_se, gfx_v8_0_gpu_init()
2914 adev->gfx.config.max_backends_per_se); gfx_v8_0_gpu_init()
2953 (adev->gfx.config.sc_prim_fifo_size_frontend << gfx_v8_0_gpu_init()
2955 (adev->gfx.config.sc_prim_fifo_size_backend << gfx_v8_0_gpu_init()
2957 (adev->gfx.config.sc_hiz_tile_fifo_size << gfx_v8_0_gpu_init()
2959 (adev->gfx.config.sc_earlyz_tile_fifo_size << gfx_v8_0_gpu_init()
2971 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { gfx_v8_0_wait_for_rlc_serdes()
2972 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { gfx_v8_0_wait_for_rlc_serdes()
3058 if (!adev->gfx.rlc_fw) gfx_v8_0_rlc_load_microcode()
3061 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; gfx_v8_0_rlc_load_microcode()
3064 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + gfx_v8_0_rlc_load_microcode()
3071 WREG32(mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); gfx_v8_0_rlc_load_microcode()
3120 for (i = 0; i < adev->gfx.num_gfx_rings; i++) gfx_v8_0_cp_gfx_enable()
3121 adev->gfx.gfx_ring[i].ready = false; gfx_v8_0_cp_gfx_enable()
3135 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) gfx_v8_0_cp_gfx_load_microcode()
3139 adev->gfx.pfp_fw->data; gfx_v8_0_cp_gfx_load_microcode()
3141 adev->gfx.ce_fw->data; gfx_v8_0_cp_gfx_load_microcode()
3143 adev->gfx.me_fw->data; gfx_v8_0_cp_gfx_load_microcode()
3153 (adev->gfx.pfp_fw->data + gfx_v8_0_cp_gfx_load_microcode()
3159 WREG32(mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); gfx_v8_0_cp_gfx_load_microcode()
3163 (adev->gfx.ce_fw->data + gfx_v8_0_cp_gfx_load_microcode()
3169 WREG32(mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); gfx_v8_0_cp_gfx_load_microcode()
3173 (adev->gfx.me_fw->data + gfx_v8_0_cp_gfx_load_microcode()
3179 WREG32(mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version); gfx_v8_0_cp_gfx_load_microcode()
3215 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0]; gfx_v8_0_cp_gfx_start()
3221 WREG32(mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1); gfx_v8_0_cp_gfx_start()
3311 ring = &adev->gfx.gfx_ring[0]; gfx_v8_0_cp_gfx_resume()
3339 /* no gfx doorbells on iceland */ gfx_v8_0_cp_gfx_resume()
3385 for (i = 0; i < adev->gfx.num_compute_rings; i++) gfx_v8_0_cp_compute_enable()
3386 adev->gfx.compute_ring[i].ready = false; gfx_v8_0_cp_compute_enable()
3404 if (!adev->gfx.mec_fw) gfx_v8_0_cp_compute_load_microcode()
3409 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; gfx_v8_0_cp_compute_load_microcode()
3413 (adev->gfx.mec_fw->data + gfx_v8_0_cp_compute_load_microcode()
3421 WREG32(mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); gfx_v8_0_cp_compute_load_microcode()
3424 if (adev->gfx.mec2_fw) { gfx_v8_0_cp_compute_load_microcode()
3427 mec2_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data; gfx_v8_0_cp_compute_load_microcode()
3431 (adev->gfx.mec2_fw->data + gfx_v8_0_cp_compute_load_microcode()
3438 WREG32(mmCP_MEC_ME2_UCODE_ADDR, adev->gfx.mec2_fw_version); gfx_v8_0_cp_compute_load_microcode()
3709 for (i = 0; i < adev->gfx.num_compute_rings; i++) { gfx_v8_0_cp_compute_fini()
3710 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; gfx_v8_0_cp_compute_fini()
3740 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) { gfx_v8_0_cp_compute_resume()
3744 eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE); gfx_v8_0_cp_compute_resume()
3766 for (i = 0; i < adev->gfx.num_compute_rings; i++) { gfx_v8_0_cp_compute_resume()
3767 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; gfx_v8_0_cp_compute_resume()
3966 for (i = 0; i < adev->gfx.num_compute_rings; i++) { gfx_v8_0_cp_compute_resume()
3967 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i]; gfx_v8_0_cp_compute_resume()
4150 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { gfx_v8_0_print_status()
4392 mutex_lock(&adev->gfx.gpu_clock_mutex); gfx_v8_0_get_gpu_clock_counter()
4396 mutex_unlock(&adev->gfx.gpu_clock_mutex); gfx_v8_0_get_gpu_clock_counter()
4452 adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS; gfx_v8_0_early_init()
4453 adev->gfx.num_compute_rings = GFX8_NUM_COMPUTE_RINGS; gfx_v8_0_early_init()
4962 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); gfx_v8_0_eop_irq()
4966 for (i = 0; i < adev->gfx.num_compute_rings; i++) { gfx_v8_0_eop_irq()
4967 ring = &adev->gfx.compute_ring[i]; gfx_v8_0_eop_irq()
5050 for (i = 0; i < adev->gfx.num_gfx_rings; i++) gfx_v8_0_set_ring_funcs()
5051 adev->gfx.gfx_ring[i].funcs = &gfx_v8_0_ring_funcs_gfx; gfx_v8_0_set_ring_funcs()
5053 for (i = 0; i < adev->gfx.num_compute_rings; i++) gfx_v8_0_set_ring_funcs()
5054 adev->gfx.compute_ring[i].funcs = &gfx_v8_0_ring_funcs_compute; gfx_v8_0_set_ring_funcs()
5074 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; gfx_v8_0_set_irq_funcs()
5075 adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs; gfx_v8_0_set_irq_funcs()
5077 adev->gfx.priv_reg_irq.num_types = 1; gfx_v8_0_set_irq_funcs()
5078 adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs; gfx_v8_0_set_irq_funcs()
5080 adev->gfx.priv_inst_irq.num_types = 1; gfx_v8_0_set_irq_funcs()
5081 adev->gfx.priv_inst_irq.funcs = &gfx_v8_0_priv_inst_irq_funcs; gfx_v8_0_set_irq_funcs()
5128 for (i = 0; i < adev->gfx.config.max_cu_per_sh; i ++) { gfx_v8_0_get_cu_active_bitmap()
5146 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { gfx_v8_0_get_cu_info()
5147 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { gfx_v8_0_get_cu_info()
5154 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) { gfx_v8_0_get_cu_info()
H A Damdgpu_kms.c207 for (i = 0; i < adev->gfx.num_gfx_rings; i++) amdgpu_info_ioctl()
208 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i); amdgpu_info_ioctl()
214 for (i = 0; i < adev->gfx.num_compute_rings; i++) amdgpu_info_ioctl()
215 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i); amdgpu_info_ioctl()
314 fw_info.ver = adev->gfx.me_fw_version; amdgpu_info_ioctl()
315 fw_info.feature = adev->gfx.me_feature_version; amdgpu_info_ioctl()
318 fw_info.ver = adev->gfx.pfp_fw_version; amdgpu_info_ioctl()
319 fw_info.feature = adev->gfx.pfp_feature_version; amdgpu_info_ioctl()
322 fw_info.ver = adev->gfx.ce_fw_version; amdgpu_info_ioctl()
323 fw_info.feature = adev->gfx.ce_feature_version; amdgpu_info_ioctl()
326 fw_info.ver = adev->gfx.rlc_fw_version; amdgpu_info_ioctl()
327 fw_info.feature = adev->gfx.rlc_feature_version; amdgpu_info_ioctl()
331 fw_info.ver = adev->gfx.mec_fw_version; amdgpu_info_ioctl()
332 fw_info.feature = adev->gfx.mec_feature_version; amdgpu_info_ioctl()
334 fw_info.ver = adev->gfx.mec2_fw_version; amdgpu_info_ioctl()
335 fw_info.feature = adev->gfx.mec2_feature_version; amdgpu_info_ioctl()
436 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; amdgpu_info_ioctl()
437 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; amdgpu_info_ioctl()
449 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; amdgpu_info_ioctl()
450 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * amdgpu_info_ioctl()
451 adev->gfx.config.max_shader_engines; amdgpu_info_ioctl()
452 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; amdgpu_info_ioctl()
467 dev_info.ce_ram_size = adev->gfx.ce_ram_size; amdgpu_info_ioctl()
H A Damdgpu_gds.h55 /* At present, GDS, GWS and OA resources for gfx (graphics)
57 * Such resource is shared between all gfx clients.
H A Damdgpu_acpi.h38 * ATIF provides an entry point for the gfx driver to interact with the sbios.
131 * BYTE - thermal state: target gfx controller
133 * BYTE - forced power state: target gfx controller
152 /* target gfx controller */
235 * WORD - gfx controller id
243 * WORD - number of gfx devices
H A Damdgpu_amdkfd_gfx_v7.c622 adev->gfx.pfp_fw->data; get_fw_version()
627 adev->gfx.me_fw->data; get_fw_version()
632 adev->gfx.ce_fw->data; get_fw_version()
637 adev->gfx.mec_fw->data; get_fw_version()
642 adev->gfx.mec2_fw->data; get_fw_version()
647 adev->gfx.rlc_fw->data; get_fw_version()
H A Damdgpu_amdkfd_gfx_v8.c496 adev->gfx.pfp_fw->data; get_fw_version()
501 adev->gfx.me_fw->data; get_fw_version()
506 adev->gfx.ce_fw->data; get_fw_version()
511 adev->gfx.mec_fw->data; get_fw_version()
516 adev->gfx.mec2_fw->data; get_fw_version()
521 adev->gfx.rlc_fw->data; get_fw_version()
H A Dcik_ih.c219 * - for gfx, hw shader state (0=PS...5=LS, 6=CS)
220 * ME_ID - 0 = gfx, 1 = first 4 CS pipes, 2 = second 4 CS pipes
226 * QUEUE_ID - 0 = gfx, 1 = rlc0, 2 = rlc1
H A Damdgpu_cs.c89 if (ring < adev->gfx.num_gfx_rings) { amdgpu_cs_get_ring()
90 *out_ring = &adev->gfx.gfx_ring[ring]; amdgpu_cs_get_ring()
92 DRM_ERROR("only %d gfx rings are supported now\n", amdgpu_cs_get_ring()
93 adev->gfx.num_gfx_rings); amdgpu_cs_get_ring()
98 if (ring < adev->gfx.num_compute_rings) { amdgpu_cs_get_ring()
99 *out_ring = &adev->gfx.compute_ring[ring]; amdgpu_cs_get_ring()
102 adev->gfx.num_compute_rings); amdgpu_cs_get_ring()
H A Damdgpu_ring.c521 static int amdgpu_gfx_index = offsetof(struct amdgpu_device, gfx.gfx_ring[0]);
522 static int cayman_cp1_index = offsetof(struct amdgpu_device, gfx.compute_ring[0]);
523 static int cayman_cp2_index = offsetof(struct amdgpu_device, gfx.compute_ring[1]);
H A Damdgpu_ucode.h113 struct gfx_firmware_header_v1_0 gfx; member in union:amdgpu_firmware_header
H A Dcik_sdma.c73 * and gfx. There are two DMA engines (SDMA0, SDMA1)
74 * and each one supports 1 ring buffer used for gfx
322 * cik_sdma_gfx_stop - stop the gfx async dma engines
326 * Stop the gfx async dma ring buffers (CIK).
394 * Set up the gfx DMA ring buffers and enable them (CIK).
548 /* start the gfx rings and rlc compute queues */ cik_sdma_start()
H A Dsdma_v2_4.c79 * and gfx. There are two DMA engines (SDMA0, SDMA1)
80 * and each one supports 1 ring buffer used for gfx
363 * sdma_v2_4_gfx_stop - stop the gfx async dma engines
367 * Stop the gfx async dma ring buffers (VI).
437 * Set up the gfx DMA ring buffers and enable them (VI).
600 /* start the gfx rings and rlc compute queues */ sdma_v2_4_start()
H A Dsdma_v3_0.c143 * and gfx. There are two DMA engines (SDMA0, SDMA1)
144 * and each one supports 1 ring buffer used for gfx
474 * sdma_v3_0_gfx_stop - stop the gfx async dma engines
478 * Stop the gfx async dma ring buffers (VI).
573 * Set up the gfx DMA ring buffers and enable them (VI).
750 /* start the gfx rings and rlc compute queues */ sdma_v3_0_start()
H A Damdgpu_acpi.c57 u8 thermal_gfx; /* thermal state: target gfx controller */
59 u8 forced_power_gfx; /* forced power state: target gfx controller */
H A Damdgpu_ib.c303 if (ring == &adev->gfx.gfx_ring[0]) { amdgpu_ib_ring_tests()
H A Dcz_dpm.c1176 if (adev->gfx.gfx_current_status != AMDGPU_GFX_SAFE_MODE) { cz_enable_didt()
1182 adev->gfx.gfx_current_status = AMDGPU_GFX_SAFE_MODE; cz_enable_didt()
1192 if (adev->gfx.gfx_current_status == AMDGPU_GFX_SAFE_MODE) { cz_enable_didt()
1198 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; cz_enable_didt()
H A Damdgpu.h247 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
1202 /* gfx status */
2070 /* gfx */
2071 struct amdgpu_gfx gfx; member in struct:amdgpu_device
H A Dvi.c285 * Returns the reference clock used by the gfx engine
H A Dcik.c834 * Returns the reference clock used by the gfx engine
H A Damdgpu_device.c1420 mutex_init(&adev->gfx.gpu_clock_mutex); amdgpu_device_init()
/linux-4.4.14/arch/ia64/include/asm/sn/
H A Dtioca_provider.h71 u64 ca_pcigart_base; /* gfx GART bus base address */
72 u64 *ca_pcigart; /* gfx GART vm address */
78 u64 ca_gfxap_base; /* gfx aperature bus base address */
79 u64 ca_gfxap_size; /* gfx aperature size (bytes) */
80 u64 ca_gfxgart_base; /* gfx GART bus base address */
81 u64 *ca_gfxgart; /* gfx GART vm address */
H A Dtioca.h526 * | AGP GART mapped (gfx aperature)
554 * 2) CA_AGP_DIRECT_BASE-CA_AGP_MAPPED_BASE+1 (the gfx aperature size)
/linux-4.4.14/include/drm/
H A Di915_component.h34 * struct i915_audio_component_ops - callbacks defined in gfx driver
64 * @dev: the device from gfx driver
/linux-4.4.14/arch/mips/include/asm/sgi/
H A Dioc.h180 #define EXTIO_S0_IRQ_2 0x4000 /* S0: gfx.fifofull */
181 #define EXTIO_S0_IRQ_1 0x2000 /* S0: gfx.int */
184 #define EXTIO_SG_IRQ_2 0x0400 /* SG: gfx.fifofull */
185 #define EXTIO_SG_IRQ_1 0x0200 /* SG: gfx.int */
/linux-4.4.14/arch/arm/mach-omap2/
H A Dcm2xxx.h63 extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core,
H A Dcm2xxx.c373 void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, u32 mdm) omap2xxx_cm_set_mod_dividers() argument
379 omap2_cm_write_mod_reg(gfx, GFX_MOD, CM_CLKSEL); omap2xxx_cm_set_mod_dividers()
H A Domap_hwmod_33xx_43xx_ipblock_data.c166 /* gfx */
169 .name = "gfx",
173 { .name = "gfx", .rst_shift = 0, .st_shift = 0},
177 .name = "gfx",
H A Domap_hwmod_33xx_43xx_interconnect_data.c85 /* gfx -> l3 main */
93 /* l3 main -> gfx */
H A Dopp2xxx.h48 unsigned long cm_clksel_gfx; /* gfx dividers */
/linux-4.4.14/drivers/gpu/drm/radeon/
H A Dradeon_acpi.h38 * ATIF provides an entry point for the gfx driver to interact with the sbios.
131 * BYTE - thermal state: target gfx controller
133 * BYTE - forced power state: target gfx controller
152 /* target gfx controller */
235 * WORD - gfx controller id
243 * WORD - number of gfx devices
H A Dradeon_ucode.h214 struct gfx_firmware_header_v1_0 gfx; member in union:radeon_firmware_header
H A Dcik_sdma.c42 * and gfx. There are two DMA engines (SDMA0, SDMA1)
43 * and each one supports 1 ring buffer used for gfx
244 * cik_sdma_gfx_stop - stop the gfx async dma engines
248 * Stop the gfx async dma ring buffers (CIK).
362 * Set up the gfx DMA ring buffers and enable them (CIK).
539 /* start the gfx rings and rlc compute queues */ cik_sdma_resume()
H A Dcik.c1710 * Returns the reference clock used by the gfx engine
3857 * cik_ring_test - basic gfx ring test
3862 * Allocate a scratch register and write to it using the gfx ring (CIK).
3863 * Provides a basic gfx ring test to verify that the ring is working.
3954 * cik_fence_gfx_ring_emit - emit a fence on the gfx ring
3959 * Emits a fence sequnce number on the gfx ring and flushes
4130 * cik_ring_ib_execute - emit an IB (Indirect Buffer) on the gfx ring
4136 * on the gfx ring. IBs are usually generated by userspace
4139 * on the gfx ring for execution by the GPU.
4182 * cik_ib_test - basic gfx ring IB test
4187 * Allocate an IB and execute it on the gfx ring (CIK).
4188 * Provides a basic gfx ring test to verify that IBs are working.
4249 * On CIK, gfx and compute now have independant command processors.
4252 * Gfx consists of a single ring and can process both gfx jobs and
4253 * compute jobs. The gfx CP consists of three microengines (ME):
4271 * cik_cp_gfx_enable - enable/disable the gfx CP MEs
4276 * Halts or unhalts the gfx MEs.
4292 * cik_cp_gfx_load_microcode - load the gfx CP ME ucode
4296 * Loads the gfx PFP, ME, and CE ucode.
4378 * cik_cp_gfx_start - start the gfx ring
4404 /* init the CE partitions. CE only used for gfx on CIK */ cik_cp_gfx_start()
4439 * cik_cp_gfx_fini - stop the gfx ring
4443 * Stop the gfx ring and tear down the driver ring
4453 * cik_cp_gfx_resume - setup the gfx ring buffer registers
4457 * Program the location and size of the gfx ring buffer
4481 /* ring 0 - compute and gfx */ cik_cp_gfx_resume()
7303 /* gfx ring */ cik_disable_interrupt_state()
7499 DRM_DEBUG("cik_irq_set: sw int gfx\n"); cik_irq_set()
7892 * - for gfx, hw shader state (0=PS...5=LS, 6=CS)
7893 * ME_ID - 0 = gfx, 1 = first 4 CS pipes, 2 = second 4 CS pipes
7899 * QUEUE_ID - 0 = gfx, 1 = rlc0, 2 = rlc1
8335 * reset the CP for gfx cik_irq_process()
8358 * reset the CP for gfx cik_irq_process()
H A Dradeon_acpi.c57 u8 thermal_gfx; /* thermal state: target gfx controller */
59 u8 forced_power_gfx; /* forced power state: target gfx controller */
H A Dsumo_dpm.c1760 /* Some PALM chips don't seem to properly ungate gfx when UVD is in use; sumo_dpm_init()
1761 * for now just disable gfx PG. sumo_dpm_init()
H A Devergreen.c4648 DRM_DEBUG("evergreen_irq_set: sw int gfx\n"); evergreen_irq_set()
4661 DRM_DEBUG("evergreen_irq_set: sw int gfx\n"); evergreen_irq_set()
5660 /* reset the asic, the gfx blocks are often in a bad state evergreen_resume()
5728 /* reset the asic, the gfx blocks are often in a bad state evergreen_init()
H A Dradeon_fence.c1016 case RADEON_RING_TYPE_GFX_INDEX: return "radeon.gfx"; radeon_fence_get_timeline_name()
H A Drv770.c787 * Returns the reference clock used by the gfx engine
H A Dsi.c1305 * Returns the reference clock used by the gfx engine
3663 /* ring 0 - compute and gfx */ si_cp_resume()
5146 /* read a gfx register */ si_enable_gui_idle_interrupt()
6107 DRM_DEBUG("si_irq_set: sw int gfx\n"); si_irq_set()
H A Dcikd.h1081 #define SOFT_RESET_CPF (1 << 17) /* CP fetcher shared by gfx and compute */
H A Dr600_cp.c79 /* MAX values used for gfx init */
H A Dradeon.h130 /* r1xx+ has gfx CP ring */
H A Dr600.c189 * Returns the reference clock used by the gfx engine
/linux-4.4.14/drivers/video/
H A Dvgastate.c29 __u8 *gfx; member in struct:regstate
251 saved->gfx[i] = vga_rgfx(state->vgabase, i); save_vga_mode()
291 vga_wgfx(state->vgabase, i, saved->gfx[i]); restore_vga_mode()
390 saved->gfx = saved->crtc + state->num_crtc; save_vga()
391 saved->seq = saved->gfx + state->num_gfx; save_vga()
/linux-4.4.14/drivers/usb/misc/sisusbvga/
H A Dsisusb.h173 #define SISUSB_EP_GFX_IN 0x0e /* gfx std packet out(0e)/in(8e) */
176 #define SISUSB_EP_GFX_BULK_OUT 0x01 /* gfx mem bulk out/in */
179 #define SISUSB_EP_GFX_LBULK_OUT 0x03 /* gfx large mem bulk out */
H A Dsisusb_con.c536 /* Don't write to screen if in gfx mode */ sisusbcon_switch()
1487 /* Initialize some gfx registers */ sisusb_console_init()
/linux-4.4.14/drivers/clk/sirf/
H A Dclk-atlas6.c65 usp2, vip, gfx, gfx2d, lcd, vpp, mmc01, mmc23, mmc45, usbpll, enumerator in enum:atlas6_clk_index
H A Dclk-prima2.c64 usp2, vip, gfx, mm, lcd, vpp, mmc01, mmc23, mmc45, usbpll, enumerator in enum:prima2_clk_index
H A Dclk-common.c286 * clock domains - cpu, mem, sys/io, dsp, gfx
525 /* dsp, gfx, mm, lcd and vpp domain */
543 .name = "gfx",
/linux-4.4.14/drivers/video/fbdev/
H A Dau1200fb.c212 "0-FS gfx, 1-video, 2-ovly gfx, 3-ovly gfx",
246 "0-FS gfx, 1-video, 2-ovly gfx, 3-ovly gfx",
279 "0-FS gfx, 1-video, 2-ovly gfx, 3-ovly gfx",
H A Dsstfb.c961 * gfx, video, pci fifo should be reset, dram refresh disabled
1166 /* reset gfx + pci fifo */ sst_init()
1206 /* FbiInit0: unreset gfx, unreset fifo */ sst_init()
1249 /* reset video, gfx, fifo, disable dram + remap fbiinit2/3 */ sst_shutdown()
1257 /* set 20Mhz gfx clock */ sst_shutdown()
H A Dhgafb.c73 static int hga_mode = -1; /* 0 = txt, 1 = gfx mode */
H A Dpxa168fb.h388 #define CFG_GRA_VM_ENA(vm) ((vm) << 15) /* gfx */
H A Dpvr2fb.c568 * on the offset from the virtual x start to our real gfx. */ pvr2_init_display()
H A Dsm501fb.c872 control |= SM501_DC_PANEL_CONTROL_EN; /* enable PANEL gfx plane */ sm501fb_set_par_pnl()
/linux-4.4.14/drivers/video/fbdev/omap2/dss/
H A Doverlay.c72 ovl->name = "gfx"; dss_init_overlays()
H A Dmanager-sysfs.c164 "gfx-destination",
/linux-4.4.14/drivers/gpu/drm/omapdrm/
H A Domap_plane.c327 [OMAP_DSS_GFX] = "gfx",
/linux-4.4.14/drivers/char/agp/
H A Dsgi-agp.c95 * Determine gfx aperature size. This has already been determined by the
H A Dintel-agp.c744 /* In case that multiple models of gfx chip may agp_intel_probe()
H A Dintel-gtt.c1396 "set gfx device dma mask %d-bit failed!\n", mask); intel_gmch_probe()
/linux-4.4.14/include/uapi/video/
H A Dsisfb.h140 #define SISFB_CMD_ERR_EARLY 0x80000002 /* request before sisfb took over gfx system */
/linux-4.4.14/arch/mips/sgi-ip22/
H A Dip22-mc.c179 tmp = sgimc->giopar & SGIMC_GIOPAR_GFX64; /* keep gfx 64bit settings */ sgimc_init()
/linux-4.4.14/drivers/gpu/drm/i915/
H A Dintel_guc_loader.c49 * GuC does not allow any gfx GGTT address that falls into range [0, WOPCM_TOP),
51 * 512K. In order to exclude 0-512K address space from GGTT, all gfx objects
H A Di915_debugfs.c1759 unsigned long temp, chipset, gfx; i915_emon_status() local
1771 gfx = i915_gfx_val(dev_priv); i915_emon_status()
1776 seq_printf(m, "GFX power: %ld\n", gfx); i915_emon_status()
1777 seq_printf(m, "Total power: %ld\n", chipset + gfx); i915_emon_status()
H A Di915_gpu_error.c1331 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); i915_capture_error_state()
H A Di915_drv.c1428 /* For safety always re-enable waking and disable gfx clock forcing */ vlv_suspend_complete()
H A Dintel_hdmi.c483 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); intel_hdmi_set_spd_infoframe()
H A Di915_gem_gtt.c3128 DRM_INFO("VT-d active for gfx access\n"); i915_gem_gtt_init()
/linux-4.4.14/drivers/gpu/drm/gma500/
H A Dpsb_reg.h564 #define PSB_PWRGT_DISPLAY_MASK 0xc /*on a different BA than video/gfx*/
H A Dcdv_device.c250 * Fixes were done to Win 7 gfx driver to disable a feature called cdv_errata()
H A Dmdfld_dsi_output.c467 ret = gpio_request(gpio, "gfx"); mdfld_dsi_panel_reset()
/linux-4.4.14/arch/mips/include/asm/sn/
H A Dklconfig.h332 #define KLCLASS_PSEUDO_GFX 0x60 /* HDTV type cards that use a gfx
333 * hw ifc to xtalk and are not gfx
876 #define VDS_NOGFX 0x8000 /* Don't enable gfx and autoboot */
/linux-4.4.14/drivers/clk/berlin/
H A Dbg2.c222 .name = "gfx",
/linux-4.4.14/include/video/
H A Dvga.h190 __u32 num_gfx; /* number of gfx registers, 0 for default */
/linux-4.4.14/arch/mips/include/asm/sn/sn0/
H A Dhubio.h116 #define IIO_IGFX_0 0x400140 /* gfx node/widget register 0 */
117 #define IIO_IGFX_1 0x400148 /* gfx node/widget register 1 */
/linux-4.4.14/arch/x86/kernel/
H A Dearly-quirks.c220 * for gfx driver use. This memory is not marked in the E820 as reserved
H A Dsetup.c716 printk(KERN_DEBUG "reserving inaccessible SNB gfx pages\n"); trim_snb_memory()
/linux-4.4.14/drivers/platform/x86/
H A Dintel_ips.c570 * ips_enable_gpu_turbo - notify the gfx driver turbo is available
584 * ips_disable_gpu_turbo - notify the gfx driver to disable turbo mode
/linux-4.4.14/drivers/iommu/
H A Dintel-iommu.c3211 * identity mappings for rmrr, gfx, and isa and may fall back to static
3910 /* This IOMMU has *only* gfx devices. Either bypass it or for_each_active_drhd_unit()
5117 /* G4x/GM45 integrated gfx dmar support is totally busted. */ quirk_iommu_g4x_gfx()
5169 /* we have to ensure the gfx device is idle before we flush */ quirk_calpella_no_shadow_gtt()
/linux-4.4.14/drivers/gpu/drm/
H A Ddrm_mm.c75 * something better would be fairly complex and since gfx thrashing is a fairly
/linux-4.4.14/arch/parisc/kernel/
H A Ddrivers.c509 /* This is awkward. The STI spec says that gfx devices may occupy alloc_pa_dev()
/linux-4.4.14/drivers/video/fbdev/omap/
H A Domapfb_main.c241 * gfx DMA operations are ended, before we return. */ omapfb_release()
/linux-4.4.14/sound/pci/hda/
H A Dpatch_hdmi.c1814 * but this can happen before gfx is ready and such selection generic_hdmi_playback_pcm_prepare()

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