Searched refs:g4 (Results 1 - 63 of 63) sorted by relevance

/linux-4.4.14/arch/sparc/kernel/
H A Dmisctrap.S29 /* Setup %g4/%g5 now as they are used in the
33 mov DMMU_SFAR, %g4
34 ldxa [%g4] ASI_DMMU, %g4
54 mov TLB_SFSR, %g4
55 ldxa [%g4] ASI_DMMU, %g5
56 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
58 mov DMMU_SFAR, %g4
59 ldxa [%g4] ASI_DMMU, %g4
72 mov TLB_SFSR, %g4
73 ldxa [%g4] ASI_DMMU, %g5
74 stxa %g0, [%g4] ASI_DMMU ! Clear FaultValid bit
76 mov DMMU_SFAR, %g4
77 ldxa [%g4] ASI_DMMU, %g4
H A Dsun4v_ivec.S14 /* Head offset in %g2, tail offset in %g4.
19 mov INTRQ_CPU_MONDO_TAIL, %g4
20 ldxa [%g4] ASI_QUEUE, %g4
21 cmp %g2, %g4
25 /* Get &trap_block[smp_processor_id()] into %g4. */
26 ldxa [%g0] ASI_SCRATCHPAD, %g4
27 sub %g4, TRAP_PER_CPU_FAULT_INFO, %g4
30 ldx [%g4 + TRAP_PER_CPU_CPU_MONDO_PA], %g7
50 lduw [%g4 + TRAP_PER_CPU_CPU_MONDO_QMASK], %g4
51 and %g2, %g4, %g2
53 mov INTRQ_CPU_MONDO_HEAD, %g4
54 stxa %g2, [%g4] ASI_QUEUE
64 /* Head offset in %g2, tail offset in %g4. */
67 mov INTRQ_DEVICE_MONDO_TAIL, %g4
68 ldxa [%g4] ASI_QUEUE, %g4
69 cmp %g2, %g4
73 /* Get &trap_block[smp_processor_id()] into %g4. */
74 ldxa [%g0] ASI_SCRATCHPAD, %g4
75 sub %g4, TRAP_PER_CPU_FAULT_INFO, %g4
78 ldx [%g4 + TRAP_PER_CPU_DEV_MONDO_PA], %g5
92 lduw [%g4 + TRAP_PER_CPU_DEV_MONDO_QMASK], %g4
93 and %g2, %g4, %g2
95 mov INTRQ_DEVICE_MONDO_HEAD, %g4
96 stxa %g2, [%g4] ASI_QUEUE
99 TRAP_LOAD_IRQ_WORK_PA(%g1, %g4)
103 xnor %g3, %g0, %g4
105 /* Get __pa(&ivector_table[IVEC]) into %g4. */
106 sethi %hi(ivector_table_pa), %g4
107 ldx [%g4 + %lo(ivector_table_pa)], %g4
109 add %g4, %g3, %g4
112 stxa %g2, [%g4] ASI_PHYS_USE_EC
113 stx %g4, [%g1]
122 /* Head offset in %g2, tail offset in %g4. */
125 mov INTRQ_RESUM_MONDO_TAIL, %g4
126 ldxa [%g4] ASI_QUEUE, %g4
127 cmp %g2, %g4
146 lduw [%g3 + TRAP_PER_CPU_RESUM_QMASK], %g4
178 and %g2, %g4, %g2
180 mov INTRQ_RESUM_MONDO_HEAD, %g4
181 stxa %g2, [%g4] ASI_QUEUE
185 * C code. The etrap handling will leave %g4 in %l4 for us
190 mov %g1, %g4
215 stxa %g4, [%g2] ASI_QUEUE
233 /* Head offset in %g2, tail offset in %g4. */
236 mov INTRQ_NONRESUM_MONDO_TAIL, %g4
237 ldxa [%g4] ASI_QUEUE, %g4
238 cmp %g2, %g4
257 lduw [%g3 + TRAP_PER_CPU_NONRESUM_QMASK], %g4
289 and %g2, %g4, %g2
291 mov INTRQ_NONRESUM_MONDO_HEAD, %g4
292 stxa %g2, [%g4] ASI_QUEUE
296 * C code. The etrap handling will leave %g4 in %l4 for us
301 mov %g1, %g4
326 stxa %g4, [%g2] ASI_QUEUE
H A Dktlb.S20 mov TLB_TAG_ACCESS, %g4
21 ldxa [%g4] ASI_IMMU, %g4
24 * address already loaded into %g4
30 cmp %g4, %g5
34 KERN_TSB_LOOKUP_TL1(%g4, %g6, %g5, %g1, %g2, %g3, kvmap_itlb_load)
38 cmp %g4, %g5
42 cmp %g4, %g5
47 KERN_PGTABLE_WALK(%g4, %g5, %g2, kvmap_itlb_longpath)
69 * %g4: vaddr
91 mov FAULT_CODE_ITLB, %g4
94 OBP_TRANS_LOOKUP(%g4, %g5, %g2, %g3, kvmap_itlb_longpath)
104 OBP_TRANS_LOOKUP(%g4, %g5, %g2, %g3, kvmap_dtlb_longpath)
117 xor %g2, %g4, %g5
128 mov TLB_TAG_ACCESS, %g4
129 ldxa [%g4] ASI_DMMU, %g4
132 * address already loaded into %g4
135 brgez,pn %g4, kvmap_dtlb_nonlinear
142 KERN_TSB_LOOKUP_TL1(%g4, %g6, %g5, %g1, %g2, %g3, kvmap_dtlb_load)
155 KERN_PGTABLE_WALK(%g4, %g5, %g2, kvmap_dtlb_longpath)
177 * %g4: vaddr
189 KERN_PGTABLE_WALK(%g4, %g5, %g2, kvmap_dtlb_longpath)
196 cmp %g4, %g5
204 cmp %g4,%g5
209 KERN_TSB_LOOKUP_TL1(%g4, %g6, %g5, %g1, %g2, %g3, kvmap_dtlb_load)
213 cmp %g4, %g5
217 cmp %g4, %g5
223 cmp %g4, %g5
227 cmp %g4, %g5
246 661: mov TLB_TAG_ACCESS, %g4
247 ldxa [%g4] ASI_DMMU, %g5
255 mov FAULT_CODE_DTLB, %g4
H A Dwindows.c26 "ld [%%g6 + %2], %%g4\n\t" flush_user_windows()
27 "orcc %%g0, %%g4, %%g0\n\t" flush_user_windows()
38 : "g4", "cc"); flush_user_windows()
88 "ldd [%1 + 0x8], %%g4\n\t"
90 "std %%g4, [%0 + 0x8]\n\t"
92 "ldd [%1 + 0x18], %%g4\n\t"
94 "std %%g4, [%0 + 0x18]\n\t"
96 "ldd [%1 + 0x28], %%g4\n\t"
98 "std %%g4, [%0 + 0x28]\n\t"
100 "ldd [%1 + 0x38], %%g4\n\t"
102 "std %%g4, [%0 + 0x38]\n\t" : :
104 "g2", "g3", "g4", "g5");
H A Dspiterrs.S17 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
19 /* __spitfire_cee_trap branches here with AFSR in %g4 and
29 or %g4, %g3, %g4
36 or %g4, %g3, %g4
54 or %g4, %g7, %g4
65 or %g4, %g7, %g4
76 stxa %g4, [%g0] ASI_AFSR
133 ldxa [%g0] ASI_AFSR, %g4 ! Get AFSR
136 andcc %g4, %g3, %g0 ! Check for UE
150 /* Preserve AFSR in %g4, indicate UDB state to capture in %g1 */
157 rdpr %pstate, %g4
158 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
161 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
185 rdpr %pstate, %g4
186 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
189 ldxa [%g3] ASI_DMMU, %g4 ! Get SFSR
205 rdpr %pstate, %g4
206 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
208 ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
224 rdpr %pstate, %g4
225 wrpr %g4, PSTATE_MG|PSTATE_AG, %pstate
227 ldxa [%g3] ASI_IMMU, %g4 ! Get SFSR
H A Dsun4v_tlb_miss.S54 LOAD_ITLB_INFO(%g2, %g4, %g5)
55 COMPUTE_TAG_TARGET(%g6, %g4, %g5, kvmap_itlb_4v)
56 COMPUTE_TSB_PTR(%g1, %g4, PAGE_SHIFT, %g3, %g7)
71 * %g4: vaddr
79 mov %g4, %o0 ! vaddr
100 LOAD_DTLB_INFO(%g2, %g4, %g5)
101 COMPUTE_TAG_TARGET(%g6, %g4, %g5, kvmap_dtlb_4v)
102 COMPUTE_TSB_PTR(%g1, %g4, PAGE_SHIFT, %g3, %g7)
114 * %g4: vaddr
122 mov %g4, %o0 ! vaddr
145 mov FAULT_CODE_DTLB | FAULT_CODE_WRITE, %g4
150 * %g4: vaddr
162 * %g4: vaddr
175 COMPUTE_TSB_PTR(%g1, %g4, PAGE_SHIFT, %g5, %g7)
185 COMPUTE_TSB_PTR(%g5, %g4, REAL_HPAGE_SHIFT, %g2, %g7)
204 stx %g4, [%g1 + %lo(sun4v_err_itlb_vaddr)]
215 rdpr %tl, %g4
231 stx %g4, [%g1 + %lo(sun4v_err_dtlb_vaddr)]
242 rdpr %tl, %g4
252 or %g0, %g4, %g5
254 or %g1, %g0, %g4
262 ldx [%g2 + HV_FAULT_I_ADDR_OFFSET], %g4
278 ldx [%g2 + HV_FAULT_I_ADDR_OFFSET], %g4
294 ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
310 ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
334 ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g4
336 or %g4, %g3, %g4
343 ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
368 ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
384 ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
H A Durtt_fill.S34 mov %g4, %l4
39 or %g4, FAULT_CODE_WINFIXUP, %g4
40 stb %g4, [%g6 + TI_FAULT_CODE]
55 ldx [%g6 + TI_TASK], %g4
H A Dtrampoline_32.S60 srl %g3, 10, %g4
61 and %g4, 0xc, %g4
62 ld [%g5 + %g4], %g6
122 srl %g3, 1, %g4
123 ld [%g5 + %g4], %g6
177 srl %g3, 28, %g4
178 sll %g4, 2, %g4
179 ld [%g5 + %g4], %g6
H A Dtsb.S23 * %g4: available temporary
31 mov TLB_TAG_ACCESS, %g4
33 ldxa [%g4] ASI_DMMU, %g4
36 mov TLB_TAG_ACCESS, %g4
38 ldxa [%g4] ASI_IMMU, %g4
43 * %g4 -- missing virtual address
78 srlx %g4, REAL_HPAGE_SHIFT, %g6
93 srlx %g4, 22, %g6
103 * %g4 -- missing virtual address
111 USER_PGTABLE_WALK_TL1(%g4, %g7, %g5, %g2, tsb_do_fault)
168 mov %g3, %g4
210 * %g4: vaddr
222 661: sethi %hi(_PAGE_EXEC_4U), %g4
223 andcc %g5, %g4, %g0
246 * %g4: vaddr
269 ldxa [%g0] ASI_SCRATCHPAD, %g4
279 661: mov TLB_TAG_ACCESS, %g4
280 ldxa [%g4] ASI_DMMU, %g5
283 ldx [%g4 + HV_FAULT_D_ADDR_OFFSET], %g5
288 mov FAULT_CODE_DTLB, %g4
295 mov FAULT_CODE_ITLB, %g4
299 /* fault code in %g4, fault address in %g5, etrap will
H A Divec.S17 sethi %hi(KERNBASE), %g4
18 cmp %g3, %g4
H A Dutrap.S3 utrap_trap: /* %g3=handler,%g4=level */
H A Dhead_32.S107 mov %o7, %g4 ! Save %o7
119 mov %g4, %o7 /* Previous %o7. */
153 ldd [%g3], %g4
154 std %g4, [%g1]
155 ldd [%g3+8], %g4
156 std %g4, [%g1+8]
164 ldd [%g2], %g4
165 std %g4, [%g3]
166 ldd [%g2 + 0x8], %g4
167 std %g4, [%g3 + 0x8] ! Copy proms handler
249 set AC_M_CTPR, %g4
250 lda [%g4] ASI_M_MMUREGS, %g4
251 sll %g4, 0x4, %g4 ! We use this below
252 ! DO NOT TOUCH %g4
265 lda [%g4] ASI_M_BYPASS, %o1 ! This is a level 1 ptr
449 set patch_handler_irq, %g4
452 sub %g5, %g4, %g5
455 st %g5, [%g4]
462 srl %g3, 3, %g4
463 sta %g4, [%g0] ASI_M_VIKING_TMP1
465 stb %g4, [%g5 + %lo(boot_cpu_id)]
587 ld [%g5], %g4; \
588 st %g4, [%g2];
620 set 0x01000000, %g4
622 st %g4, [%g5 + 0x18]
623 st %g4, [%g5 + 0x1c]
625 st %g4, [%g5 + 0x18]
626 st %g4, [%g5 + 0x1c]
628 st %g4, [%g5 + 0x18]
629 st %g4, [%g5 + 0x1c]
631 st %g4, [%g5 + 0x18]
632 st %g4, [%g5 + 0x1c]
634 st %g4, [%g5 + 0x18]
635 st %g4, [%g5 + 0x1c]
637 st %g4, [%g5 + 0x18]
638 st %g4, [%g5 + 0x1c]
641 sethi %hi(nwindows), %g4
642 st %g3, [%g4 + %lo(nwindows)] ! store final value
644 sethi %hi(nwindowsm1), %g4
645 st %g3, [%g4 + %lo(nwindowsm1)]
H A Dwinfixup.S27 or %g4, FAULT_CODE_WINFIXUP, %g4
28 stb %g4, [%g6 + TI_FAULT_CODE]
96 1: mov FAULT_CODE_WRITE | FAULT_CODE_DTLB | FAULT_CODE_WINFIXUP, %g4
97 stb %g4, [%g6 + TI_FAULT_CODE]
H A Dasm-offsets.c38 OFFSET(SC_REG_G4, saved_context, g4); sparc64_foo()
H A Dcherrs.S185 rdpr %tstate, %g4 ! Read TSTATE for this level
186 andcc %g4, %g3, %g0 ! Interrupt globals in use?
236 rdpr %tstate, %g4 ! Read TSTATE for this level
237 andcc %g4, %g3, %g0 ! Interrupt globals in use?
297 * %g4: AFSR
307 or %g4, %g2, %g4
336 stx %g4, [%g1 + 0x0]
479 ldxa [%g0] ASI_AFSR, %g4
481 stxa %g4, [%g0] ASI_AFSR
515 ldxa [%g0] ASI_AFSR, %g4
517 stxa %g4, [%g0] ASI_AFSR
551 ldxa [%g0] ASI_AFSR, %g4
553 stxa %g4, [%g0] ASI_AFSR
H A Detrap_64.S25 * %g4 and %g5 will be preserved %l4 and %l5 respectively.
114 2: mov %g4, %l4
130 stx %g4, [%sp + PTREGS_OFF + PT_V9_G4]
148 LOAD_PER_CPU_BASE(%g5, %g6, %g4, %g3, %l1)
149 ldx [%g6 + TI_TASK], %g4
H A Dhead_64.S324 ldub [%g1], %g4
325 cmp %g2, %g4
387 ldub [%g1], %g4
388 cmp %g2, %g4
403 ldub [%g1], %g4
404 cmp %g2, %g4
423 mov SUN4V_CHIP_NIAGARA3, %g4
426 mov SUN4V_CHIP_NIAGARA4, %g4
429 mov SUN4V_CHIP_NIAGARA5, %g4
432 mov SUN4V_CHIP_SPARC_M6, %g4
435 mov SUN4V_CHIP_SPARC_M7, %g4
444 mov SUN4V_CHIP_NIAGARA1, %g4
447 mov SUN4V_CHIP_NIAGARA2, %g4
457 ldub [%g1], %g4
458 cmp %g2, %g4
465 mov SUN4V_CHIP_SPARC64X, %g4
468 mov SUN4V_CHIP_UNKNOWN, %g4
471 stw %g4, [%g2]
668 ldx [%g6 + TI_TASK], %g4
H A Dhvtramp.S106 ldx [%g6 + TI_TASK], %g4
H A Dtrampoline_64.S277 * %g4 (current task pointer), or %g5 (base of current cpu's
290 set 0xdeadbeef, %g4
394 ldx [%g6 + TI_TASK], %g4
H A Dfpu_traps.S5 sethi %hi(TSTATE_PEF), %g4
7 andcc %g5, %g4, %g0
189 or %g3, %g4, %g3 ! anal...
H A Dentry.S883 rd %psr, %g4
889 std %g4, [%o4 + AOFF_task_thread + AOFF_thread_fork_kpsr]
902 rd %psr, %g4
913 std %g4, [%o4 + AOFF_task_thread + AOFF_thread_fork_kpsr]
925 rd %psr, %g4
929 std %g4, [%o4 + AOFF_task_thread + AOFF_thread_fork_kpsr]
1087 set 0x2000, %g4
1088 andcc %g1, %g4, %g0
1098 andcc %g3, %g4, %g0
H A Dwuf.S164 mov %fp, %g4 /* Save bogus frame pointer. */
190 mov %g4, %o0
H A Drtrap_32.S22 #define glob_tmp g4
H A Drtrap_64.S159 ldx [%sp + PTREGS_OFF + PT_V9_G4], %g4
H A Dsignal_32.c471 * In particular %g2, %g3, %g4, and %g5 are all assumed to be do_signal()
H A Dprocess_64.c177 printk("g4: %016lx g5: %016lx g6: %016lx g7: %016lx\n", show_regs()
H A Dsignal_64.c490 * In particular %g2, %g3, %g4, and %g5 are all assumed to be do_signal()
/linux-4.4.14/arch/sparc/include/asm/
H A Dxor_32.h31 "ldd [%0 + 0x08], %%g4\n\t" sparc_2()
40 "xor %%g4, %%l0, %%g4\n\t" sparc_2()
47 "std %%g4, [%0 + 0x08]\n\t" sparc_2()
52 : "g2", "g3", "g4", "g5", sparc_2()
69 "ldd [%0 + 0x08], %%g4\n\t" sparc_3()
79 "xor %%g4, %%l0, %%g4\n\t" sparc_3()
90 "xor %%g4, %%l0, %%g4\n\t" sparc_3()
97 "std %%g4, [%0 + 0x08]\n\t" sparc_3()
102 : "g2", "g3", "g4", "g5", sparc_3()
120 "ldd [%0 + 0x08], %%g4\n\t" sparc_4()
130 "xor %%g4, %%l0, %%g4\n\t" sparc_4()
142 "xor %%g4, %%l0, %%g4\n\t" sparc_4()
153 "xor %%g4, %%l0, %%g4\n\t" sparc_4()
160 "std %%g4, [%0 + 0x08]\n\t" sparc_4()
165 : "g2", "g3", "g4", "g5", sparc_4()
184 "ldd [%0 + 0x08], %%g4\n\t" sparc_5()
194 "xor %%g4, %%l0, %%g4\n\t" sparc_5()
206 "xor %%g4, %%l0, %%g4\n\t" sparc_5()
218 "xor %%g4, %%l0, %%g4\n\t" sparc_5()
229 "xor %%g4, %%l0, %%g4\n\t" sparc_5()
236 "std %%g4, [%0 + 0x08]\n\t" sparc_5()
241 : "g2", "g3", "g4", "g5", sparc_5()
H A Dchecksum_32.h56 "g2", "g3", "g4", "g5", "g7", csum_partial_copy_nocheck()
80 : "o2", "o3", "o4", "o5", "o7", "g2", "g3", "g4", "g5", csum_partial_copy_from_user()
109 "g2", "g3", "g4", "g5", csum_partial_copy_to_user()
129 __asm__ __volatile__("sub\t%2, 4, %%g4\n\t" ip_fast_csum()
142 "subcc\t%%g4, 1, %%g4\n\t" ip_fast_csum()
153 : "g2", "g3", "g4", "cc", "memory"); ip_fast_csum()
208 "addcc %3, %4, %%g4\n\t" csum_ipv6_magic()
209 "addxcc %5, %%g4, %%g4\n\t" csum_ipv6_magic()
212 "addxcc %%g2, %%g4, %%g4\n\t" csum_ipv6_magic()
214 "addxcc %%g3, %%g4, %%g4\n\t" csum_ipv6_magic()
216 "addxcc %%g2, %%g4, %%g4\n\t" csum_ipv6_magic()
218 "addxcc %%g3, %%g4, %%g4\n\t" csum_ipv6_magic()
220 "addxcc %%g2, %%g4, %%g4\n\t" csum_ipv6_magic()
222 "addxcc %%g3, %%g4, %%g4\n\t" csum_ipv6_magic()
224 "addxcc %%g2, %%g4, %%g4\n\t" csum_ipv6_magic()
225 "addxcc %%g3, %%g4, %0\n\t" csum_ipv6_magic()
230 : "g2", "g3", "g4", "cc"); csum_ipv6_magic()
H A Dcurrent.h17 register struct task_struct *current asm("g4");
21 /* We might want to consider using %g4 like sparc64 to shave a few cycles.
H A Dhibernate.h18 unsigned long g4; member in struct:saved_context
H A Dswitch_to_32.h65 "rd %%psr, %%g4\n\t" \
68 "wr %%g4, 0x20, %%psr\n\t" \
70 "std %%g4, [%%g6 + %3]\n\t" \
71 "ldd [%2 + %3], %%g4\n\t" \
76 "wr %%g4, 0x20, %%psr\n\t" \
84 "wr %%g4, 0x0, %%psr\n\t" \
96 : "g1", "g2", "g3", "g4", "g5", "g7", \
H A Dspinlock_32.h85 "mov %%o7, %%g4\n\t" __arch_read_lock()
90 : "g2", "g4", "memory", "cc"); __arch_read_lock()
105 "mov %%o7, %%g4\n\t" __arch_read_unlock()
110 : "g2", "g4", "memory", "cc"); __arch_read_unlock()
125 "mov %%o7, %%g4\n\t" arch_write_lock()
130 : "g2", "g4", "memory", "cc"); arch_write_lock()
169 "mov %%o7, %%g4\n\t" __arch_read_trylock()
174 : "g2", "g4", "memory", "cc"); __arch_read_trylock()
H A Dswitch_to_64.h29 "mov %%g4, %%g7\n\t" \
47 "ldx [%%g6 + %9], %%g4\n\t" \
H A Dwinmacro.h46 ldd [%base_reg + STACKFRAME_SZ + PT_G4], %g4; \
73 std %g4, [%base_reg + STACKFRAME_SZ + PT_G4]; \
H A Dttable.h106 mov lvl, %g4; \
197 ldx [%g2 + HV_FAULT_I_ADDR_OFFSET], %g4; \
199 srlx %g4, 22, %g6; \
207 ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4; \
209 srlx %g4, 22, %g6; \
223 * Further note that we cannot use the g2, g4, g5, and g7 alternate
226 * g4/g5 are the globals which are preserved by etrap processing
H A Dtsb.h17 * ldda [%g1] ASI_NUCLEUS_QUAD_LDD, %g4
18 * cmp %g4, %g6
H A Duaccess_32.h359 "g1", "g2", "g3", "g4", "g5", "g7", "cc"); __clear_user()
/linux-4.4.14/arch/sparc/prom/
H A Dcif.S18 mov %g4, %l0
23 mov %l0, %g4
35 LOAD_PER_CPU_BASE(%g5, %g6, %g4, %g3, %o0)
36 ldx [%g6 + TI_TASK], %g4
/linux-4.4.14/arch/sparc/lib/
H A Dmemcpy.S236 MOVE_BIGCHUNK(o1, o0, 0x00, o2, o3, o4, o5, g2, g3, g4, g5)
237 MOVE_BIGCHUNK(o1, o0, 0x20, o2, o3, o4, o5, g2, g3, g4, g5)
238 MOVE_BIGCHUNK(o1, o0, 0x40, o2, o3, o4, o5, g2, g3, g4, g5)
239 MOVE_BIGCHUNK(o1, o0, 0x60, o2, o3, o4, o5, g2, g3, g4, g5)
246 andcc %g1, 0x70, %g4
251 srl %g4, 1, %o4
252 add %g4, %o4, %o4
253 add %o1, %g4, %o1
256 add %o0, %g4, %o0
260 MOVE_LASTCHUNK(o1, o0, 0x60, g2, g3, g4, g5)
261 MOVE_LASTCHUNK(o1, o0, 0x50, g2, g3, g4, g5)
262 MOVE_LASTCHUNK(o1, o0, 0x40, g2, g3, g4, g5)
263 MOVE_LASTCHUNK(o1, o0, 0x30, g2, g3, g4, g5)
264 MOVE_LASTCHUNK(o1, o0, 0x20, g2, g3, g4, g5)
265 MOVE_LASTCHUNK(o1, o0, 0x10, g2, g3, g4, g5)
266 MOVE_LASTCHUNK(o1, o0, 0x00, g2, g3, g4, g5)
306 MOVE_BIGALIGNCHUNK(o1, o0, 0x00, o2, o3, o4, o5, g2, g3, g4, g5)
307 MOVE_BIGALIGNCHUNK(o1, o0, 0x20, o2, o3, o4, o5, g2, g3, g4, g5)
308 MOVE_BIGALIGNCHUNK(o1, o0, 0x40, o2, o3, o4, o5, g2, g3, g4, g5)
309 MOVE_BIGALIGNCHUNK(o1, o0, 0x60, o2, o3, o4, o5, g2, g3, g4, g5)
316 andcc %g1, 0x70, %g4
321 add %o1, %g4, %o1
322 sub %o5, %g4, %o5
324 add %o0, %g4, %o0
328 MOVE_LASTALIGNCHUNK(o1, o0, 0x60, g2, g3, g4, g5)
329 MOVE_LASTALIGNCHUNK(o1, o0, 0x50, g2, g3, g4, g5)
330 MOVE_LASTALIGNCHUNK(o1, o0, 0x40, g2, g3, g4, g5)
331 MOVE_LASTALIGNCHUNK(o1, o0, 0x30, g2, g3, g4, g5)
332 MOVE_LASTALIGNCHUNK(o1, o0, 0x20, g2, g3, g4, g5)
333 MOVE_LASTALIGNCHUNK(o1, o0, 0x10, g2, g3, g4, g5)
334 MOVE_LASTALIGNCHUNK(o1, o0, 0x00, g2, g3, g4, g5)
401 sll %g2, 3, %g4
404 sub %g2, %g4, %l0
442 sll %i5, %g4, %g2
448 sll %g1, %g4, %g2
454 sll %i3, %g4, %g2
460 sll %i4, %g4, %g2
470 sll %i5, %g4, %g2
H A Dlocks.S36 mov %g4, %o7
59 mov %g4, %o7
70 mov %g4, %o7
81 mov %g4, %o7
92 mov %g4, %o7
H A Dchecksum_32.S114 5: CSUM_BIGCHUNK(%o0, 0x00, %o2, %o4, %o5, %g2, %g3, %g4, %g5)
115 CSUM_BIGCHUNK(%o0, 0x20, %o2, %o4, %o5, %g2, %g3, %g4, %g5)
116 CSUM_BIGCHUNK(%o0, 0x40, %o2, %o4, %o5, %g2, %g3, %g4, %g5)
117 CSUM_BIGCHUNK(%o0, 0x60, %o2, %o4, %o5, %g2, %g3, %g4, %g5)
130 cptbl: CSUM_LASTCHUNK(%o0, 0x68, %o2, %g2, %g3, %g4, %g5)
131 CSUM_LASTCHUNK(%o0, 0x58, %o2, %g2, %g3, %g4, %g5)
132 CSUM_LASTCHUNK(%o0, 0x48, %o2, %g2, %g3, %g4, %g5)
133 CSUM_LASTCHUNK(%o0, 0x38, %o2, %g2, %g3, %g4, %g5)
134 CSUM_LASTCHUNK(%o0, 0x28, %o2, %g2, %g3, %g4, %g5)
135 CSUM_LASTCHUNK(%o0, 0x18, %o2, %g2, %g3, %g4, %g5)
136 CSUM_LASTCHUNK(%o0, 0x08, %o2, %g2, %g3, %g4, %g5)
306 EX(lduh [%o0 + 0x00], %g4, add %g1, 0)
308 EX2(sth %g4, [%o1 + 0x00])
310 sll %g4, 16, %g4
311 addcc %g4, %g7, %g7
314 addx %g0, %g3, %g4
316 sll %g4, 16, %g3
322 EX(ld [%o0 + 0x00], %g4, add %g1, 0)
324 EX2(st %g4, [%o1 + 0x00])
326 addcc %g4, %g7, %g7
349 5: CSUMCOPY_BIGCHUNK(%o0,%o1,%g7,0x00,%o4,%o5,%g2,%g3,%g4,%g5,%o2,%o3)
350 CSUMCOPY_BIGCHUNK(%o0,%o1,%g7,0x20,%o4,%o5,%g2,%g3,%g4,%g5,%o2,%o3)
351 CSUMCOPY_BIGCHUNK(%o0,%o1,%g7,0x40,%o4,%o5,%g2,%g3,%g4,%g5,%o2,%o3)
352 CSUMCOPY_BIGCHUNK(%o0,%o1,%g7,0x60,%o4,%o5,%g2,%g3,%g4,%g5,%o2,%o3)
371 cctbl: CSUMCOPY_LASTCHUNK(%o0,%o1,%g7,0x68,%g2,%g3,%g4,%g5)
372 CSUMCOPY_LASTCHUNK(%o0,%o1,%g7,0x58,%g2,%g3,%g4,%g5)
373 CSUMCOPY_LASTCHUNK(%o0,%o1,%g7,0x48,%g2,%g3,%g4,%g5)
374 CSUMCOPY_LASTCHUNK(%o0,%o1,%g7,0x38,%g2,%g3,%g4,%g5)
375 CSUMCOPY_LASTCHUNK(%o0,%o1,%g7,0x28,%g2,%g3,%g4,%g5)
376 CSUMCOPY_LASTCHUNK(%o0,%o1,%g7,0x18,%g2,%g3,%g4,%g5)
377 CSUMCOPY_LASTCHUNK(%o0,%o1,%g7,0x08,%g2,%g3,%g4,%g5)
385 ccdbl: CSUMCOPY_BIGCHUNK_ALIGNED(%o0,%o1,%g7,0x00,%o4,%o5,%g2,%g3,%g4,%g5,%o2,%o3)
386 CSUMCOPY_BIGCHUNK_ALIGNED(%o0,%o1,%g7,0x20,%o4,%o5,%g2,%g3,%g4,%g5,%o2,%o3)
387 CSUMCOPY_BIGCHUNK_ALIGNED(%o0,%o1,%g7,0x40,%o4,%o5,%g2,%g3,%g4,%g5,%o2,%o3)
388 CSUMCOPY_BIGCHUNK_ALIGNED(%o0,%o1,%g7,0x60,%o4,%o5,%g2,%g3,%g4,%g5,%o2,%o3)
404 srl %g1, 1, %g4
409 srl %g1, 1, %g4
411 1: cmp %g4, 0
416 srl %g4, 1, %g4
420 sub %g4, 1, %g4
425 srl %g4, 1, %g4
427 1: cmp %g4, 0
442 subcc %g4, 1, %g4 ! tricks
540 sll %g4, 2, %g4
541 add %g1, %g4, %o3
H A Dblockops.S74 MIRROR_BLOCK(%o0, %o1, 0x00, %o2, %o3, %o4, %o5, %g2, %g3, %g4, %g5)
75 MIRROR_BLOCK(%o0, %o1, 0x20, %o2, %o3, %o4, %o5, %g2, %g3, %g4, %g5)
76 MIRROR_BLOCK(%o0, %o1, 0x40, %o2, %o3, %o4, %o5, %g2, %g3, %g4, %g5)
77 MIRROR_BLOCK(%o0, %o1, 0x60, %o2, %o3, %o4, %o5, %g2, %g3, %g4, %g5)
78 MIRROR_BLOCK(%o0, %o1, 0x80, %o2, %o3, %o4, %o5, %g2, %g3, %g4, %g5)
79 MIRROR_BLOCK(%o0, %o1, 0xa0, %o2, %o3, %o4, %o5, %g2, %g3, %g4, %g5)
80 MIRROR_BLOCK(%o0, %o1, 0xc0, %o2, %o3, %o4, %o5, %g2, %g3, %g4, %g5)
81 MIRROR_BLOCK(%o0, %o1, 0xe0, %o2, %o3, %o4, %o5, %g2, %g3, %g4, %g5)
H A Dcopy_user.S178 MOVE_BIGCHUNK(o1, o0, 0x00, o2, o3, o4, o5, g2, g3, g4, g5)
179 MOVE_BIGCHUNK(o1, o0, 0x20, o2, o3, o4, o5, g2, g3, g4, g5)
180 MOVE_BIGCHUNK(o1, o0, 0x40, o2, o3, o4, o5, g2, g3, g4, g5)
181 MOVE_BIGCHUNK(o1, o0, 0x60, o2, o3, o4, o5, g2, g3, g4, g5)
202 MOVE_LASTCHUNK(o1, o0, 0x60, g2, g3, g4, g5)
203 MOVE_LASTCHUNK(o1, o0, 0x50, g2, g3, g4, g5)
204 MOVE_LASTCHUNK(o1, o0, 0x40, g2, g3, g4, g5)
205 MOVE_LASTCHUNK(o1, o0, 0x30, g2, g3, g4, g5)
206 MOVE_LASTCHUNK(o1, o0, 0x20, g2, g3, g4, g5)
207 MOVE_LASTCHUNK(o1, o0, 0x10, g2, g3, g4, g5)
208 MOVE_LASTCHUNK(o1, o0, 0x00, g2, g3, g4, g5)
246 MOVE_BIGALIGNCHUNK(o1, o0, 0x00, o2, o3, o4, o5, g2, g3, g4, g5)
247 MOVE_BIGALIGNCHUNK(o1, o0, 0x20, o2, o3, o4, o5, g2, g3, g4, g5)
248 MOVE_BIGALIGNCHUNK(o1, o0, 0x40, o2, o3, o4, o5, g2, g3, g4, g5)
249 MOVE_BIGALIGNCHUNK(o1, o0, 0x60, o2, o3, o4, o5, g2, g3, g4, g5)
288 MOVE_HALFCHUNK(o1, o0, 0x00, g2, g3, g4, g5)
289 MOVE_HALFCHUNK(o1, o0, 0x08, g2, g3, g4, g5)
439 andn %g2, 7, %g4
443 sll %g4, 2, %g4
446 sub %g7, %g4, %g7
452 and %g2, 3, %g4
455 sll %g4, 1, %g4
458 add %g2, %g4, %g2
H A Dmemset.S70 mov 1, %g4
95 clr %g4
171 andcc %g4, 1, %g0
/linux-4.4.14/arch/sparc/mm/
H A Dhypersparc.S26 WINDOW_FLUSH(%g4, %g5)
27 sethi %hi(vac_cache_size), %g4
28 ld [%g4 + %lo(vac_cache_size)], %g5
45 WINDOW_FLUSH(%g4, %g5)
54 add %o1, %g3, %g4
55 add %o1, %g4, %g5
67 sta %g0, [%o0 + %g4] ASI_M_FLUSH_USER
83 WINDOW_FLUSH(%g4, %g5)
96 sub %o2, %o1, %g4
100 cmp %g4, %g5
101 add %o4, %g3, %g4
103 add %o4, %g4, %g5
117 sta %g0, [%o3 + %g4] ASI_M_FLUSH_USER
146 sta %g0, [%o2 + %g4] ASI_M_FLUSH_PAGE
172 WINDOW_FLUSH(%g4, %g5)
189 add %o4, %g3, %g4
190 add %o4, %g4, %g5
203 sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
208 mov SRMMU_CTX_REG, %g4
210 sta %o2, [%g4] ASI_M_MMUREGS
234 add %o4, %g3, %g4
235 add %o4, %g4, %g5
248 sta %g0, [%o0 + %g4] ASI_M_FLUSH_PAGE
333 mov 96, %g4
343 stda %g0, [%o0 + %g4] ASI_M_BFILL
H A Dswift.S42 WINDOW_FLUSH(%g4, %g5)
58 WINDOW_FLUSH(%g4, %g5)
124 WINDOW_FLUSH(%g4, %g5)
149 add %g3, 512, %g4
157 sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
195 add %g3, 512, %g4
203 sta %g0, [%o1 + %g4] ASI_M_FLUSH_PAGE
H A Dultra.S446 * %g4 scratch 4
453 srlx %g3, CTX_PGSZ1_NUC_SHIFT, %g4
454 sllx %g4, CTX_PGSZ1_NUC_SHIFT, %g4
455 or %g5, %g4, %g5 /* Preserve nucleus page size fields */
457 mov 0x40, %g4
458 stxa %g0, [%g4] ASI_DMMU_DEMAP
459 stxa %g0, [%g4] ASI_IMMU_DEMAP
476 mov PRIMARY_CONTEXT, %g4
477 ldxa [%g4] ASI_DMMU, %g2
478 srlx %g2, CTX_PGSZ1_NUC_SHIFT, %g4
479 sllx %g4, CTX_PGSZ1_NUC_SHIFT, %g4
480 or %g5, %g4, %g5
481 mov PRIMARY_CONTEXT, %g4
482 stxa %g5, [%g4] ASI_DMMU
489 stxa %g2, [%g4] ASI_DMMU
693 mov %g5, %g4
704 /* %g5=ctx, g1,g2,g3,g4,g7=scratch, %g6=unusable */
707 mov %o2, %g4
721 mov %g4, %o2
732 mov %o2, %g4
744 mov %g4, %o2
750 /* %g1=start, %g7=end, g2,g3,g4,g5,g6=scratch */
759 mov %o1, %g4
772 mov %g4, %o1
H A Dviking.S49 sll %o1, 5, %g4
50 or %g4, %o4, %g4 ! 0x80000000 | (set << 5)
54 or %g5, %g4, %g5
62 add %g4, %o3, %g2 ! (PAGE_OFFSET + PAGE_SIZE) | (set << 5)
122 WINDOW_FLUSH(%g4, %g5)
H A Dtsunami.S33 WINDOW_FLUSH(%g4, %g5)
/linux-4.4.14/arch/sparc/power/
H A Dhibernate_asm.S34 stx %g4, [%g3 + SC_REG_G4]
115 ldxa [%g3 + SC_REG_G4] %asi, %g4
/linux-4.4.14/crypto/
H A Dpoly1305_generic.c219 u32 g0, g1, g2, g3, g4; crypto_poly1305_final() local
251 g4 = h4 + (g3 >> 26) - (1 << 26); g3 &= 0x3ffffff; crypto_poly1305_final()
254 mask = (g4 >> ((sizeof(u32) * 8) - 1)) - 1; crypto_poly1305_final()
259 g4 &= mask; crypto_poly1305_final()
265 h4 = (h4 & mask) | g4; crypto_poly1305_final()
/linux-4.4.14/tools/perf/arch/sparc/util/
H A Ddwarf-regs.c18 "%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7",
/linux-4.4.14/arch/sparc/
H A DMakefile41 KBUILD_CFLAGS += -ffixed-g4 -ffixed-g5 -fcall-used-g7 -Wno-sign-compare
/linux-4.4.14/arch/x86/crypto/sha-mb/
H A Dsha1_x8_avx2.S78 # r6 = {g7 g6 g5 g4 g3 g2 g1 g0}
86 # r4 = {h4 g4 f4 e4 d4 c4 b4 a4}
107 vshufps $0x44, \r7, \r6, \t1 # t1 = {h5 h4 g5 g4 h1 h0 g1 g0}
112 vshufps $0x88, \t1, \r2, \t1 # t1 = {h4 g4 f4 e4 h0 g0 f0 e0}
/linux-4.4.14/drivers/mtd/nand/
H A Ddocg4.c607 "docg4: %s: g4 page %08x\n", __func__, docg4_addr); read_page_prologue()
634 "docg4: %s: g4 addr: %x\n", __func__, docg4_addr); write_page_prologue()
891 g4_page = (uint16_t)(page / 4); /* to g4's 2k page addressing */ docg4_erase_block()
1269 /* check for presence of g4 chip by reading id registers */ read_id_reg()
/linux-4.4.14/include/linux/
H A Dhyperv.h1010 #define VMBUS_DEVICE(g0, g1, g2, g3, g4, g5, g6, g7, \
1012 .guid = { g0, g1, g2, g3, g4, g5, g6, g7, \
/linux-4.4.14/drivers/media/platform/omap/
H A Domap_vout.c110 * g2 g1 g0 r4 r3 r2 r1 r0 b4 b3 b2 b1 b0 g5 g4 g3
115 * g2 g1 g0 b4 b3 b2 b1 b0 r4 r3 r2 r1 r0 g5 g4 g3
/linux-4.4.14/drivers/power/
H A Dbq27xxx_battery.c26 * http://www.ti.com/product/bq27520-g4
/linux-4.4.14/arch/powerpc/kernel/
H A Dmisc_32.S376 sync /* additional sync needed on g4 */
H A Dhead_32.S800 sync /* additional sync needed on g4 */
/linux-4.4.14/arch/arm/mach-omap2/
H A Dmux34xx.c1172 _OMAP3_BALLENTRY(GPMC_NCS7, "g4", NULL),
/linux-4.4.14/drivers/gpu/drm/radeon/
H A Dradeon_combios.c2160 DRM_INFO("Connector Table: %d (mac g4 silver)\n", radeon_get_legacy_connector_info_from_table()

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