Searched refs:fclk (Results 1 - 46 of 46) sorted by relevance

/linux-4.4.14/drivers/cpufreq/
H A Ds3c2410-cpufreq.c48 unsigned long hclk, fclk, pclk; s3c2410_cpufreq_calcdivs() local
52 fclk = cfg->freq.fclk; s3c2410_cpufreq_calcdivs()
55 cfg->freq.armclk = fclk; s3c2410_cpufreq_calcdivs()
57 s3c_freq_dbg("%s: fclk is %lu, max hclk %lu\n", s3c2410_cpufreq_calcdivs()
58 __func__, fclk, hclk_max); s3c2410_cpufreq_calcdivs()
60 hdiv = (fclk > cfg->max.hclk) ? 2 : 1; s3c2410_cpufreq_calcdivs()
61 hclk = fclk / hdiv; s3c2410_cpufreq_calcdivs()
87 .fclk = 200000000,
140 s3c2410_cpufreq_info.max.fclk = 266000000; s3c2410a_cpufreq_add()
H A Ds3c2440-cpufreq.c34 static struct clk *fclk; variable in typeref:struct:clk
58 unsigned long hclk, fclk, armclk; s3c2440_cpufreq_calcdivs() local
61 fclk = cfg->freq.fclk; s3c2440_cpufreq_calcdivs()
65 s3c_freq_dbg("%s: fclk is %lu, armclk %lu, max hclk %lu\n", s3c2440_cpufreq_calcdivs()
66 __func__, fclk, armclk, hclk_max); s3c2440_cpufreq_calcdivs()
68 if (armclk > fclk) { s3c2440_cpufreq_calcdivs()
69 printk(KERN_WARNING "%s: armclk > fclk\n", __func__); s3c2440_cpufreq_calcdivs()
70 armclk = fclk; s3c2440_cpufreq_calcdivs()
74 if (armclk < fclk && armclk < hclk_max) s3c2440_cpufreq_calcdivs()
81 hclk = (fclk / hdiv); s3c2440_cpufreq_calcdivs()
108 /* if we're running armclk lower than fclk, this really means s3c2440_cpufreq_calcdivs()
111 if (armclk < fclk) { s3c2440_cpufreq_calcdivs()
194 clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk); s3c2440_cpufreq_setdivs()
197 static int run_freq_for(unsigned long max_hclk, unsigned long fclk, run_freq_for() argument
207 freq = fclk / div; run_freq_for()
233 cfg->info->max.fclk, s3c2440_cpufreq_calctable()
244 .fclk = 400000000,
272 fclk = s3c_cpufreq_clk_get(NULL, "fclk"); s3c2440_cpufreq_add()
275 if (IS_ERR(xtal) || IS_ERR(hclk) || IS_ERR(fclk) || IS_ERR(armclk)) { s3c2440_cpufreq_add()
H A Ds3c2412-cpufreq.c35 static struct clk *fclk; variable in typeref:struct:clk
44 unsigned long hclk, fclk, armclk, armdiv_clk; s3c2412_cpufreq_calcdivs() local
47 fclk = cfg->freq.fclk; s3c2412_cpufreq_calcdivs()
57 s3c_freq_dbg("%s: fclk=%lu, armclk=%lu, hclk_max=%lu\n", s3c2412_cpufreq_calcdivs()
58 __func__, fclk, armclk, hclk_max); s3c2412_cpufreq_calcdivs()
60 __func__, cfg->freq.fclk, cfg->freq.armclk, s3c2412_cpufreq_calcdivs()
63 armdiv = fclk / armclk; s3c2412_cpufreq_calcdivs()
71 armdiv_clk = fclk / armdiv; s3c2412_cpufreq_calcdivs()
140 clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk); s3c2412_cpufreq_setdivs()
170 .fclk = 200000000,
204 fclk = clk_get(NULL, "fclk"); s3c2412_cpufreq_add()
205 if (IS_ERR(fclk)) { s3c2412_cpufreq_add()
206 printk(KERN_ERR "%s: cannot find fclk clock\n", __func__); s3c2412_cpufreq_add()
210 fclk_rate = clk_get_rate(fclk); s3c2412_cpufreq_add()
213 "%s: fclk %ld MHz, assuming 266MHz capable part\n", s3c2412_cpufreq_add()
215 s3c2412_cpufreq_info.max.fclk = 266000000; s3c2412_cpufreq_add()
237 clk_put(fclk); s3c2412_cpufreq_add()
H A Ds3c24xx-cpufreq.c65 unsigned long fclk, pclk, hclk, armclk; s3c_cpufreq_getcur() local
67 cfg->freq.fclk = fclk = clk_get_rate(clk_fclk); s3c_cpufreq_getcur()
73 cfg->pll.frequency = fclk; s3c_cpufreq_getcur()
77 cfg->divs.h_divisor = fclk / hclk; s3c_cpufreq_getcur()
78 cfg->divs.p_divisor = fclk / pclk; s3c_cpufreq_getcur()
85 cfg->freq.fclk = pll; s3c_cpufreq_calc()
105 pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk, s3c_cpufreq_show()
175 cpu_new.freq.fclk = cpu_new.pll.frequency; s3c_cpufreq_settarget()
210 s3c_cpufreq_updateclk(clk_fclk, cpu_new.freq.fclk); s3c_cpufreq_settarget()
229 if (cpu_new.freq.fclk == cpu_cur.freq.fclk) { s3c_cpufreq_settarget()
234 if (cpu_new.freq.fclk < cpu_cur.freq.fclk) { s3c_cpufreq_settarget()
374 clk_fclk = s3c_cpufreq_clk_get(NULL, "fclk"); s3c_cpufreq_initclks()
534 dst->fclk = do_min(a->fclk, b->fclk); s3c_cpufreq_freq_min()
H A Ds3c24xx-cpufreq-debugfs.c34 f->fclk, f->hclk, f->pclk, f->armclk); show_max()
87 seq_printf(seq, " FCLK %ld Hz\n", cfg->freq.fclk); info_show()
/linux-4.4.14/drivers/usb/host/
H A Dehci-sh.c17 struct clk *iclk, *fclk; member in struct:ehci_sh_priv
125 priv->fclk = devm_clk_get(&pdev->dev, "usb_fck"); ehci_hcd_sh_probe()
126 if (IS_ERR(priv->fclk)) ehci_hcd_sh_probe()
127 priv->fclk = NULL; ehci_hcd_sh_probe()
133 clk_enable(priv->fclk); ehci_hcd_sh_probe()
153 clk_disable(priv->fclk); ehci_hcd_sh_probe()
171 clk_disable(priv->fclk); ehci_hcd_sh_remove()
H A Dohci-at91.c52 struct clk *fclk; member in struct:ohci_at91_priv
78 clk_set_rate(ohci_at91->fclk, 48000000); at91_start_clock()
81 clk_prepare_enable(ohci_at91->fclk); at91_start_clock()
90 clk_disable_unprepare(ohci_at91->fclk); at91_stop_clock()
189 ohci_at91->fclk = devm_clk_get(dev, "uhpck"); usb_hcd_at91_probe()
190 if (IS_ERR(ohci_at91->fclk)) { usb_hcd_at91_probe()
192 retval = PTR_ERR(ohci_at91->fclk); usb_hcd_at91_probe()
/linux-4.4.14/drivers/media/dvb-frontends/
H A Dmb86a20s.h25 * @fclk: Clock frequency. If zero, assumes the default
32 u32 fclk; member in struct:mb86a20s_config
H A Ds5h1420.c53 u32 fclk; member in struct:s5h1420_state
382 tmp = state->fclk / tmp; s5h1420_read_status()
489 do_div(val, (state->fclk / 1000)); s5h1420_setsymbolrate()
515 * divide fclk by 1000000 to get the correct value. */ s5h1420_setfreqoffset()
516 val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000)); s5h1420_setfreqoffset()
543 * divide fclk by 1000000 to get the correct value. */ s5h1420_getfreqoffset()
544 val = (((-val) * (state->fclk/1000000)) / (1<<24)); s5h1420_getfreqoffset()
680 /* set s5h1420 fclk PLL according to desired symbol rate */ s5h1420_set_frontend()
682 state->fclk = 80000000; s5h1420_set_frontend()
684 state->fclk = 59000000; s5h1420_set_frontend()
686 state->fclk = 86000000; s5h1420_set_frontend()
688 state->fclk = 88000000; s5h1420_set_frontend()
690 state->fclk = 44000000; s5h1420_set_frontend()
692 dprintk("pll01: %d, ToneFreq: %d\n", state->fclk/1000000 - 8, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32)); s5h1420_set_frontend()
693 s5h1420_writereg(state, PLL01, state->fclk/1000000 - 8); s5h1420_set_frontend()
695 s5h1420_writereg(state, DiS01, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32)); s5h1420_set_frontend()
899 state->fclk = 88000000; s5h1420_attach()
H A Dcx24110.c244 u32 tmp, fclk, BDRI; cx24110_set_symbolrate() local
264 fclk=90999000UL/2; cx24110_set_symbolrate()
268 fclk=60666000UL; cx24110_set_symbolrate()
272 fclk=80888000UL; cx24110_set_symbolrate()
276 fclk=90999000UL; cx24110_set_symbolrate()
278 dprintk("cx24110 debug: fclk %d Hz\n",fclk); cx24110_set_symbolrate()
288 BDRI=fclk>>2; cx24110_set_symbolrate()
301 dprintk("fclk = %d\n", fclk); cx24110_set_symbolrate()
H A Dmb86a20s.c1767 u32 fclk; mb86a20s_initfe() local
1802 fclk = state->config->fclk; mb86a20s_initfe()
1803 if (!fclk) mb86a20s_initfe()
1804 fclk = 32571428; mb86a20s_initfe()
1814 do_div(pll, 63 * fclk); mb86a20s_initfe()
1828 dev_dbg(&state->i2c->dev, "%s: fclk=%d, IF=%d, clock reg=0x%06llx\n", mb86a20s_initfe()
1829 __func__, fclk, state->if_freq, (long long)pll); mb86a20s_initfe()
/linux-4.4.14/drivers/clk/samsung/
H A Dclk-s3c2410.c99 MUX(FCLK, "fclk", fclk_p, CLKSLOW, 4, 1),
152 ALIAS(FCLK, NULL, "fclk"),
209 * armclk is directly supplied by the fclk, without
212 FFACTOR(ARMCLK, "armclk", "fclk", 1, 1, 0),
269 PNAME(hclk_p) = { "fclk", "div_hclk_2", "div_hclk_4", "div_hclk_3" };
270 PNAME(armclk_p) = { "fclk", "hclk" };
278 FFACTOR(0, "div_hclk_2", "fclk", 1, 2, 0),
296 DIV(0, "div_hclk", "fclk", CLKDIVN, 1, 1),
297 DIV_T(0, "div_hclk_4", "fclk", CAMDIVN, 9, 1, div_hclk_4_d),
298 DIV_T(0, "div_hclk_3", "fclk", CAMDIVN, 8, 1, div_hclk_3_d),
H A Dclk-s3c2410-dclk.c143 static const char *clkout0_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
145 static const char *clkout1_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
150 static const char *clkout1_s3c2412_p[] = { "xti", "upll", "fclk", "hclk", "pclk",
153 static const char *clkout0_s3c2440_p[] = { "xti", "upll", "fclk", "hclk", "pclk",
H A Dclk-exynos4.c1234 struct samsung_fixed_rate_clock fclk; exynos4_clk_register_finpll() local
1250 fclk.id = CLK_FIN_PLL; exynos4_clk_register_finpll()
1251 fclk.name = "fin_pll"; exynos4_clk_register_finpll()
1252 fclk.parent_name = NULL; exynos4_clk_register_finpll()
1253 fclk.flags = CLK_IS_ROOT; exynos4_clk_register_finpll()
1254 fclk.fixed_rate = finpll_f; exynos4_clk_register_finpll()
1255 samsung_clk_register_fixed_rate(ctx, &fclk, 1); exynos4_clk_register_finpll()
H A Dclk-s3c2412.c204 ALIAS(MSYSCLK, NULL, "fclk"),
/linux-4.4.14/sound/soc/omap/
H A Domap-dmic.c50 struct clk *fclk; member in struct:omap_dmic
322 dev_err(dmic->dev, "fclk clk_id (%d) not supported\n", clk_id); omap_dmic_select_fclk()
336 ret = clk_set_parent(dmic->fclk, parent_clk); omap_dmic_select_fclk()
339 ret = clk_set_parent(dmic->fclk, parent_clk); omap_dmic_select_fclk()
469 dmic->fclk = devm_clk_get(dmic->dev, "fck"); asoc_dmic_probe()
470 if (IS_ERR(dmic->fclk)) { asoc_dmic_probe()
H A Dmcbsp.c748 r = clk_set_parent(mcbsp->fclk, fck_src); omap2_mcbsp_set_clks_src()
1031 mcbsp->fclk = clk_get(&pdev->dev, "fck"); omap_mcbsp_init()
1032 if (IS_ERR(mcbsp->fclk)) { omap_mcbsp_init()
1033 ret = PTR_ERR(mcbsp->fclk); omap_mcbsp_init()
1079 clk_put(mcbsp->fclk); omap_mcbsp_init()
H A Dmcbsp.h293 struct clk *fclk; member in struct:omap_mcbsp
H A Domap-mcbsp.c837 clk_put(mcbsp->fclk); asoc_mcbsp_remove()
/linux-4.4.14/arch/sh/drivers/pci/
H A Dpcie-sh7786.c27 struct clk *fclk, phy_clk; member in struct:sh7786_pcie_port
223 port->fclk = clk_get(NULL, fclk_name); pcie_clk_init()
224 if (IS_ERR(port->fclk)) { pcie_clk_init()
225 ret = PTR_ERR(port->fclk); pcie_clk_init()
229 clk_enable(port->fclk); pcie_clk_init()
249 clk_disable(port->fclk); pcie_clk_init()
250 clk_put(port->fclk); pcie_clk_init()
/linux-4.4.14/arch/arm/plat-omap/
H A Ddmtimer.c149 timer->fclk = clk_get(&timer->pdev->dev, "fck"); omap_dm_timer_prepare()
150 if (WARN_ON_ONCE(IS_ERR(timer->fclk))) { omap_dm_timer_prepare()
151 dev_err(&timer->pdev->dev, ": No fclk handle.\n"); omap_dm_timer_prepare()
326 clk_put(timer->fclk); omap_dm_timer_free()
408 if (timer && !IS_ERR(timer->fclk)) omap_dm_timer_get_fclk()
409 return timer->fclk; omap_dm_timer_get_fclk()
465 rate = clk_get_rate(timer->fclk); omap_dm_timer_stop()
504 if (IS_ERR(timer->fclk)) omap_dm_timer_set_source()
527 ret = clk_set_parent(timer->fclk, parent); omap_dm_timer_set_source()
830 timer->fclk = ERR_PTR(-ENODEV); omap_dm_timer_probe()
/linux-4.4.14/drivers/clk/zynq/
H A Dclkc.c113 static void __init zynq_clk_register_fclk(enum zynq_clk fclk, zynq_clk_register_fclk() argument
158 clks[fclk] = clk_register_gate(NULL, clk_name, zynq_clk_register_fclk()
163 if (clk_prepare_enable(clks[fclk])) zynq_clk_register_fclk()
165 fclk - fclk0); zynq_clk_register_fclk()
182 clks[fclk] = ERR_PTR(-ENOMEM); zynq_clk_register_fclk()
260 of_property_read_u32(np, "fclk-enable", &fclk_enable); zynq_clk_setup()
/linux-4.4.14/drivers/net/hamradio/
H A Dbaycom_epp.c182 unsigned int fclk; member in struct:baycom_state::__anon7914
315 sprintf(modearg, "%sclk,%smodem,fclk=%d,bps=%d,divider=%d%s,extstat", eppconfig()
317 bc->cfg.extmodem ? "ext" : "int", bc->cfg.fclk, bc->cfg.bps, eppconfig()
318 (bc->cfg.fclk + 8 * bc->cfg.bps) / (16 * bc->cfg.bps), eppconfig()
984 if ((cp = strstr(modestr,"fclk="))) { baycom_setmode()
985 bc->cfg.fclk = simple_strtoul(cp+5, NULL, 0); baycom_setmode()
986 if (bc->cfg.fclk < 1000000) baycom_setmode()
987 bc->cfg.fclk = 1000000; baycom_setmode()
988 if (bc->cfg.fclk > 25000000) baycom_setmode()
989 bc->cfg.fclk = 25000000; baycom_setmode()
1081 sprintf(hi.data.modename, "%sclk,%smodem,fclk=%d,bps=%d%s", baycom_ioctl()
1083 bc->cfg.extmodem ? "ext" : "int", bc->cfg.fclk, bc->cfg.bps, baycom_ioctl()
1191 bc->cfg.fclk = 19666600; baycom_epp_dev_setup()
/linux-4.4.14/drivers/clk/imx/
H A Dclk-imx1.c36 "prem", "fclk", };
61 clk[IMX1_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1); _mx1_clocks_init()
H A Dclk-imx21.c61 clk[IMX21_CLK_HCLK] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4); _mx21_clocks_init()
67 clk[IMX21_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 29, 3); _mx21_clocks_init()
73 clk[IMX21_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "fclk", CCM_PCDR0, 12, 4); _mx21_clocks_init()
/linux-4.4.14/arch/arm/plat-samsung/include/plat/
H A Dcpu-freq.h22 * @fclk: The FCLK frequency in Hz.
36 unsigned long fclk; member in struct:s3c_freq
/linux-4.4.14/drivers/spi/
H A Dspi-ti-qspi.c49 struct clk *fclk; member in struct:ti_qspi
142 clk_rate = clk_get_rate(qspi->fclk); ti_qspi_setup()
542 qspi->fclk = devm_clk_get(&pdev->dev, "fck"); ti_qspi_probe()
543 if (IS_ERR(qspi->fclk)) { ti_qspi_probe()
544 ret = PTR_ERR(qspi->fclk); ti_qspi_probe()
/linux-4.4.14/drivers/mmc/host/
H A Domap.c129 struct clk * fclk; member in struct:mmc_omap_host
193 clk_enable(host->fclk); mmc_omap_fclk_enable()
195 clk_disable(host->fclk); mmc_omap_fclk_enable()
1130 int func_clk_rate = clk_get_rate(host->fclk); mmc_omap_calc_divisor()
1379 host->fclk = clk_get(&pdev->dev, "fck"); mmc_omap_probe()
1380 if (IS_ERR(host->fclk)) { mmc_omap_probe()
1381 ret = PTR_ERR(host->fclk); mmc_omap_probe()
1452 clk_put(host->fclk); mmc_omap_probe()
1474 clk_put(host->fclk); mmc_omap_remove()
H A Domap_hsmmc.c182 struct clk *fclk; member in struct:omap_hsmmc_host
621 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); calc_divisor()
668 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) omap_hsmmc_set_clock()
1626 host->clk_rate = clk_get_rate(host->fclk); omap_hsmmc_request()
2082 host->fclk = devm_clk_get(&pdev->dev, "fck"); omap_hsmmc_probe()
2083 if (IS_ERR(host->fclk)) { omap_hsmmc_probe()
2084 ret = PTR_ERR(host->fclk); omap_hsmmc_probe()
2085 host->fclk = NULL; omap_hsmmc_probe()
/linux-4.4.14/drivers/i2c/busses/
H A Di2c-omap.c363 struct clk *fclk; omap_i2c_init() local
381 fclk = clk_get(omap->dev, "fck"); omap_i2c_init()
382 fclk_rate = clk_get_rate(fclk); omap_i2c_init()
383 clk_put(fclk); omap_i2c_init()
404 * The filter is iclk (fclk for HS) period. omap_i2c_init()
413 fclk = clk_get(omap->dev, "fck"); omap_i2c_init()
414 fclk_rate = clk_get_rate(fclk) / 1000; omap_i2c_init()
415 clk_put(fclk); omap_i2c_init()
/linux-4.4.14/arch/arm/mach-omap2/
H A Dtimer.c293 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh)); omap_dm_timer_init_one()
294 if (IS_ERR(timer->fclk)) omap_dm_timer_init_one()
295 return PTR_ERR(timer->fclk); omap_dm_timer_init_one()
301 WARN(clk_set_parent(timer->fclk, src) < 0, omap_dm_timer_init_one()
317 timer->rate = clk_get_rate(timer->fclk); omap_dm_timer_init_one()
H A Dprm3xxx.c232 u32 wkst, fclk, iclk, clken; omap3xxx_prm_clear_mod_irqs() local
245 fclk = omap2_cm_read_mod_reg(module, fclk_off); omap3xxx_prm_clear_mod_irqs()
262 omap2_cm_write_mod_reg(fclk, module, fclk_off); omap3xxx_prm_clear_mod_irqs()
H A Domap_hwmod_2430_data.c95 * the iclk and fclk. Needs to be handled using
/linux-4.4.14/drivers/usb/gadget/udc/
H A Dat91_udc.h142 struct clk *iclk, *fclk; member in struct:at91_udc
H A Dat91_udc.c920 clk_enable(udc->fclk); clk_on()
929 clk_disable(udc->fclk); clk_off()
1880 udc->fclk = devm_clk_get(dev, "hclk"); at91udc_probe()
1881 if (IS_ERR(udc->fclk)) at91udc_probe()
1882 return PTR_ERR(udc->fclk); at91udc_probe()
1885 clk_set_rate(udc->fclk, 48000000); at91udc_probe()
1886 retval = clk_prepare(udc->fclk); at91udc_probe()
1959 clk_unprepare(udc->fclk); at91udc_probe()
1983 clk_unprepare(udc->fclk); at91udc_remove()
/linux-4.4.14/drivers/video/fbdev/omap2/dss/
H A Dsdi.c88 * DSS fclk gives us very few possibilities, so finding a good pixel sdi_calc_clock_div()
H A Ddispc.c3412 seq_printf(s, "dispc fclk source = %s (%s)\n", dispc_dump_clocks()
3656 * For OMAP2/3 the DISPC fclk is the same as LCD's logic dispc_div_calc()
3657 * clock, which means we're configuring DISPC fclk here dispc_div_calc()
3659 * OMAP4+ the DISPC fclk is a separate clock. dispc_div_calc()
H A Ddpi.c76 * would also be used for DISPC fclk. Meaning, when the DPI output is dpi_get_pll()
H A Ddsi.c1526 seq_printf(s, "dsi fclk source = %s (%s)\n", dsi_dump_dsidev_clocks()
/linux-4.4.14/drivers/tty/serial/
H A Dsh-sci.c97 struct clk *fclk; member in struct:sci_port
459 clk_prepare_enable(sci_port->fclk); sci_port_enable()
475 clk_disable_unprepare(sci_port->fclk); sci_port_disable()
2323 sci_port->fclk = clk_get(&dev->dev, "sci_fck"); sci_init_single()
2324 if (IS_ERR(sci_port->fclk)) sci_init_single()
2325 sci_port->fclk = NULL; sci_init_single()
2383 clk_put(port->fclk); sci_cleanup_single()
H A Dsamsung.c1107 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
/linux-4.4.14/drivers/clk/
H A Dclk-stm32f4.c351 clks[FCLK] = clk_register_fixed_factor(NULL, "fclk", "ahb_div", stm32f4_rcc_init()
/linux-4.4.14/drivers/thermal/ti-soc-thermal/
H A Dti-bandgap.h229 * @div_clk: pointer to divider clock of temperature sensor fclk
/linux-4.4.14/arch/arm/plat-omap/include/plat/
H A Ddmtimer.h105 struct clk *fclk; member in struct:omap_dm_timer
/linux-4.4.14/arch/arm/mach-ep93xx/
H A Dclock.c211 INIT_CK(NULL, "fclk", &clk_f),
/linux-4.4.14/drivers/power/avs/
H A Dsmartreflex.c163 dev_err(&sr->pdev->dev, "%s: Invalid fclk rate: %d\n", sr_set_clk_length()

Completed in 2289 milliseconds