/linux-4.4.14/drivers/gpu/drm/radeon/ |
H A D | trinity_dpm.c | 993 if ((old_rps->evclk != new_rps->evclk) || trinity_set_vce_clock() 996 if (new_rps->evclk || new_rps->ecclk) trinity_set_vce_clock() 1000 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); trinity_set_vce_clock() 1504 u32 evclk, u32 ecclk, u16 *voltage) trinity_get_vce_clock_voltage() 1511 if (((evclk == 0) && (ecclk == 0)) || trinity_get_vce_clock_voltage() 1518 if ((evclk <= table->entries[i].evclk) && trinity_get_vce_clock_voltage() 1554 new_rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; trinity_apply_state_adjust_rules() 1557 new_rps->evclk = 0; trinity_apply_state_adjust_rules() 1575 trinity_get_vce_clock_voltage(rdev, new_rps->evclk, new_rps->ecclk, &min_vce_voltage); trinity_apply_state_adjust_rules() 1503 trinity_get_vce_clock_voltage(struct radeon_device *rdev, u32 evclk, u32 ecclk, u16 *voltage) trinity_get_vce_clock_voltage() argument
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H A D | kv_dpm.c | 906 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk); kv_populate_vce_table() 910 (u8)kv_get_clk_bypass(rdev, table->entries[i].evclk); kv_populate_vce_table() 913 table->entries[i].evclk, false, ÷rs); kv_populate_vce_table() 1459 static u8 kv_get_vce_boot_level(struct radeon_device *rdev, u32 evclk) kv_get_vce_boot_level() argument 1466 if (table->entries[i].evclk >= evclk) kv_get_vce_boot_level() 1482 if (radeon_new_state->evclk > 0 && radeon_current_state->evclk == 0) { kv_update_vce_dpm() 1489 pi->vce_boot_level = kv_get_vce_boot_level(rdev, radeon_new_state->evclk); kv_update_vce_dpm() 1506 } else if (radeon_new_state->evclk == 0 && radeon_current_state->evclk > 0) { kv_update_vce_dpm() 2154 new_rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; kv_apply_state_adjust_rules() 2157 new_rps->evclk = 0; kv_apply_state_adjust_rules() 2222 new_rps->evclk || new_rps->ecclk; kv_apply_state_adjust_rules()
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H A D | si_dpm.c | 2957 u32 evclk, u32 ecclk, u16 *voltage) si_get_vce_clock_voltage() 2964 if (((evclk == 0) && (ecclk == 0)) || si_get_vce_clock_voltage() 2971 if ((evclk <= table->entries[i].evclk) && si_get_vce_clock_voltage() 3020 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; si_apply_state_adjust_rules() 3022 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, si_apply_state_adjust_rules() 3025 rps->evclk = 0; si_apply_state_adjust_rules() 5945 if ((old_rps->evclk != new_rps->evclk) || si_set_vce_clock() 5948 if (new_rps->evclk || new_rps->ecclk) si_set_vce_clock() 5952 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); si_set_vce_clock() 2956 si_get_vce_clock_voltage(struct radeon_device *rdev, u32 evclk, u32 ecclk, u16 *voltage) si_get_vce_clock_voltage() argument
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H A D | radeon_asic.h | 697 int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk); 749 int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk); 787 int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
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H A D | ci_dpm.c | 797 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; ci_apply_state_adjust_rules() 800 rps->evclk = 0; ci_apply_state_adjust_rules() 2673 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk; ci_populate_smc_vce_level() 4074 if (table->entries[i].evclk >= min_evclk) ci_get_vce_boot_level() 4089 if (radeon_current_state->evclk != radeon_new_state->evclk) { ci_update_vce_dpm() 4090 if (radeon_new_state->evclk) { ci_update_vce_dpm()
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H A D | r600_dpm.c | 1104 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].evclk = r600_parse_extended_power_table() 1119 rdev->pm.dpm.vce_states[i].evclk = r600_parse_extended_power_table()
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H A D | radeon.h | 1355 u32 evclk; member in struct:radeon_ps 1450 u32 evclk; member in struct:radeon_vce_clock_voltage_dependency_entry 1539 u32 evclk; member in struct:radeon_vce_state 1967 int (*set_vce_clocks)(struct radeon_device *rdev, u32 evclk, u32 ecclk);
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H A D | si.c | 7807 int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) si_set_vce_clocks() argument 7812 /* bypass evclk and ecclk with bclk */ si_set_vce_clocks() 7821 if (!evclk || !ecclk) { si_set_vce_clocks() 7828 r = radeon_uvd_calc_upll_dividers(rdev, evclk, ecclk, 125000, 250000, si_set_vce_clocks()
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H A D | ni.c | 2632 int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) tn_set_vce_clocks() argument
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H A D | cik.c | 9750 int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) cik_set_vce_clocks() argument
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/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/ |
H A D | kv_dpm.c | 995 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk); kv_populate_vce_table() 999 (u8)kv_get_clk_bypass(adev, table->entries[i].evclk); kv_populate_vce_table() 1002 table->entries[i].evclk, false, ÷rs); kv_populate_vce_table() 1529 static u8 kv_get_vce_boot_level(struct amdgpu_device *adev, u32 evclk) kv_get_vce_boot_level() argument 1536 if (table->entries[i].evclk >= evclk) kv_get_vce_boot_level() 1552 if (amdgpu_new_state->evclk > 0 && amdgpu_current_state->evclk == 0) { kv_update_vce_dpm() 1562 pi->vce_boot_level = kv_get_vce_boot_level(adev, amdgpu_new_state->evclk); kv_update_vce_dpm() 1579 } else if (amdgpu_new_state->evclk == 0 && amdgpu_current_state->evclk > 0) { kv_update_vce_dpm() 2248 new_rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; kv_apply_state_adjust_rules() 2251 new_rps->evclk = 0; kv_apply_state_adjust_rules() 2316 new_rps->evclk || new_rps->ecclk; kv_apply_state_adjust_rules()
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H A D | amdgpu.h | 1376 u32 evclk; member in struct:amdgpu_ps 1473 u32 evclk; member in struct:amdgpu_vce_clock_voltage_dependency_entry 1563 u32 evclk; member in struct:amdgpu_vce_state 1845 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
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H A D | amdgpu_dpm.c | 545 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].evclk = amdgpu_parse_extended_power_table() 560 adev->pm.dpm.vce_states[i].evclk = amdgpu_parse_extended_power_table()
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H A D | ci_dpm.c | 914 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk; ci_apply_state_adjust_rules() 917 rps->evclk = 0; ci_apply_state_adjust_rules() 2803 adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk; ci_populate_smc_vce_level() 4212 if (table->entries[i].evclk >= min_evclk) ci_get_vce_boot_level() 4227 if (amdgpu_current_state->evclk != amdgpu_new_state->evclk) { ci_update_vce_dpm() 4228 if (amdgpu_new_state->evclk) { ci_update_vce_dpm()
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H A D | vi.c | 1014 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) vi_set_vce_clocks() argument
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H A D | cik.c | 1525 static int cik_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) cik_set_vce_clocks() argument
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H A D | cz_dpm.c | 1249 new_rps->evclk || new_rps->ecclk; cz_apply_state_adjust_rules()
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