| /linux-4.4.14/drivers/gpu/drm/radeon/ |
| D | rv770_dpm.h | 180 u32 engine_clock,
183 u32 engine_clock, u32 memory_clock,
201 int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock,
204 u32 engine_clock, u32 memory_clock,
226 u32 engine_clock);
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| D | rv740_dpm.c | 121 int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, in rv740_populate_sclk_value() argument
138 engine_clock, false, ÷rs); in rv740_populate_sclk_value()
144 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in rv740_populate_sclk_value()
161 u32 vco_freq = engine_clock * dividers.post_div; in rv740_populate_sclk_value()
177 sclk->sclk_value = cpu_to_be32(engine_clock); in rv740_populate_sclk_value()
188 u32 engine_clock, u32 memory_clock, in rv740_populate_mclk_value() argument
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| D | rv730_dpm.c | 41 u32 engine_clock, in rv730_populate_sclk_value() argument
58 engine_clock, false, ÷rs); in rv730_populate_sclk_value()
70 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv730_populate_sclk_value()
93 u32 vco_freq = engine_clock * post_divider; in rv730_populate_sclk_value()
109 sclk->sclk_value = cpu_to_be32(engine_clock); in rv730_populate_sclk_value()
120 u32 engine_clock, u32 memory_clock, in rv730_populate_mclk_value() argument
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| D | cypress_dpm.h | 125 u32 engine_clock, u32 memory_clock);
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| D | rv770_dpm.c | 387 u32 engine_clock, u32 memory_clock, in rv770_populate_mclk_value() argument
485 u32 engine_clock, in rv770_populate_sclk_value() argument
507 engine_clock, false, ÷rs); in rv770_populate_sclk_value()
518 tmp = (u64) engine_clock * reference_divider * post_divider * 16384; in rv770_populate_sclk_value()
540 u32 vco_freq = engine_clock * post_divider; in rv770_populate_sclk_value()
556 sclk->sclk_value = cpu_to_be32(engine_clock); in rv770_populate_sclk_value()
723 u32 engine_clock) in rv770_calculate_memory_refresh_rate() argument
734 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; in rv770_calculate_memory_refresh_rate()
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| D | ci_dpm.c | 2466 const u32 engine_clock, in ci_register_patching_mc_arb() argument
2480 tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff; in ci_register_patching_mc_arb()
2484 tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff; in ci_register_patching_mc_arb()
3130 u32 engine_clock, in ci_calculate_sclk_params() argument
3146 engine_clock, false, ÷rs); in ci_calculate_sclk_params()
3159 u32 vco_freq = engine_clock * dividers.post_div; in ci_calculate_sclk_params()
3175 sclk->SclkFrequency = engine_clock; in ci_calculate_sclk_params()
3186 u32 engine_clock, in ci_populate_single_graphic_level() argument
3193 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level); in ci_populate_single_graphic_level()
3199 engine_clock, &graphic_level->MinVddc); in ci_populate_single_graphic_level()
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| D | ni_dpm.c | 1999 u32 engine_clock, in ni_calculate_sclk_params() argument
2018 engine_clock, false, ÷rs); in ni_calculate_sclk_params()
2025 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834; in ni_calculate_sclk_params()
2042 u32 vco_freq = engine_clock * dividers.post_div; in ni_calculate_sclk_params()
2058 sclk->sclk_value = engine_clock; in ni_calculate_sclk_params()
2070 u32 engine_clock, in ni_populate_sclk_value() argument
2076 ret = ni_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); in ni_populate_sclk_value()
2161 u32 engine_clock, in ni_populate_mclk_value() argument
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| D | si_dpm.c | 1757 u32 engine_clock,
4287 u32 engine_clock) in si_calculate_memory_refresh_rate() argument
4300 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; in si_calculate_memory_refresh_rate()
4795 u32 engine_clock, in si_calculate_sclk_params() argument
4814 engine_clock, false, ÷rs); in si_calculate_sclk_params()
4820 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; in si_calculate_sclk_params()
4837 u32 vco_freq = engine_clock * dividers.post_div; in si_calculate_sclk_params()
4853 sclk->sclk_value = engine_clock; in si_calculate_sclk_params()
4865 u32 engine_clock, in si_populate_sclk_value() argument
4871 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); in si_populate_sclk_value()
[all …]
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| D | cypress_dpm.c | 474 u32 engine_clock, u32 memory_clock, in cypress_populate_mclk_value() argument
904 u32 engine_clock, u32 memory_clock) in cypress_calculate_burst_time() argument
908 u32 result = (4 * multiplier * engine_clock) / (memory_clock / 2); in cypress_calculate_burst_time()
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| D | rv6xx_dpm.c | 783 u32 engine_clock) in calculate_memory_refresh_rate() argument
792 return ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; in calculate_memory_refresh_rate()
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| /linux-4.4.14/drivers/gpu/drm/amd/amdgpu/ |
| D | ci_dpm.c | 2597 const u32 engine_clock, in ci_register_patching_mc_arb() argument
2611 tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff; in ci_register_patching_mc_arb()
2615 tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff; in ci_register_patching_mc_arb()
3268 u32 engine_clock, in ci_calculate_sclk_params() argument
3284 engine_clock, false, ÷rs); in ci_calculate_sclk_params()
3297 u32 vco_freq = engine_clock * dividers.post_div; in ci_calculate_sclk_params()
3313 sclk->SclkFrequency = engine_clock; in ci_calculate_sclk_params()
3324 u32 engine_clock, in ci_populate_single_graphic_level() argument
3331 ret = ci_calculate_sclk_params(adev, engine_clock, graphic_level); in ci_populate_single_graphic_level()
3337 engine_clock, &graphic_level->MinVddc); in ci_populate_single_graphic_level()
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